RISC-V Assembly - I

Computer Architectures

Department of Information Engineering and Computer Science

Prof. Kasim Sinan Yildirim
Instruction Set
● The repertoire of instructions of a computer
● Different computers have different instruction sets
○ But with many aspects in common
● Early computers had very simple instruction sets
○ Simplified implementation
● Many modern computers also have simple instruction sets

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We will see many ISAs
● Intel ISA
○ Millions of PCs are based on Intel or Intel compatible architecture
○ It's a paradigmatic example of CISC architecture
● ARM
○ middle ground between CISC and RISC
○ Used in many embedded systems
● RISC-V
○ precisely RISC, modern, open-source

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The RISC-V Instruction Set
● Developed at UC Berkeley as open ISA
● Now managed by the RISC-V Foundation (riscv.org)
● Similar ISAs have a large share of embedded core market
○ Applications in consumer electronics, network/storage equipment, cameras,
printers, …

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Arithmetic Operations
● Add and subtract, three operands
○ Two sources and one destination
add a, b, c // a gets b + c
● All arithmetic operations have this form
○ Each RISC-V arithmetic instruction performs only one operation and must
always have exactly three variables.
● Design Principle 1: Simplicity favours regularity
○ Regularity makes implementation simpler
○ Simplicity enables higher performance at lower cost

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Assembly language notation
● Each line of this language can contain at most one instruction.
add a, b, c // The sum of b and c is placed in a
add a, a, d // The sum of b, c, and d is now in a
add a, a, e // The sum of b, c, d, and e is now in a
● Comments always terminate at the end of a line.

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Arithmetic Example
● We want to place the sum of four variables b, c, d, and e into variable a.
● The following sequence of instructions adds the four variables:

add a, b, c // The sum of b and c is placed in a

add a, a, d // The sum of b, c, and d is now in a
add a, a, e // The sum of b, c, d, and e is now in a

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Arithmetic Example
● C code: a = b + c;
d = a − e;
● The compiler translates from C to RISC-V assembly language instructions.

add a, b, c
sub d, a, e

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Arithmetic Example
● C code: f = (g + h) - (i + j);
● Compiled RISC-V code:
add t0, g, h // temp t0 = g + h
add t1, i, j // temp t1 = i + j
sub f, t0, t1 // f = t0 - t1
● The compiler must break this statement into several assembly
instructions:
○ Since only one operation is performed per RISC-V instruction!

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Operands of the Computer Hardware
● We have operands in arithmetic instructions :
add a, b, c // a gets b + c
● Where are do these operands stay?

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Operands of the Computer Hardware
● We have operands in arithmetic instructions :
add a, b, c // a gets b + c
● Where are do these operands stay?
● The operands of arithmetic instructions are restricted:
○ they must be from a limited number of special locations built directly in
hardware
● Called registers!

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Registers - Recap
8-bit register
● Assembly Instructions: operate on data i7 D
C
Q+ o7
○ Immediate (constant) i6 D
C
Q+ o6
○ Values stored in registers i5 D
Q+ o5
Memory contents (various addressing modes)
C
○ i4 D
o4
● k-bit register: a set of k D-type flip-flops
Q+
C
i3 D
Q+ o3
C
i2 D
Q+ o2
C
i1 D
Q+ o1
C
i0 D
Q+ o0
C

Clock

I O
A D-type flip-flop

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Clock
Register Operands
● Registers are visible to the programmer
○ Arithmetic instructions use register operands
● RISC-V has a 32 × 64-bit register file
○ Use for frequently accessed data
○ 64-bit data is called a “doubleword”
■ 32 x 64-bit general purpose registers x0 to x30
○ 32-bit data is called a “word”
● Design Principle 2: Smaller is faster
○ main memory: millions of locations
○ A very large number of registers may increase the clock cycle time
■ it takes electronic signals longer when they must travel farther.

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RISC-V Registers
● x0: the constant value 0
● x1: return address
● x2: stack pointer
● x3: global pointer
● x4: thread pointer
● x5 – x7, x28 – x31: temporaries
● x8: frame pointer
● x9, x18 – x27: saved registers
● x10 – x11: function arguments/results
● x12 – x17: function arguments

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Register Operand Example
● C code: f = (g + h) - (i + j);
● It is the compiler’s job to associate program variables with registers.
○ f, …, j in x19, x20, …, x23

● Compiled RISC-V code:

add x5, x20, x21 // register x5 contains g + h

add x6, x22, x23 // register x6 contains i + j
sub x19, x5, x6 // f gets x5 – x6, which is (g + h) − (i + j)

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Memory Operands
● Programming languages have simple variables that contain single data
elements
○ but they also have more complex data structures—arrays and structures.

● How can a computer represent and access such large structures?

○ The processor can keep only small amount of data in its registers

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Memory Operands
● Memory (contains billions of data elements)
○ a large, single-dimensional array
○ memory address acts as the index to that array -
starting at 0.
○ To access a word or doubleword in memory, we must
supply the memory address.
● Can hold composite data
○ data structures (arrays and structures) are kept in
memory!

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Memory Operands
● We need data transfer instructions
○ transfer data between memory and registers.
● Such instructions are traditionally called
○ load - copies data from memory to a register
○ store - copies data from a register to memory

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Memory Operands
● Arithmetic operations occur only on registers in RISC-V instructions.
● To apply arithmetic operations in RISC-V:
○ Load values from memory into registers
○ Perform arithmetic operation using registers
○ Store result from register to memory

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Byte-addressed Memory
● Virtually all architectures today address individual bytes

Doubleword
0 1 2 3 4 5 6 7

Bytes

● There are 8 bytes in a doubleword.

○ Addresses of sequential doublewords differ by 8.
○ The address of a doubleword matches the address of one of the 8 bytes within
the doubleword

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Alignment Restriction
● Many architectures have alignment restrictions:
○ words must start at addresses that are multiples of 4
○ doublewords must start at addresses that are multiples of 8

● RISC-V and Intel x86 do not have alignment restrictions

Doubleword at adddr. 0 Doubleword at addr. 3
0 1 2 3 4 5 6 7 3 4 5 6 7 8 9 10
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Little Endian vs Big Endian
● Little Endian: Least-significant byte at least address of a word
● Big Endian: most-significant byte at least address
● RISC-V is Little Endian

Addr 3 EA
Little Endian Addr 2 01
EA01BD1C Addr 1 BD
Addr 0 1C

Addr 3 1C
Big Endian Addr 2 BD
EA01BD1C Addr 1 01
Addr 0 EA

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Memory Operand Example
● C code: g = h + A[8];
● Assume that:
○ starting address (or base address) of A is in x22.
■ A is an array of 100 doublewords.
○ registers x20 and x21 hold g and h
■ associated by the compiler

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Memory Operand Example
● C code: g = h + A[8];
● One of the operands is in memory:
○ We must first transfer A[8] to a register.

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Memory Operand Example
● C code: g = h + A[8];
● One of the operands is in memory:
○ We must first transfer A[8] to a register.
○ The address of A[8]:
■ the base of the array A + 64
found in register x22 the offset to select element 8

○ The data should be placed in a temporary register

■ for use in the next instruction.

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Memory Operand Example
● C code: g = h + A[8];
● One of the operands is in memory:
○ We must first transfer A[8] to a register.
○ The address of A[8]:
■ the base of the array A + 64
found in register x22 the offset to select element 8

○ The data should be placed in a temporary register

■ for use in the next instruction.

ld x9, 64(x22) // Temporary reg x9 gets A[8]

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load doubleword RISC-V Instruction
● The format of the ld (load doubleword) instruction

ld x9, 64(x22) // Temporary reg x9 gets A[8]

ld: the name of 64: offset (a constant)

the operation
The sum forms the memory address.
x9: register to be
loaded x22: base register

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Memory Operand Example
● The next instruction must add h (x21) to A[8] (x9) and put the sum in the
register corresponding to g (x20) :

add x20, x21, x9 // g = h + A[8]

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Memory Operand Example
● C code:
g = h + A[8];
● Compiled RISC-V code:

ld x9, 64(x22) // Temporary reg x9 gets A[8]

add x20, x21, x9 // g = h + A[8]

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Memory Operand Example
● C code:
A[12] = h + A[8];

● Assume that:
○ starting address (or base address) of A is in x22.
■ A is an array of 100 doublewords.
○ register x21 holds h
■ associated by the compiler

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Memory Operand Example
● C code:
A[12] = h + A[8];

● Now two of the operands are in memory:

○ we need even more RISC-V instructions.

ld x9, 64(x22) // Temporary reg x9 gets A[8]

add x9, x21, x9 // Temporary reg x9 gets h + A[8]
sd x9, 96(x22) // Stores h + A[8] back into A[12]

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store doubleword RISC-V Instruction
● The instruction complementary to load is traditionally called store
○ it copies data from a register to memory.
● The format of the sd (store doubleword) instruction:

sd x9, 96(x22) // Stores h + A[8] back into A[12]

sd: the name of 8: offset (a constant)

the operation
The sum forms the memory address.
x9: register to be
stored x22: base register

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Registers vs. Memory
● Registers are faster to access than memory
● Operating on memory data requires loads and stores
○ More instructions to be executed

● Compiler must use registers for variables as much as possible

○ tries to keep the most frequently used variables in registers and places the rest
in memory
○ The process of putting less frequently used variables (or those needed later)
into memory is called spilling registers.

● To achieve the highest performance and conserve energy:

○ an instruction set architecture must have enough registers, and compilers
must use registers efficiently.

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Immediate Operands
● The constants would have been placed in memory when the program was
loaded
○ We have to load a constant from memory to use one.
● For example, to add the constant 4 to register x22
○ assume that x3 + AddrConstant4 is the memory address of the constant 4:

ld x9, AddrConstant4(x3) // x9 = constant 4

add x22, x22, x9 // x22 = x22 + x9
// (where x9 = 4)

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Immediate Operands
● An alternative that avoids the memory load instruction:
○ Offer arithmetic instructions in which one operand is a constant.
● add immediate or addi
○ Constant data specified in an instruction

addi x22, x22, 4 // x22 = x22 + 4

● Make the common case fast
○ Constant operands occur frequently;
○ addi is the most popular instruction in most RISC-V programs.

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Constant Zero
● RISC-V dedicates register x0 to be hard-wired to the value zero.
● Making the common case fast:
○ Using frequency to justify the inclusions of constants is another example of the
great idea.

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The end
● Read Sections 2.1, 2.2 and 2.3 of your book.

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