1

Assignment 1 = 5 points [USE SEPARATE SHEET]

In the manufacturing system in Figure 1, jobs arrive with a rate of λ jobs per hour. Each workstation
has ample buffer space. The mean natural processing time t0i and the number of (identical) machines
mi in workstation Wi , i = 1, 2, 3, 4, are listed in Table 1. In workstation W1 , 40% of the jobs moves to
W2 and 60% to W3 . All jobs processed in workstations W2 and W3 proceed to W4 . In workstation W4 ,
jobs are tested: 80% of the jobs successfully passes the quality test and leaves the system. Jobs
that fail the test return to W1 to go through the whole manufacturing process again.

0.2
Workstation t0i [hour] mi
0.4 W2
0.8
W1 0.4 2
λ W1 W4 W2 1.5 2
W3 2.0 4
0.6 W3
W4 0.1 1
Table 1: Mean natural processing time t0i and
Figure 1: Manufacturing system with workstations
number of machines mi
W1 , W2 , W3 and W4

a. (2 pt) Formulate the balance equations for the throughput δi of workstation Wi .

b. (1 pt) Express the throughput δi of each workstation in terms of λ.
c. (1 pt) Express the machine utilization ui in each workstation in terms of λ.
d. (1 pt) What is the maximal inflow λmax for the manufacturing system to remain stable?

Assignment 2 = 5 points [USE SEPARATE SHEET]

Random variable X has triangular density on the interval [−1, 1] defined as


1 + x −1 ≤ x ≤ 0,
f (x ) =
1 − x 0 ≤ x ≤ 1,
and f (x ) = 0 otherwise, see Figure 2. Clearly, the minimal value of X is −1, the maximal value is 1
and the most likely one is 0.

f (x)

−1 1 x

Figure 2: Triangular density on [−1, 1]

a. (2 pt) Calculate mean E [X ] and variance Var [X ].

The processing time on a machine can be modeled by the random variable Y = aX + b, where b ≥ a
to make sure that Y ≥ 0.

b. (1 pt) Specify the triangular density of Y .

c. (2 pt) Calculate mean E [Y ] and variance Var [Y ].
 questions that will tackle the problem. The section explains what the different insert
are and how the test parallelism is determent. Finally, the importance of different cha
discussed.
2
2.1 Problem Definition
During the final test of the integrated circuit (IC) production process, the products a
Assignment 3 = 10 points [USE SEPARATE
manufacturing mistakesSHEET]
that might occur at the assembly process. When product
tested, a lot of products need to be inserted into the tester. A lot consists of 10
During the final test of integrated circuitsproducts.
(ICs), theA lot is insertedare
products at the test handler
tested and the products
on manufacturing are tested in batches.
mistakes
by two identical semiconductor testers T1 and T2 (see Figure 3). A tester is shown in Figure 4. Each around the te
size is also called test parallelism. The current research will revolve
policies in the final test. The easiest insertion policy is to insert the product on
IC has 100 connections pins. Part of the test program of an IC requires all pins to be connected to
program and let the tester run the whole test program. However, engineers at NXP
the tester. This part is called the full pin that
test.splitting
The remaining part of into
the test program the two
testinsertions
programcouldonly decrease
needs 50 the total testing
connections. This part is called the min Thispin test.
could The tester by
be achieved has 800 connections.
increasing So 8 of
the test parallelism ICsthecan be insertion. Th
second
tested simultaneously, for which they arethat needson
loaded to be explained
a load boardis how
(seetheFigure
maximum
5). test
Lotsparallelism
consisting is determined.
of Each
many ICs arrive at the testers, and each lot circuit
musthasbea certain number
completely of connection
processed by pins. These
a single are connection
tester, i.e., it is points on the
side ofLots
not allowed to split a lot over the two testers. an integrated circuit. These
arrive according to aconnection
Poissonpins need towith
process be tested
a rateon manufacturi
during the assembly process. Semiconductor testers have a limited number of con
of 2 lots per hour and they are tested in order of arrival. The total full pin test time for all ICs in a lot
which the pins can be connected. Divide the total connections at the tester by the
is denoted by the random variable X with mean 25 minutes and standard deviation 5 minutes. The
pins on the integrated circuit to determine the maximum test parallelism. Figure 2.1
total min pin test time is Y , with mean 20this
minutes
works.and standard deviation 2 minutes. So the total test
time of a lot (full pin plus min pin test) is X + Y , where it is assumed that X and Y are independent.
NXP Graduation thesis Introductio

IC Lots T1

T2

Figure 1.3: An example of a load board

Figure 3: Two testers in parallel Figure 5: Load board for 8 ICs

Each time a product is inserted into the load board and tested is called a test insertion. Produc
Figure 4: Semiconductor tester
are often tested multiple times, depending on the product type and purpose. Common tes
are temperature tests, in which the product is tested at a very high temperature and a ver
low temperature. This study focuses on a test insertion policy analysis in the final test
the integrated circuit production. Testing accounts for approximately five percent of the tot
a. (2 pt) Calculate mean and variance of the total test time X + Y of a lot.
Figure 2.1: An
expenses at NXP, so it often is an area where improvement needs to be made in order to decrea
example ofcosts
how
the production andthe maximum
increase test
the total profits parallelism is determined
of NXP.

b. (1 pt) Calculate the utilization of the testers.

At one point in a test program, all the connection pins need to be connected to the te
c. (2 pt) Estimate the mean flow time a(waiting time
significant plusoftest
portion the time) of a lot.this is not the case. For that part of the te
test program,
only a subset of the pins has to be connected, so this part of the test program can b
Instead of performing the whole test program higher parallelism. This means
on each machine, it that a single
is also test can
possible to be splitthe
split intotest
two tests, where
test is being done at higher parallelism. This results in a lower net test time. Figur
program and devote tester T1 to the full pint test and T2 to the min pin test. The lots are first tested by
how a single insertion policy works, the lot is tested once per test program with low
T1 and then by T2 (see Figure 6). The advantage is that
Full pin means theallmin
that thepin test requires
connection pins areonly 50 connections,
connected to the tester, this results i
so 16 instead of 8 ICs can be tested simultaneously,
parallelism. Thedoubling
Chevronthebartest capacity
represents of T2test.
a single (of Figure
course, 2.3then
shows the same te
T2 needs a bigger load board carrying 16but split
ICs). up intothe
Hence, twototal
separate
min pintests.
testThe second
time of a test
lot onis aT2min pin test, this mea
is now
1 minimal number of connection pins are connected to the tester resulting in the high
2 Y . The total full pin test time of a lot on T1 remains X .
test parallelism. The split insertion strategy results in a lower total net test time.

IC Lots
TU/e T1 T2

Figure 6: Two testers in series

TU/e
d. (1 pt) Calculate the utilization of the testers.

e. (1 pt) Estimate the squared coefficient of variation of the inter-departure times of lots leaving
tester T1 .

f. (2 pt) Estimate the mean total flow time of a lot, i.e., the sum of the mean flow time at T1 and
at T2 .

g. (1 pt) Do you expect the mean total flow time to decrease when the testers change their roles:
first T1 performs the min pin test and then T2 the full pin test? Motivate your answer.
 3

Formula sheet 4DC10

1 te , ce
m
buffer re = te
t a , ca 2 td , cd

1
.. 1
ra = ta . rd = td

• Coefficient of variation
σ
c= (t is mean, σ standard deviation)
t
• Process time variability
mf
A = (Availability)
mf + mr
t0
te = (Mean effective process time)
A
mr mr
ce2 = c02 + A(1 − A) + cr2 A(1 − A) (Squared coefficient of variation)
t0 t0
where t0 and c0 are mean and coefficient of variation of natural process time, mf is mean time
to failure, and mr and cr are mean and coefficient of variation of time to repair
• Flow variability

rd = ra (Conservation of flow)
(
(1 − u 2 )ca2 + u 2 ce2 if m = 1
cd2 ≈ u2
1 + (1 − u 2 )(ca2 − 1) + √ (c 2
m e
− 1) if m > 1

where u is machine utilization

ra te
u=
m
• Performance approximations
Q te
ϕB = γ (Mean waiting time)
1−um
wB = δϕB (WIP in buffer by Little’s law)
ϕ = ϕB + te (Mean flow time)
w = δϕ (WIP by Little’s law)
√
where δ = ra is throughput, γ = 21 (ca2 + ce2 ) and Q = u if m = 1 and Q ≈ u 2(m+1)−1
if m > 1
• Batching interactions for batch size k
k −1
ϕ(w2b) = (Wait-to-batch)
2ra
ra
ra (batch) = (Batch arrival rate)
k
ca2
ca2 (batch) = (Squared coefficient of variation of batch inter-arrival time)
k