Lecture 3,4
Lecture 3,4
Week: 2
Introduction to Computer System
Discipline: BSCS
Instructor: Misbah Shahid
Lecture Outline
✧ A sequence of steps
✧ For each step, an arithmetic or logical operation is
done
✧ For each operation, a different set of control signals
is needed
Levels of Representation
Machine Interpretation
✧ The Control Unit and the Arithmetic and Logic Unit constitute the
▪ Central Processing Unit
✧ Data and instructions need to get into the system and results out
▪ Input/output
✧ Temporary storage of code and results, is needed
▪ Main memory
Computer Components: Top Level View
Register
Instruction Cycle
Fetch Cycle
Instruction 1
Instruction 2
Instruction 3
✧ Disable interrupts
▪ Processor will ignore further interrupts whilst
processing one interrupt
▪ Interrupts remain pending and are checked after
first interrupt has been processed
▪ Interrupts handled in sequence as they occur
✧ Define priorities
▪ Low priority interrupts can be interrupted by higher
priority interrupts
▪ When higher priority interrupt has been
processed, processor returns to previous interrupt
Multiple Interrupts-Sequential
Multiple Interrupts-Nested
Time Sequence of Multiple Interrupts
Interconnection Structures
Structure
✧ A system bus consists of from about 50 to hundreds of
separate lines, each line is assigned a particular
meaning or function
✧ Commonly the bus lines can be classified into three
functional groups i.e. data lines, address lines and
control lines.
Data Bus
✧ are used to control the access to and use of data and address
lines
✧ Control lines transmit both command and timing info b/w system
modules, timing signals indicate validity of data and address info,
command signals specify operations to be performed, e.g.