Department of Electrical & Electronics Engineering

CAE 1 Answer Key

Semester/Year VI/III
Course Code& EE3404 & Microprocessor and
Course Title Microcontroller
Credits 3
Course Type Core
Nature of the
Theory
Course

PART A (10X2=20)

Sl.No Question
Find Maximum external memory that shall be interfaced with 8085 which has 16-
bit address lines.
The Intel 8085 microprocessor has a 16-bit address bus, meaning it can address a
maximum of:
216=65,536 (or 64 KB)
Since 8085 is an 8-bit microprocessor, it can access a total of 64 KB (Kilobytes) of
external memory.
1.
This 64 KB memory space is used for both ROM and RAM. Typically, a portion is
allocated for program memory (ROM), and the rest is available for data memory
(RAM).

So, the maximum external memory that can be interfaced with the 8085
microprocessor is 64 KB (or 65,536 bytes).
What is the signal classification of 8085?
The signals of the 8085 microprocessor can be classified into six groups based on
their function:
1. Power Supply and frequency Signals
2. 2. Address Signals
3. Data Bus Signals
4. Control and Status Signals
5. Externally initiated signals
6. Serial I/O ports
Specify the four control signals commonly used by 8085 MPU.
Control Signals
• ALE (Address Latch Enable) – Distinguishes address and data phases
3.
• IO/M ̅ – Differentiates memory and I/O operations
̅
• RD (Read) – Enables memory or I/O read
• WR̅ (Write) – Enables memory or I/O write
Define machine cycle and T-state.
4. Machine Cycle:
A machine cycle is the time required by the 8085 microprocessor to complete one
 operation, such as fetching an opcode, reading/writing data, or performing an I/O
operation. It consists of one or more T-states.
T-State:
A T-state is one clock cycle of the microprocessor. It is the smallest unit of time in
which the processor executes a part of an operation. Multiple T-states form a machine
cycle.
Example:
• An Opcode Fetch Machine Cycle in 8085 consists of 4 to 6 T-states.
• A Memory Read/Write Machine Cycle typically takes 3 T-states.
State any two applications of look up table.
• Character Encoding and Display – Used in embedded systems and
microcontrollers for mapping ASCII values to display characters in seven-
segment or LCD displays.
5.
• Mathematical Computation – Used to store precomputed values of
trigonometric, logarithmic, or exponential functions to speed up calculations in
signal processing and scientific applications.

Write the functionality of DAA instruction with appropriate example.

DAA (Decimal Adjust Accumulator) Instruction in 8085

Functionality:
• The DAA (Decimal Adjust Accumulator) instruction is used to convert the
result of a binary addition operation into a valid BCD (Binary-Coded Decimal)
number.
• It works by adjusting the contents of the accumulator (A) based on the
6. Auxiliary Carry (AC) and Carry (CY) flags after an addition operation.
• This instruction is useful when performing BCD arithmetic in the 8085
microprocessor.
Working Mechanism:
1. If the lower 4 bits (D3 – D0) of the accumulator are greater than 9 or the
Auxiliary Carry (AC) flag is set, 6 (06H) is added to the accumulator.
2. If the higher 4 bits (D7 – D4) of the accumulator are greater than 9 or the Carry
(CY) flag is set, 60H is added to the accumulator.

Define stack and stack related instructions.

Stack: A stack is a Last-In-First-Out (LIFO) memory structure used for storing return
addresses, register values, and temporary data during program execution. It grows
downward in memory.
Stack-related Instructions:
7.
1. PUSH rp – Stores a register pair onto the stack.
2. POP rp – Retrieves a register pair from the stack.
3. CALL addr – Pushes the return address to the stack and jumps to a subroutine.
4. RET – Pops the return address from the stack and returns to the main program.
5. SPHL – Loads HL register pair into the stack pointer.
State the function of given 8085 instructions: JP, JPE, JPO, JNZ.
• JP addr – Jump if positive (i.e., Sign Flag = 0).
• JPE addr – Jump if parity is even (i.e., Parity Flag = 1).
8.
• JPO addr – Jump if parity is odd (i.e., Parity Flag = 0).
• JNZ addr – Jump if not zero (i.e., Zero Flag = 0).

What are the different Peripheral interfacing used with 8085 processor?
• Input/Output Devices – 8255 PPI, 8279 Keyboard/Display Interface.
• Communication Interfaces – 8251 USART, RS-232.
9.
• Interrupt Controllers – 8259 PIC.
• Timers/Counters – 8253/8254 PIT.
• Memory Interfaces – EPROM, RAM.
 What is the need for for 8259 PIC?
• 8085 has only one INTR pin, limiting multiple interrupt handling.
10. • 8259 PIC allows prioritization and handling of multiple interrupts efficiently.
• Supports vector addressing to avoid polling.
• Reduces the processing overhead of interrupt handling.

PART B (40 Marks)

Sl.No Question
11.a With neat sketch, briefly explain the interrupt structure of 8085 microprocessor.

Interrupt Structure of 8085 Microprocessor:

The 8085 microprocessor has a well-organized interrupt system that allows it to temporarily
stop the current program execution to service an urgent task, called an Interrupt Service
Routine (ISR). After handling the interrupt, the microprocessor resumes the original program.
8085 Interrupts:
8085 has 5 hardware interrupts:
1. TRAP (Highest priority, non-maskable)
2. RST 7.5 (Maskable, edge-triggered)
3. RST 6.5 (Maskable, level-triggered)
4. RST 5.5 (Maskable, level-triggered)
5. INTR (General purpose, maskable)
Priority order:
TRAP > RST 7.5 > RST 6.5 > RST 5.5 > INTR
Brief Explanation:
• TRAP:
o Non-maskable (cannot be disabled).
o Used for critical events like power failure.
o Both edge and level triggered.
• RST 7.5, RST 6.5, RST 5.5:
o Maskable (can be enabled or disabled using instructions like EI, DI, SIM).
o RST 7.5 is edge-triggered (responds to rising edge).
o RST 6.5 and 5.5 are level-triggered (responds as long as signal is active).
• INTR:
o General-purpose interrupt request.
o Needs external hardware to provide the address of ISR.
o Acknowledge signal (INTA) is used.
Important Control Instructions:
• EI (Enable Interrupts)
• DI (Disable Interrupts)
• SIM (Set Interrupt Mask)
• RIM (Read Interrupt Mask)

11.b Two machine codes 00111110 (3EH) and 00110010 (32H) are stored in memory locations
8000H and 8001H, respectively. The first machine code (3EH) represents the opcode to load
a data byte in the accumulator, and the second code (32H) represents the data byte to be
loaded in the accumulator. Illustrate the bus timings as these machine codes are executed.
Calculate the time required to execute the Opcode Fetch and the Memory Read cycles and
the entire instruction cycle if the clock frequency is 2 MHz.
12.a Illustrate the contents of stack memory and register when push and POP instructions are
executed, and explain how memory pointers are exchanged.
PUSH Instruction
Definition:
The PUSH RP instruction stores the contents of a register pair (RP) into the stack.
Execution Steps:
1. SP is decremented by 1 → Higher byte of the register pair is stored.
2. SP is decremented by 1 → Lower byte of the register pair is stored.
3. SP is updated to point to the new stack location.

Example of PUSH Instruction

Given:
• Register Pair: D = A2H, E = 5CH
• Initial Stack Pointer (SP) = 5000H
• Instruction Executed: PUSH DE
Stack and Register Changes:
Step Address Content (Memory) Stack Pointer (SP)
Before PUSH - - 5000H
SP = SP - 1 4FFFH A2H (D register) 4FFFH
SP = SP - 1 4FFEH 5CH (E register) 4FFEH
Final SP after PUSH: 4FFEH

2️. POP Instruction

Definition:
The POP RP instruction retrieves data from the stack into the specified register pair.
Execution Steps:
1. Lower byte is retrieved from the stack.
2. SP is incremented by 1.
3. Higher byte is retrieved from the stack.
4. SP is incremented by 1 again.

Example of POP Instruction

Given:
• Memory (Stack) Contents:
o 4FFEH = 5CH (Lower byte, E register)
o 4FFFH = A2H (Higher byte, D register)
• Initial Stack Pointer (SP) = 4FFEH
• Instruction Executed: POP DE
 Stack and Register Changes:
Step Address Content (Memory) Stack Pointer (SP)
Before POP 4FFEH 5CH 4FFEH
E ← [SP] - - 4FFFH
D ← [SP] - - 5000H
Final SP after POP: 5000H
Final Register Pair: D = A2H, E = 5CH
3️.Exchange of Memory Pointers
• During PUSH, the Stack Pointer (SP) decreases as data is stored.
• During POP, the Stack Pointer (SP) increases as data is retrieved.
• The stack follows a LIFO (Last In, First Out) structure, meaning the last stored value
is retrieved first.

Stack Representation for PUSH & POP

Initial:
SP → 5000H

After PUSH DE:

Memory[4FFFH] ← A2️H (D)
Memory[4FFEH] ← 5CH (E)
SP → 4FFEH

After POP DE:

E ← Memory[4FFEH] (5CH)
D ← Memory[4FFFH] (A2H)
SP → 5000H

Key Takeaways
1. PUSH stores register pair data into the stack (SP decrements).
2. POP retrieves register pair data from the stack (SP increments).
3. The stack is LIFO (Last In, First Out).
4. The Stack Pointer (SP) is updated automatically after every PUSH/POP operation.

12.b (i) Write instructions to clear the CY flag, to load number FFH in register B, and increment
(B). If the CY flag is set, display 01 at the output port; otherwise, display the contents of
register B. Explain your results. (10)
Objective:
• Clear CY flag
• Load FFH in register B
• Increment B (result becomes 00H, and CY flag is set)
• If CY = 1, output 01H
• Else, output contents of register B
Explanation:
• FFH + 1 = 00H, which causes an overflow, setting the Carry flag (CY).
• The program checks the CY flag using JNC.
• Since CY is set, it outputs 01H to port 01H.
• If CY weren’t set, it would output the incremented value of B.
(ii) Write a subroutine to set the Zero flag and check whether the instruction JZ (Jump on
Zero) functions properly, without modifying any register contents other than flags. (6)

Objective:
• Write a subroutine that sets the Zero (Z) flag
• Use the JZ (Jump if Zero) instruction to test whether it works
• Do not modify any register except flags

Explanation:
• XRA A sets Accumulator = 00H, which sets the Zero flag (Z = 1)
 • The JZ instruction checks this flag and jumps to the label if it’s set
• No other register (like B, C, D...) is changed — only the flags are affected

13.a With neat diagram,explain architecture and interfacing of 8255PPL.

The Intel 8255 is a popular Programmable Peripheral Interface (PPI) device used to connect
input/output devices to a microprocessor like the 8085.
It provides 24 I/O pins that can be programmed in different modes.
Main Functional Blocks:
• Data Bus Buffer:
Interfaces the internal data bus of 8255 to the system data bus.
• Read/Write Control Logic:
Controls the operation (read or write) depending on control signals like RD, WR, CS,
A0, and A1.
• Control Logic:
o Decides whether the operation is related to Port A, Port B, Port C, or the
Control Word Register.
• Group A & Group B:
o Divides ports into two groups:
▪ Group A: Port A + upper half of Port C.
▪ Group B: Port B + lower half of Port C.
o Each group can operate in different modes.

Ports:
• Port A: 8-bit bidirectional data port.
• Port B: 8-bit bidirectional data port.
• Port C:
o Split into two 4-bit ports (CU and CL).
o Used for handshaking and control signals.

Operating Modes of 8255:

1. Mode 0: Simple Input/Output
2. Mode 1: Input/Output with Handshaking
3. Mode 2: Bidirectional Data Transfer (only for Port A)

Interfacing 8255 with 8085 Microprocessor

8255 is connected to the 8085 via:
• Data bus (D0-D7) for data transfer.
 • Address lines (A0, A1) for selecting ports/control register.
• Control signals:
o CS (Chip Select): Active low, enables 8255.
o RD (Read): Active low, reads data from 8255.
o WR (Write): Active low, writes data to 8255.
o RESET: Resets 8255.
A1 A0 Selected Port/Register
0 0 Port A
0 1 Port B
1 0 Port C
1 1 Control Register
13.b With neat circuit diagram/ functional block diagram, interface an analog sensor with 8085
microprocessor. Also write an assembly language program to read, convert the sensor value
and save the result in 8000H.
8085 Assembly Program
Assumptions:
• ADC mapped to PORT 00H (data read)
• Control signals (START, OE, etc.) controlled via PORT 01H
• EOC is checked via polling (assuming some delay)
Explanation
1. Start ADC Conversion by pulsing START and ALE.
2. Wait for EOC signal to go high (conversion done).
3. Enable OE to read digital value from ADC.
4. Read value from PORT 00H and store it in 8000H.
5. Disable OE, end program.
Applications
• Reading temperature, light intensity, pressure sensors, etc.
Useful in real-time data acquisition systems with 8085.