A Semi-Automated Sizing Tool for CMOS Analog

Building Blocks Integrated into EDA Environment

2024 37th SBC/SBMicro/IEEE Symposium on Integrated Circuits and Systems Design (SBCCI) | 979-8-3503-9169-5/24/$31.00 ©2024 IEEE | DOI: 10.1109/SBCCI62366.2024.10703984

Rodrigo S. Moraes1 and Lucas Compassi-Severo2

1
Federal University of Pampa - UNIPAMPA, Alegrete, RS, Brazil
2
Aeronautics Institute of Technology - ITA, São José dos Campos, SP, Brazil
[email protected], [email protected]

Abstract—The integrated circuits - digital, analog, or mixed- calculated components at the previous level is used, taking into
signal - are designed and verified through the use of circuit account some restrictions imposed by the integrated circuit
simulators before being reproduced in real silicon. Analog in- factory [4].
tegrated circuits exploit the physics of the manufacturing pro-
cess, manipulating precise quantities such as voltages, currents, At the circuit level, there are some semi-automatized tools
charges, and continuous ratios of parameters like resistance and for analog circuits, such as UCAF [4] and Wicked [5] that
capacitance. Unlike digital circuits, there are not many design use complex optimization algorithms in order to transform
automation tools for analog ICs. In this context, this paper the analog design task in an optimization problem. However,
presents a sizing tool for CMOS transistors, in order to assist in general, this kind of tool requires the designer a great
the design of integrated circuits in sub-micrometric technologies.
This tool is based on a set of subroutines implemented using knowledge to set up all the algorithms and their interfaces.
Python and Cadence SKILL programming languages with a These characteristics contribute to the misuse of the tools and
command line interface (CLI) to the Cadence Spectre simulator. are not attractive to specialized designers.
The semi-automated sizing tool presented can be used to explore Based on this assumption, this work proposes a transistor
the transistor size considering the small-signal parameters and sizing tool to be used to support the analog circuit designer in
bias-point information. This tool is detailed in this work, and
the design results of a common-source amplifier and a negative the sizing process. The main objective is to assist the analog
transconductor are presented considering 180 nm and 65 nm and RF designer and to reduce the time expended in preparing
CMOS fabrication processes. and executing some design procedures, without the need for a
Index Terms—EDA; Cadence Virtuoso; Analog ICs, Design test-bench preparation. It can be used to evaluate the transistor
Automation, Python, Cadence Skill. operation regions and to obtain the transistor size that fits
the desired requirements. The proposed tool is implemented
I. I NTRODUCTION in Python and its graphical interface is integrated into the
The design of analog and radio-frequency integrated circuits Cadence Virtuoso Menu in order to make easy it to use.
is one of the most challenging areas of microelectronics. In This work is organized as follows, Section II presents the
general, the circuit is designed according to the designer’s strategy of using transistor operation point for transistor sizing,
knowledge and based on previous experiences and each one Section III details the proposed tool implementation, Section
of the transistors should be individually designed. Oppositely, IV shows the application of the tools in two different designs
digital integrated circuits are mostly designed in a semi- and Section V concludes this work.
automatized process where the designer works on hardware
description language, and a set of tools are used to perform II. CMOS T RANSISTOR O PERATION -P OINT E VALUATION
the logic and physical synthesis [1]. Based on that, the number The CMOS transistors are electronic devices that have four
of automation tools focused on digital circuits is bigger than terminals: source, gate, drain and substrate or bulk. The basic
the tools for analog circuits [2]. operation of the MOSFET occurs through the flow of electrical
Generally, the analog circuit design task can be divided into current between the drain and source terminals, where the con-
three levels of abstraction, ranging from the definitions of the ductivity is controlled through the voltage applied to the gate
specifications that the circuit needs to perform its functions, [6]. The CMOS transistor channel has a width W and length
right down to the physical design of the circuit [3]. These L. The channel dimensions influence the passage of electrical
levels are called system level (higher abstraction), circuit level charges and all electrical characteristics of the device. In other
(medium abstraction) and layout level (lower abstraction). At words, the drain current ID is directly proportional to the
the system level, the analog circuit is treated as a functional W/L ratio [7]. Additionally, other significant characteristics of
block, where the circuit specifications are determined. For the MOSFETs are the variations between IDS current and voltages
circuit level, the block is treated as a schematic, in which VGS and VDS , important for analyzing small-signals from the
the components must be sized according to the specifications device. These variations, called gate transconductance (gm)
defined at the system level. In the layout level, the physical and output conductance (gds) can be calculated with Equations
design of the circuit is presented, where the size of the 1 and 2, based on the partial derivatives of IDS .

Authorized licensed use limited to: UNIVERSITY OF SOUTHAMPTON. Downloaded on November 12,2024 at 02:09:41 UTC from IEEE Xplore. Restrictions apply.
 ∂IDS
gm = (1)
∂VGS
∂IDS
gds = (2)
∂VDS
Modeling CMOS transistors is not an easy task when it
comes to manufacturing processes at sub-micrometer scales,
due to non-linear effects and its complexity [8]. Because of
that, the MOSFET drain current expression is dependent on
the biasing, transistor sizing, and also on several process-
dependent parameters (pi ), as shown in Eq.3 [9].

ID = f (W, L, VGS , VDS , VBS , p1 , p2 , ..., pn ) (3)

To overcome the need for the implementation of the tran-
sistor modeling, SPICE simulation can be used to obtain the
circuit characteristics according to the circuit parameters such
as the width W, the length L and the voltages VGS , VDS Fig. 1: Sizing process flowchart.
and VBS applied on the transistor terminals, and returns the
simulation output data. This strategy can provide other useful
simulation parameters, such as the small-signal transconduc- parameters, the values obtained from the simulation using the
tances and parasitic capacitances as shown in Eq. 4. variable start value (V ar0 ) are used as inputs in the next
iteration, and then the parameters are adjusted until they reach
the desired value for the objective parameter.
[ID , gm, gds, ..., CGS , CDS ] = f (W, L, VGS , p1 , ..., pn ) (4)
|pobjective − pcurrent |
III. P ROPOSED CMOS TRANSISTOR SIZING TOOL error = (5)
|pobjective |
The main challenge of the analog integrated circuit design is
pobjective
that, at the first step, the designer is not interested in knowing V ari+1 = × V ari (6)
the values of the parameters results by Eq. 4, since normally pcurrent
the transistor W and L are unknown parameters. Thus the basic Figure 1 shows the algorithm’s flow chart of the sizing pro-
idea of the tool proposed in this work is to obtain an inverse cess using the Cadence Spectre simulator to evaluate the tran-
function of Eq. 4. In other words, the objective is to obtain the sistor basic simulation testbench, based on an nMOS/pMOS
W and L of the transistor that generates the required current transistor with DC biasing sources, and to obtain the objective
levels or small signal parameters. parameter value.
In order to develop a generic strategy for CMOS transistor The back-end (sizing procedure) only uses Python default
sizing, a tool based on the use of the commercial simulator Ca- modules, and the front-end (graphical user interface and plots)
dence Spectre® is proposed by using the Python programming was implemented using matplotlib, pandas and PyQt modules.
language to automate the SPICE operating point simulation.
The tool proposed in this work is divided into two basic tools,
one focused on sizing the transistor to obtain objective values B. Parametric Sizing Tool
and another used to obtain an objective considering parametric The logic shown in the flowchart in Fig. 1 can be extended
variations. The following subsections present the details of to return multiple solutions from the sizing process according
each tool. to the objective parameter. As described before, one of the
dimensional parameters is a variable value that is modified
A. Transistor Sizing Tool each iteration, while the other one is fixed. If the sizing process
The sizing process was implemented in the proposed tool is kept on a loop while changing the fixed parameter, we
iteratively by running simulations and reading the simulation can ”sweep” a list of this parameter while returning different
output data. From Eq. 5 it is possible to calculate the error solutions. An example of this process is described in Fig.2,
between the objective parameter value (pobjective ) and its value where a list of fixed L values is swept while the variable
at the current iteration (pcurrent ). If the error is greater than the parameter W is adjusted to find the objective parameter, in this
maximum specified value and the number of iterations has not case, the drain current (ID ). Thus, running this example it is
been exceeded, then Eq. 6 is used to adjust the new variable possible to obtain the W for each L that makes the transistor
parameter (V ari+1 ) based on the current variable value (V ari ) present the required ID level. It is very different from the
and on the ratio of pobjective and pcurrent . In other words, simple parametric variation tool available on the classic EDA
after the user specifies the MOSFET parameters and objective tool.

Authorized licensed use limited to: UNIVERSITY OF SOUTHAMPTON. Downloaded on November 12,2024 at 02:09:41 UTC from IEEE Xplore. Restrictions apply.
 Fig. 2: Parametric sizing tool process.

This tool is extremely useful when the designer wants to see

the trade-offs for a range of parameters. All the specifications (a) Sizing Tool.
available on the transistor operation point result can be used
as a sweep variable and an objective parameter.
C. Graphical User Interface
To encourage the use of this tool by analog circuit designers
and to eliminate the necessity of using Python, it was devel-
oped graphical user interfaces (GUI) for the tools. The GUI
source code was made mainly using Python, and the integra-
tion between the sizing tool and the Virtuoso environment uses
the Cadence SKILL programming language. This integration (b) Sweep Tool.
allows the user to access the sizing tool directly through a
menu implemented in the Virtuoso CIW, as shown in Fig 3. Fig. 4: Graphical interfaces of the proposed tools.

Fig. 3: Accessing the sizing tools from the Virtuoso CIW.

Fig. 4a shows the graphical interface of the sizing tool. It (a) (b)
is composed of some fields for inserting the design character- Fig. 5: Circuits used for demonstration: (a) common-source
istics and selecting the objectives. It also has a ”project view” amplifier and (b) cross-coupled negative transconductor.
panel that makes it possible to do multiple sizing processes
sequentially, and the user can take a parameter from the
previous procedure to use as the objective for the next one. drain current (ID ). From the small-signal analysis, we obtain
Its use will be demonstrated in Section IV. the circuit voltage gain (AV ) and gain-bandwidth product
The Sweep Tool GUI is implemented in a similar way as (GBW ) equations:
shown in Fig. 4b. It has some fields to sweep setup and graph
plot definitions and to show the execution results. It is possible −gm1
AV = (7)
to plot the data obtained from the sweep tool by selecting it gds1 + gds2 + jωCL
from the window, which gives the user a powerful way to gm1
analyze the results. GBW = (8)
2πCL
IV. T OOL A PPLICATION R ESULTS We consider that it is used a CMOS 65 nm process
This section shows two application examples to demonstrate and that were required the following circuit specifications:
the main functionalities of the proposed sizing tool. The VDD = 1.2 V , GBW = 1 M Hz, CL = 10 pF , and
first design example is based on a common-source amplifier AV (ω = 0) = 30 dB. From Eq. 8 we obtain gm ≈ 63 µS.
(Fig. 5a) and the second one is a cross-coupled negative Knowing that AV = 30 dB = 31.6 V /V , and considering
transconductor (Fig. 5b). gds1 = gds2 = gds, we get that gds ≈ 1 µS. Thus, we have
the ratio gm/gds = 63. The sweep tool is used to find the
A. Common-Source Amplifier value of gm/gds as a function of L. In this case, W is used
The common-source amplifier (CSA) is a well-known am- as a variable, and L is varied between 60 nm and 1 µm, with
plifier topology. It consists of an nMOS common-source the objective of finding gm = 63 µS. Figure 6a shows the tool
transistor and a pMOS biasing current source to control the result plots for gm/gds and gds where it is possible to see

Authorized licensed use limited to: UNIVERSITY OF SOUTHAMPTON. Downloaded on November 12,2024 at 02:09:41 UTC from IEEE Xplore. Restrictions apply.
that we find the desired value of gm/gds for channel length
gmneg
longer than 880 nm. gm1 = − ( gm
(10)
1 ID ) 1
1 − ( gm )1 − gm
( gds )2 ( gm
gds ID )1

For this project, pMOS transistors were sized to present

gm1 = 10 µS and nMOS were sized according to the
current ID required by the pMOS transistors. This circuit was
designed in 180 nm and 65 nm CMOS processes. For compar-
ison, the 180 nm project uses the parameters VDD = 0.5 V ,
and L = 1 µm, to compare it to a similar project found in
the literature [10]. In the 65 nm project, the gm × L curve
was analyzed to define the best value of L (that was equal to
(a) (b) 305 nm). Table II shows the comparison of the parameters
for the 180 nm, 65 nm and the design found in the literature.
Fig. 6: CSA curves: (a) gm/gds × L, (b) gds × L.
The frequency response in Fig. 8 shows that gm = −10 µS
is kept constant from DC to 25 MHz.
For this value of L, the nMos transistor should have
ID = 6.14 µA. Thus, the next step is to use the sizing tool to TABLE II: Parameters obtained for the cross-coupled negative
obtain the pMos sizes that result in the same current ID level transconductor.
and keep the gds ≈ 1µS to satisfy the desired voltage gain
Parameter 180 nm 65 nm 180 nm [10]
level. In Fig. 6b is possible to see that for a L > 400 nm, W1 (µm) 2.12 9.76 2.17
the pMos presents the desired gds value. The results obtained W2 (µm) 5.12 2.23 5.9
by the tool can be seen in Table I and Fig. 7 shows the Iref (nA) 557 353 580.5
simulated frequency response of the common-source amplifier,
where it is possible to verify that AV (ω = 0) and GBW are
approximately equal to the required values of 30 dB and
1 MHz, respectively.

TABLE I: Parameters obtained for the designed CSA.

Parameter nMOS pMOS
gm(µS) 62.6 N/A
gds(µS) 0.99 1
ID (µA) 6.14 6.14 Fig. 8: Frequency response of the designed cross-coupled
L(µm) 0.88 0.47
W (µm) 1.31 1.52 negative transconductor.

V. C ONCLUSION
In this paper, a CMOS transistor sizing tool based on Python
integrated into Cadence Virtuoso was presented. It can be
used to assist the analog and RF circuit designer in order to
reduce the work effort and design time. As it is based on
using Python language and SPICE simulator it can be ported
for different server/computer architecture and used in different
CMOS processes. The tool implementation was detailed and
Fig. 7: Frequency response of the designed CSA. two design examples were designed using the proposed tool
in 180 nm and 65 nm CMOS process.
In future works, we intend to add compatibility to other
B. Negative Transconductor simulators, such as Ngspice, and increase the number of
In this topology, the pMOS transistors M1a and M1b imple- implemented tools and functionalities, including Monte Carlo,
ments the negative transconductance, and the nMOS transistors Mismatch and Process Corners analysis, and also to improve
M2a , M2b and M2c works as current sources. The small-signal the use of the Cadence SKILL language to maximize its
negative transconductance is obtained by Eq. 9. usability and improve the designer interface.
VI. ACKNOWLEDGMENT
gmneg = −gm1 + gds1 + gds2 (9)
The authors would like to thank to CNPq agency for the par-
Considering IDM 1 = IDM 2 = Iref , and using the parameters tial support of this work, under grant numbers 420693/2023-8
gm/ID and gm/gds, we can derive Eq. 10: and 303609/2023-0.

Authorized licensed use limited to: UNIVERSITY OF SOUTHAMPTON. Downloaded on November 12,2024 at 02:09:41 UTC from IEEE Xplore. Restrictions apply.
 R EFERENCES
[1] A. F. Budak, D. Z. Pan, H. Chen, K. Zhu, M. Liu, M. B. Alawieh,
S. Zhang, W. Shi, and X. Tang, CAD for Analog/Mixedx2010;Signal
Integrated Circuits, 2023, pp. 43–60.
[2] R. Mina, C. Jabbour, and G. E. Sakr, “A review of machine learning
techniques in analog integrated circuit design automation,” Electronics,
vol. 11, no. 3, 2022.
[3] S. Dam and P. Mandal, “Modeling and design of cmos analog circuits
through hierarchical abstraction,” Integration, vol. 46, no. 4, pp. 449–
462, 2013.
[4] L. C. Severo and A. Girardi, “Uma ferramenta para o dimensionamento
automático de circuitos integrados analógicos considerando análise de
produtividade,” Master Dissertation, Graduate Program in Electrical
Engineering, Federal University of Pampa, 2012.
[5] R. A. Rutenbar, G. G. E. Gielen, and B. A. Antao, WiCkeD: Analog
Circuit Synthesis Incorporating Mismatch, 2002, pp. 217–220.
[6] I. Sinclair, “Chapter 3 - active components and integrated circuits,” in
Electronics Simplified (Third Edition), third edition ed., I. Sinclair, Ed.
Oxford: Newnes, 2011, pp. 47–59.
[7] B. Hilbert and M. Pavanello, “Electrical characterization of mosfets from
a 180 nm cmos technology,” 20th Microelectronics Student Forum, 2020.
[8] L. C. Severo, “Ulv and ulp active-rc filters combining single-stage ota
and negative input transconductance for low energy rf receivers,” Ph.D.
dissertation, USP, 2019.
[9] Y. Tsividis and C. McAndrew, Operation and Modeling of the MOS
Transistor, ser. The Oxford Series in Electrical and Computer Engineer-
ing Series. Oxford University Press, 2011.
[10] A. Girardi, L. Compassi-Severo, and P. C. Comassetto de Aguirre,
“Design techniques for ultra-low voltage analog circuits using cmos
characteristic curves: a practical tutorial,” Journal of Integrated Circuits
and Systems, vol. 17, no. 1, p. 1–11, Apr. 2022. [Online]. Available:
http://dx.doi.org/10.29292/jics.v17i1.573

Authorized licensed use limited to: UNIVERSITY OF SOUTHAMPTON. Downloaded on November 12,2024 at 02:09:41 UTC from IEEE Xplore. Restrictions apply.