EC65102 VLSI Design

L-T-P: 3-0-2; Cr: 04

Pre-requisite: Basic device electronics, MOSFET properties, and logic circuits.
Objectives: This course is intended to impart in-depth knowledge about analog and digital
CMOS circuits. The focus is on CMOS circuits. Issues to be covered include deep submicron
design, clocking, power dissipation, CAD tools and algorithms, simulation, verification,
testing, and design methodology. This course also dealt with design analysis techniques for the
static and dynamic evaluation of CMOS circuits and memory elements including flip-flops,
SRAM, and DRAM.
COURSE CONTENTS:
Unit I: Introduction to VLSI Design: Introduction to VLSI Design; Moore's Law; Scale of
Integration; Types of VLSI Chips; Design principles (Digital VLSI); Design Domains(Y-
Chart), Challenges of VLSI design- power, timing area, noise, testability reliability, and yield;
CAD tools for VLSI design. [6L]

Course Outcomes: After completion of course, students should be able to:

1. Demonstrate a clear understanding of CMOS fabrication flow and technology scaling.
2. Design MOSFET based logic circuit
3. Draw stick diagram and layout of a given logic circuit
4. Realize logic circuits with different design styles
5. Demonstrate an understanding of working principle of operation of different types of
memories
6. Demonstrate an understanding of working principles of clocking, power reduction and
distribution
Text/Reference Books:
1. Neil H. E. Weste and Kamran Eshraghian, "Principles of CMOS VLSI Design", 2nd edition,
Pearson Education Asia.
2. Jan M. Rabaey, Anantha Chandrakasan, Borivoje Nikolic, "Digital Integrated Circuits: A
Design Perspective," Prentics Hall
3. Sung-Mo Kang, Yusuf Liblebici, "CMOS Digital Integrated Circuits," Tata Mc Graw HillR.
Jacob Baker, "CMOS Mixed-Signal Circuit Design," Wiley India Pvt. Ltd.
4. Ivan Sutherland, R. Sproull and D. Harris, "Logical Effort: Designing Fast CMOS Circuits",
Morgan Kaufmann
Dr. G. Gopal
Assistant Professor (ECE), NIT Patna
Job opportunities after study this subject:
Studying VLSI Design offers VLSI job opportunities in roles like IC Design, Verification, and
Physical Design Engineer, with top companies like Intel, Qualcomm, and Synopsys.

Suggested Courses for VLSI Jobs:

1. https://www.youtube.com/playlist?list=PLJ5C_6qdAvBELELTSPgzYkQg3Hgcl
Qh-5
2. https://www.udemy.com/share/1036pm3@yWdJMhgA1uzWYm0_fFwdu6QKlS
b6Svg-Zs0Jvymt0GxybwGKbIMTYUKp7nk7alkryQ==/
3. https://www.udemy.com/share/104ub03@Mu-
IehU5aOCM0GDKAixov1X8HyYgbSQS1vuhSQUDmBz9pVpwoeUFCXyifXdJ6
3dt3A==/
4. https://www.udemy.com/share/103FYJ3@p5NvLj-
ULSK4ClNg4wX_KrGIRRebwOmgf8tQRUiI-
dDn4ob2Abj0XRzGaD9lk9jH2A==/
5. https://www.udemy.com/share/1047PU3@alSRnXYoa2bt7lFZUfR-
GlHu8SkKIa2Q--_seu70q4yMobRcP0DrfYIqfjXtadh6Cg==/
6. https://www.udemy.com/share/103nFa3@L9GCva4ruEn1tJk4rnuySsZdP2rMZn
3SM3GCeJtCOkPB0nx1XIGFBPtNTtJYFrxoug==/
7. https://www.vlsi-expert.com/p/static-timing-analysis.html

Introduction to VLSI Design:

Historical Perspective:
• The evolution of very large-scale integration (VLSI) in the last half century is illustrated
in Fig. 1, indicating major milestones.
• Depending on the level of integration of components into a single chip, the IC
technology is classified into several categories, among which VLSI is an advanced
integration level.

Dr. G. Gopal
Assistant Professor (ECE), NIT Patna
 Fig. 1 Evolution of VLSI (major milestones)

What is Integrated Circuit (IC)?

• An integrated circuit (IC), also known as a chip or microchip, is a semiconductor wafer
on which thousands or millions of tiny resistors, capacitors, and transistors can be
manufactured.
• Integrated circuit design, or IC design, is a significant part of electronics engineering
that deals with logic and circuit design.
• Different types of IC chips include Digital Integrated Circuits, Analog Integrated
Circuits, and Mixed Integrated Circuits.
• Digital integrated circuits are also known as logical circuits because they execute
logical operations on digital signals.
• Digital integrated circuit design is a technique of designing circuits that execute logical
operations based on digital circuits.
• Digital IC Design focuses on creating and optimizing digital integrated circuits, the
building blocks of modern electronic systems.
• It covers designing combinational and sequential circuits, using HDL (like
Verilog/VHDL), and employing EDA tools to develop efficient, high-performance, and
scalable chips for applications in computing, communication, and automation.
Introduction to IC Technology
• VLSI technology has been the enabler for advancement of the present electronics and
communication age.

Dr. G. Gopal
Assistant Professor (ECE), NIT Patna
 • Silicon has been a natural choice of material for IC manufacturing because of its
abundance in nature, and more importantly its native oxide which is most suitable for
IC fabrication. Almost 90% of the electronic circuits fabricated worldwide are made
of silicon using CMOS technology. CMOS technology is the most popular technology
because of its low power and less area requirement.
• Figure describes the IC manufacturing process in a pictorial format. First, the single
crystal silicon ingot is grown, which is sliced to obtain wafers. The wafers are the
substrate of the IC chip. Now on the wafer, the devices and their interconnections are
patterned using the lithography technique.
• A processed wafer contains several identical ICs called a die. The processed wafer is
then tested to identify faulty circuits. The dies are separated from the wafer and each
die is bonded and packaged to form IC chips. These chips are tested to sort out the
faulty ones from the manufactured chips, and then the good chips are shipped to the
customer site.

Fig. 2: Schematic view of IC technology

The steps of Digital IC Design are:

• Specification: Define what the chip needs to do and its performance requirements.
• Architecture Design: Plan the structure and flow of the design.
• RTL Design: Write code (using Verilog or VHDL) to describe the chip's functionality.
• Functional Verification: Test the design to ensure it works as expected.
• Synthesis: Convert the design into a circuit of logic gates.
• DFT (Design for Testability): Add features to make the chip testable after
manufacturing.
• Place and Route (Physical Design): Arrange the circuit on a chip layout and connect it.
• Timing Analysis: Check if the design meets speed requirements.
• Power Analysis: Ensure the chip uses power efficiently.
• Verification and Signoff: Final checks before sending the design for manufacturing.
Simplified flow of circuit design:
• As circuit designers, start from a logic diagram along with design specifications.

Dr. G. Gopal
Assistant Professor (ECE), NIT Patna
 • The logic circuit is first translated into a CMOS circuit and the initial layout is done.
• Once a full circuit description is obtained from the initial layout, we analyse the circuit
for DC and transient performance by using the circuit-level simulation program,
SPICE, and then compare the results with the given design specifications.
• If the initial design fails to meet any one of the specifications, then an improved circuit
is designed to meet the design objective.
• Then the improved design will be implemented into a new layout and the design-
analysis cycle will be repeated until all of the design specifications are met.

Fig. 3: Simplified flow of circuit design

Design abstraction levels in digital circuits:

• Abstraction is the process of simplifying complex systems by focusing on the most
relevant details at a specific level.
• Typically used abstraction levels in digital circuit design are, in order of increasing
abstraction, the device, circuit, gate, functional module (e.g., adder) and system levels
(e.g., processor), as illustrated in Fig. 4.

Dr. G. Gopal
Assistant Professor (ECE), NIT Patna
 Fig.4: Design abstraction levels in digital circuits.
The design abstraction levels in digital circuits span from the device to the system. At the
device level, the focus is on individual semiconductor devices like MOSFETs and their
physical characteristics. Moving up, the circuit level combines these devices to create basic
circuits such as logic gates, amplifiers, and memory cells. The gate level further interconnects
these gates to perform specific Boolean operations like addition or multiplexing. At the module
level, gates are grouped into functional blocks, such as arithmetic logic units (ALUs), memory
modules, or control units. Finally, the system level integrates multiple modules to form a
complete system capable of handling complex tasks like computation, communication, or
control.

Moore's Law; Scale of Integration

Table 1 lists the different IC technologies that have evolved over the last 50 years.
• The main target of integrated circuit design and fabrication is to achieve more
functionality at higher speed using less power, less area, and low cost.
• In the early 1960s, Intel cofounder Gordon Moore had predicted that the number
of devices on a single chip will double in every eighteen months.
• Over the last 50 years it has been found that the semiconductor industry has really
followed the prediction of Moore, and hence it has become a law which is famously
known as the Moore’s law.
Dr. G. Gopal
Assistant Professor (ECE), NIT Patna
 Table 1 Evolution of integration level in integrated circuits

Fig.5: Evolution of minimum feature size in integrated circuits over time

Fig. 5 shows the evolution of the minimum feature size of transistors in integrated circuits, starting from
the late 1970s. In 1980, at the beginning of the VLSI era, the typical minimum feature size was 2 µm,
and a feature size of 0.3 µm was expected around the year 2000. The actual development of the
technology, however, has far exceeded these expectations. A minimum feature size of 7 nm was
achieved by 2023.

Dr. G. Gopal
Assistant Professor (ECE), NIT Patna
 Types of VLSI Chips;
Depending on the types of substrates, devices, signal processing, and applications, ICs are classified as
shown in Table II. The material used for substrate of the IC can be either of silicon, GaAs, or Si–Ge.
Table II shows the classification of ICs on the basis of types of substrates.
Table II Classifications of integrated circuits

Based on the devices used for implementing the IC, they are classified as follows:

• Bipolar—In these ICs, bipolar junction transistors (BJTs) are used to implement the IC.
• CMOS—In the CMOS ICs, combination of nMOS and pMOS transistors are used to implement
the IC.
• BiCMOS—In these ICs, combination of BJT and CMOS transistors are used.
• MESFET—Metal semiconductor field effect transistors are used in these ICs.
• HBT—These ICs use hetero-junction bipolar transistors.
• HEMT—High electron mobility transistors are used in these ICs.

Design principles (Digital VLSI);

Design Methodology
• VLSI design is a sequential process of generating the physical layout of an IC, starting from
the specification of that circuit. It can be fully or semi-automated using numerous softwares
called electronic design automation (EDA) or computer aided design (CAD) tools.

Dr. G. Gopal
Assistant Professor (ECE), NIT Patna
 • The designers first get an idea of a new system or device for a particular application. This new
idea is translated in the form of an integrated circuit chip using the VLSI design flow.
• There are two design styles used in VLSI design. One is the top–down approach and another is
the bottom–up approach. In the top–down approach, the system is built starting from the top up
to the bottom. While in the bottom–up approach, the basic building blocks are built first, and
they are combined or assembled to build the entire system.
• Hierarchical Abstraction Hierarchical decomposition or ‘divide and conquer’ is a useful
methodology that partitions the entire system into its components.
• The components are again partitioned into modules and this process continues until the basic
building blocks are reached. This methodology is illustrated in Fig. 6.

Fig. 6 Hierarchical decomposition of an electronic system

Regularity, Modularity, and Locality

• Regularity indicates that the decomposition process must not produce a large number of blocks,
and the blocks need to be similar as much as possible.
• Modularity is another important aspect of hierarchical decomposition. It means that the
functional blocks must have well-defined interfaces and functionality
• Hierarchical decomposition must also consider the locality of the functional blocks. The
decomposition should be such that the blocks, exchanging signals frequently, must be close to
each other in order to reduce the interconnect length.

VLSI Design Flow

• The VLSI design flow is a sequence of steps followed to translate the idea of a system into a
chip. The flow is based on the standard design automation tools.
• The basic steps are shown in Fig. 7. It starts with system specifications such as area, speed,
and power. Then the functional design is done followed by functional verification to check if
the design is correct. In this phase, the design is described at the behavioural level.
• Next, the design is implemented at the logic level and verified for its correctness. This is
followed by the transistor level or circuit design verification. Up to this step, the flow is known
as logical design.
• The next phase is the physical design which actually deals with the geometry of the chip.
• Once the physical layout is generated, it must be verified to check if the layout really
implements the actual design.
Dr. G. Gopal
Assistant Professor (ECE), NIT Patna
 • The last and final step is the fabrication and testing of the chip. Fig. 7 illustrates the VLSI
design flow at the top level.

Fig. 7 VLSI design flow

VLSI Design Styles

• Depending on the application, cost of production, performance, and the volume of production,
there are different VLSI design styles that are followed to implement a chip. Each of the styles
has its own advantages and disadvantages and is chosen on the basis of the target application.
• The commonly used design styles are as follows: (i) Field programmable gate array (FPGA)
design (ii) Gate array design (iii) Standard cell-based design (iv) Full-custom design (v) Semi-
custom design (vi) Programmable logic device (PLD)

Field Programmable Gate Array (FPGA) Design

• Field programmable gate array (FPGA) is a fully fabricated IC chip in which the
interconnections can be programmed to implement different functions.
• A typical FPGA architecture is shown in Fig. 8 . It has the following three main components:
(i) I/O buffers (ii) Array of configurable logic blocks (CLBs) (iii) Programmable interconnects.
• In the FPGA-based design, first a behavioural netlist is written to describe the functionality of
the design. This is done using the hardware description languages such as Verilog or VHDL.

Dr. G. Gopal
Assistant Professor (ECE), NIT Patna
 • Then the netlist is synthesized to come up with the gate level design.
• The next step is to map the logic blocks into available logic cells. This process is called the
technology-mapping. This is followed by placement and routing, which configures the CLBs
and defines interconnections.
• The next step is to generate the bit-stream and download the bit-stream into an FPGA chip
with the help of a software interface. Then the FPGA chip can function as desired as long as
the power is ON, or it is reprogrammed

Fig. 8 Typical FPGA architecture

Gate Array Design

• In a gate array (GA) structure, the transistors are fabricated on the silicon wafer. But the
interconnections are not fabricated.
• Depending on the array structure, the GA are of the following three types: (i) Channelled (ii)
Channel-less (iii) Structured
• In the channelled gate array architecture, there are rows of transistors called arrays and channels
are provided between the rows of transistors for their interconnections.
• In the channel-less gate array there are no channels between the rows. As there are no channels
in the channel-less architecture, the interconnections are made by drawing metal lines through
the unused transistors.
• In case of the structured GA architecture, either channelled or channel-less structure can be
used, but the only difference is that it includes custom blocks.

Dr. G. Gopal
Assistant Professor (ECE), NIT Patna
 Fig. 9 Gate array (GA) architecture: (a) channelled; (b) channel-less; (c) structured

Standard Cell-based Design

• The standard cell-based integrated circuit refers to a class of integrated circuits which uses the
pre-designed, pre-tested, and pre-characterized standard cells.
• The standard cells include basic logic gates (AND, OR, NAND, NOR, XOR, XNOR, NOT,
etc.), some mega cells (such as multiplexer, full-adder, decoder, etc.), sequential elements
(such as D flip-flop, scan-FF, flip-flop with direct set/reset/clear inputs, registers, etc.), input–
output buffers (I/O cells), and some special cells. Figure 10 describes the architecture of a
standard cell-based design.

Fig. 10 Standard cell-based architecture

Full-custom Design
• In the full-custom design, the designers do not use the pre-designed standard cell library.
Instead, they design the entire chip from the scratch. As each and every part is designed in this
approach, the chips are highly optimized for area, power, and delay. Hence, a full-custom
design is always superior to any other design style.

Semi-custom Design

Dr. G. Gopal
Assistant Professor (ECE), NIT Patna
 • In this style of design, almost all the basic building blocks are used from the standard cell
library.
• Only few cells are designed from the beginning, which are not available in the standard cell
library or to be optimized for a specific target.
• This approach is faster compared to the full-custom style but slower than the standard cell-
based design. Performance-wise also, it is superior to the standard cell-based design but inferior
to the full-custom design.
Programmable Logic Device (PLD)
• Programmable logic devices (PLDs) are standard products, which can be programmed to obtain
the desired functionality required for a specific application.
• The PLDs are classified into three categories based on the architecture and programmability.
(i) Read only memory (ROM) (ii) Programmable array logic (PAL) (iii) Programmable logic
array (PLA)

Design Domains(Y-Chart)
• The design process, at various levels, is usually evolutionary in nature. It starts with a given set
of requirements.
• Initial design is developed and tested against the requirements. When requirements are not met,
the design has to be improved.
• The Y-chart (first introduced by D. Gajski) shown in Fig. 11 illustrates a design flow for most
logic chips, using design activities on three different axes (domains) which resemble the letter
"Y."

Fig. 11: Typical VLSI design flow in three domains (Y-chart representation).
• The Y-chart consists of three domains of representation, namely (i) behavioral domain, (ii)
structural domain, and (iii) geometrical layout domain.
• The design flow starts from the algorithm that describes the behavior of the target chip. The
corresponding architecture of the processor is first defined. It is mapped onto the chip surface
by floorplanning.
Dr. G. Gopal
Assistant Professor (ECE), NIT Patna
 • The next design evolution in the behavioral domain defines finite state machines (FSMs) which
are structurally implemented with functional modules such as registers and arithmetic logic
units (ALUs). These modules are then geometrically placed onto the chip surface using CAD
tools for automatic module placement followed by routing, with a goal of minimizing the
interconnects area and signal delays.
• The third evolution starts with a behavioral module description. Individual modules are then
implemented with leaf cells. At this stage the chip is described in terms of logic gates (leaf
cells), which can be placed and interconnected by using a cell placement and routing program.
• The last evolution involves a detailed Boolean description of leaf cells followed by a transistor
level implementation of leaf cells and mask generation.

Quiz:
Q 1. What is VLSI Q. 2 Who predicted that the Q. 3 Why is CMOS
technology primarily number of devices on a chip technology widely used in IC
categorized by? would double every 18 fabrication?
A) The material used for months? A) It is the cheapest option
manufacturing chips A) Robert Noyce available
B) The level of integration of B) Gordon Moore B) It requires less power and
components into a single chip C) Jack Kilby area
C) The size of the chip D) Alan Turing C) It is faster than all other
D) The cost of the chip technologies
Answer: B) Gordon Moore D) It does not require silicon
Answer: B) The level of
integration of components Answer: B) It requires less
into a single chip power and area

Challenges of VLSI design- power, timing, area, noise,

testability, reliability, and yield
With the advancement of the CMOS IC technology, the dimensions have reduced from the micron
to submicron to nanometer regime. This aggressive device scaling has manifested new issues for
the IC designers.
Power:
• An important issue is increase in power dissipation of the integrated circuits. With a
large number of devices packed into a small area, the power dissipation in a chip is
almost 1 kW which is equivalent of 10 filament bulbs of 100 W!
• A good design must have high speed, low power dissipation, and energy consumption.

Timing & Area

• The performance of the ICs is measured in terms of how many million operations can be
performed per unit time. This indicates that the performance is dependent upon how fast
circuits can respond to an input.
• In other words, the propagation delay through the circuits or devices must be reduced
from microseconds to nanoseconds for migrating a design from an operating frequency
of MHz to GHz.
• Figure 12 illustrates how the propagation delay through the circuits depends on process
(P), voltage (V), and temperature (T) conditions, which are very often called PVT or PTV

Dr. G. Gopal
Assistant Professor (ECE), NIT Patna
 conditions. Typically, when the ICs are fabricated using a particular technology node, the
devices are intended to have the target dimensions.
• For example, if a circuit is fabricated using 180 nm technology node, the gate length of
the transistors must be 180 nm. But due to process variations during manufacturing, the
fabricated transistors would not have the same gate length.

Fig. 12 (a) Delay vs process technology; (b) delay vs power supply voltage; (c) delay vs
operating temperature
• Hence, the transistors with gate length lesser than the nominal value will be faster, and
the transistors with gate length greater than the nominal value will be slower. Similar to
the delay variation due to process variation, the delay also varies with the power supply
voltage and operating temperature.
• As the voltage is increased, delay through the devices reduces; and if the temperature is
increased, delay through the devices increases. More importantly, optimizing all three
parameters, i.e., area, speed, and power cannot be achieved simultaneously.
• Reducing the area must be traded off with increase in delay, or speed can be achieved
with the sacrifice of chip area and power. A typical delay vs chip area plot is shown in
Fig. 13

Fig. 13 Delay vs chip area

The processing speed of the design must be high so that high frequency inputs can be applied to
its input.
Noise & Reliability
• Noise in VLSI, such as crosstalk, power supply noise, and electromagnetic interference,
degrades signal integrity and impacts circuit performance. A good design must have large
noise margins.
Testability
Dr. G. Gopal
Assistant Professor (ECE), NIT Patna
 • Testing complex circuits for defects is time-consuming and costly.
• Design for Testability (DFT): Techniques like scan chains and built-in self-test (BIST)
are required.
• Fault Coverage: Higher fault coverage is needed to detect manufacturing defects.
• Post-Silicon Validation: Identifying and fixing bugs after fabrication is complex.

Yield

CAD tools for VLSI design

Computer-aided design (CAD) tools are essential for timely development of integrated circuits.
The CAD technology for VLSI chip design can be categorized into the following areas:
• High level synthesis
• Logic synthesis
• Circuit optimization
• Layout
• Simulation Design rules checking
Synthesis Tools The high-level synthesis tools using hardware description languages (HDLs),
such as VHDL or Verilog, address the automation of the design phase in the top level of the
design hierarchy.
Layout Tools The tools for circuit optimization are concerned with transistor sizing for
minimization of delays and with process variations, noise, and reliability hazards. The layout
CAD tools include floorplanning, place-and-route and module generation.
Below is a list of widely used CAD tools for VLSI design, categorized by their primary functions:

1. Schematic Capture and Design Entry

Dr. G. Gopal
Assistant Professor (ECE), NIT Patna
 • Cadence Virtuoso: Industry-standard tool for schematic entry, custom IC design,
and simulation.
• Synopsys Custom Compiler: Provides schematic capture and custom design
capabilities.
• Mentor Graphics (Siemens EDA) Xpedition: Used for schematic design and PCB
integration.

2. Simulation and Verification

SPICE Simulators:
• Cadence Spectre: High-performance SPICE simulator for analog and mixed-signal
circuits.
• Synopsys HSPICE: Industry-standard SPICE tool for accurate circuit simulation.
• LTspice: Free SPICE simulator from Analog Devices, suitable for smaller designs.

Digital Simulators:
• Mentor Graphics ModelSim: Popular for digital logic simulation.
• Cadence Xcelium: Advanced digital and mixed-signal simulation.
• Synopsys VCS: High-performance Verilog simulator for digital designs.

Mixed-Signal Simulators:

• Cadence AMS Designer: For mixed-signal simulation.

• Synopsys FineSim: Supports both analog and digital simulation.

3. Logic Synthesis
• Synopsys Design Compiler: Industry-leading tool for logic synthesis.
• Cadence Genus Synthesis Solution: Advanced synthesis tool for RTL-to-GDSII
flow.
• Mentor Graphics Precision Synthesis: Supports FPGA and ASIC synthesis.

4. Place and Route (P&R)

• Cadence Innovus: High-performance tool for physical design and place-and-
route.
• Synopsys IC Compiler II: Comprehensive P&R tool for advanced nodes.
• Mentor Graphics (Siemens EDA) Olympus-SoC: For digital implementation and
P&R.
5. Timing Analysis
• Synopsys PrimeTime: Industry-standard static timing analysis (STA) tool.
• Cadence Tempus Timing Signoff Solution: For advanced timing analysis and
signoff.
• Mentor Graphics (Siemens EDA) Tessent: Focused on timing and testability.

6. Physical Verification and DRC/LVS

• Cadence Pegasus Verification System: For physical verification and signoff.
• Synopsys IC Validator: Performs DRC (Design Rule Checking) and LVS (Layout
vs. Schematic).
• Mentor Graphics (Siemens EDA) Calibre: Industry-leading tool for DRC, LVS,
and DFM (Design for Manufacturability).
Dr. G. Gopal
Assistant Professor (ECE), NIT Patna
7. Analog and Mixed-Signal Design
• Cadence Virtuoso ADE (Analog Design Environment): For analog and mixed-
signal simulation.
• Synopsys CustomSim: Provides fast and accurate analog/mixed-signal
simulation.
• Keysight ADS (Advanced Design System): For RF and analog design.

8. FPGA Design Tools

• Xilinx Vivado: For designing and implementing FPGA-based systems.
• Intel Quartus Prime: For Intel (Altera) FPGA designs.
• Lattice Diamond: For Lattice FPGA designs.

9. Formal Verification
• Synopsys VC Formal: For formal verification of RTL designs.
• Cadence JasperGold: Advanced formal verification tool.
• Mentor Graphics (Siemens EDA) Questa Formal: For formal property
verification.

10. Power Analysis and Optimization

• Synopsys PrimePower: For power analysis and optimization.
• Cadence Voltus: Provides power integrity and analysis.
• Mentor Graphics (Siemens EDA) PowerPro: For power estimation and
optimization.

11. Emerging Tools and Open-Source Options

• OpenROAD: Open-source tool for autonomous chip design (RTL-to-GDSII).
• Magic VLSI Layout Tool: Open-source layout editor for VLSI design.
• Qflow: Open-source digital design flow for synthesis and place-and-route.

12. System-Level Design and Verification

• MATLAB/Simulink: For system-level modeling and simulation.
• Cadence System C: For system-level design and verification.
• Synopsys Platform Architect: For system-level exploration and optimization.

13. DFM (Design for Manufacturability)

• Synopsys Proteus: For lithography simulation and DFM.
• Mentor Graphics (Siemens EDA) Calibre DFM: For manufacturability analysis.

14. Educational and Free Tools

• Electric VLSI Design System: Open-source tool for VLSI design.
• NGSPICE: Open-source SPICE simulator.
• Icarus Verilog: Open-source Verilog simulation tool.

15. Cloud-Based Tools

• Cadence Cloud Solutions: Cloud-based design and simulation tools.
• Synopsys Cloud: Cloud-based EDA tools for VLSI design.
• OpenROAD Cloud: Cloud-based open-source design flow.
Dr. G. Gopal
Assistant Professor (ECE), NIT Patna