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Pipelining_Numerical_Questions

The document presents a series of numerical questions related to pipelining in processors, covering topics such as speedup calculation, throughput and latency, pipeline efficiency, stalling impact, delay slot usage, pipeline clock cycle time, and instructions in the pipeline. Each question includes specific calculations and formulas to derive the answers. The focus is on understanding the performance improvements and metrics associated with pipelined processors.

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mairaawan52
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0 views

Pipelining_Numerical_Questions

The document presents a series of numerical questions related to pipelining in processors, covering topics such as speedup calculation, throughput and latency, pipeline efficiency, stalling impact, delay slot usage, pipeline clock cycle time, and instructions in the pipeline. Each question includes specific calculations and formulas to derive the answers. The focus is on understanding the performance improvements and metrics associated with pipelined processors.

Uploaded by

mairaawan52
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Pipelining Numerical Questions

Q1. Speedup Calculation:

A non-pipelined processor takes 5 ns to execute each instruction. A pipelined version takes 1 ns per

stage with 5 stages. Calculate the speedup.

Formula: Speedup = Execution time (non-pipelined) / Execution time (pipelined)

Q2. Throughput and Latency:

If a pipelined processor has 4 stages, each taking 2 ns, calculate:

1. The time to execute 1 instruction

2. The time to execute 10 instructions

3. The throughput

Hint: Latency = 4 * 2 ns = 8 ns, Throughput = 1 instruction per clock cycle

Q3. Pipeline Efficiency:

A pipeline has 6 stages, each taking 3 ns. If 10 instructions are executed, find:

1. The total time taken

2. The speedup over a non-pipelined processor (assuming 6x3 = 18 ns per instruction)

3. The efficiency

Formula: Efficiency = (Speedup / Number of stages) * 100%

Q4. Stalling Impact:

In a 5-stage pipeline, every 4th instruction causes a stall of 1 cycle. Find the average CPI (Cycles

per Instruction).

Hint: CPI = 1 + 1/4 = 1.25

Q5. Delay Slot Usage:

Assume a program has 100 branch instructions. If delayed branch technique allows one delay slot

to be filled 70% of the time with useful instructions, how many cycles are saved?

Hint: Without delay slot fill = 100 stalls, with fill = 30 stalls, cycles saved = 70
Q6. Pipeline Clock Cycle Time:

If the slowest pipeline stage takes 10 ns and others are faster, what should be the clock cycle time

for the whole pipeline?

Answer: 10 ns (determined by the slowest stage)

Q7. Instructions in Pipeline:

If each pipeline stage takes 4 ns and there are 5 stages, how many instructions are in execution

after 20 ns?

Answer: 5 instructions (20 ns / 4 ns = 5 clock cycles)

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