UNIT - 3

Control Unit:
Computer perform task on the basis of instruction provided. A instruction in computer comprises of groups
called fields. These field contains different information as for computers every thing is in 0 and 1 so each field
has different significance on the basis of which a CPU decide what so perform. The most common fields are:
 Operation field which specifies the operation to be performed like addition.
 Address field which contain the location of operand, i.e., register or memory location.
 Mode field which specifies how operand is to be founded.
A instruction is of various length depending upon the number of addresses it contain. Generally CPU
organization are of three types on the basis of number of address fields:
 Single Accumulator organization
 General register organization
 Stack organization

In first organization operation is done involving a special register called accumulator. In second on multiple
registers are used for the computation purpose. In third organization the work on stack basis operation due to
which it does not contain any address field. It is not necessary that only a single organization is applied a blend
of various organization is mostly what we see generally.

On the basis of number of address instruction are classified as:

Note that we will use X = (A+B)*(C+D) expression to showcase the procedure.
Zero Address Instructions –

A stack based computer do not use address field in instruction.To evaluate a expression first it is converted to
revere Polish Notation i.e. Post fix Notation.
Expression: X =
(A+B)*(C+D) Postfixed :
X = AB+CD+* TOP means
top of stack

PUSH A TOP = A

PUSH B TOP = B

ADD TOP = A+B

PUSH C TOP = C

PUSH D TOP = D

ADD TOP = C+D

MUL TOP = (C+D)*(A+B)

POP X M[X] = TOP

One Address Instructions –

This use a implied ACCUMULATOR register for data manipulation.One operand is in accumulator and other
is in register or memory location.Implied means that the CPU already know that one operand is in accumulator
so there is no need to specify it.

Expression: X =
(A+B)*(C+D) AC is
accumulator
M[] is any memory location
 LOAD A AC = M[A]

ADD B AC = AC + M[B]

STORE T M[T] = AC

LOAD C AC = M[C]

ADD D AC = AC + M[D]

MUL T AC = AC * M[T]

STORE X M[X] = AC

Two Address Instructions –

This is common in commercial computers.Here two address can be specified in the instruction.Unlike earlier
in one address instruction the result was stored in accumulator here result cab be stored at different location
rather than just accumulator, but require more number of bit to represent address.

Here destination address can also contain operand.

Expression: X =
(A+B)*(C+D) R1, R2 are
registers

MOV R1, A R1 = M[A]

ADD R1, B R1 = R1 + M[B]

MOV R2, C R2 = C
 ADD R2, D R2 = R2 + D

MUL R1, R2 R1 = R1 * R2

MOV X, R1 M[X] = R1

Three Address Instructions –

This has three address field to specify a register or a memory location. Program created are much short in size
but number of bits per instruction increase. These instructions make creation of program much easier but it
does not mean that program will run much faster because now instruction only contain more information but
each micro operation (changing content of register, loading address in address bus etc.) will be performed in
one cycle only.

Expression: X =
(A+B)*(C+D) R1, R2 are
registers
Computer Organization | Different Instruction Cycles
Registers Involved In Each Instruction Cycle:
Memory address registers(MAR) : It is connected to the address lines of the system bus. It specifies the
address in memory for a read or write operation.
Memory Buffer Register(MBR) : It is connected to the data lines of the system bus. It contains the value to be
stored in memory or the last value read from the memory.
Program Counter(PC) : Holds the address of the next instruction to be fetched.
Instruction Register(IR) : Holds the last instruction fetched.
The Instruction Cycle –
Each phase of Instruction Cycle can be decomposed into a sequence of elementary micro- operations. In the
above examples, there is one sequence each for the Fetch, Indirect, Execute and Interrupt Cycles.

The Indirect Cycle is always followed by the Execute Cycle. The Interrupt Cycle is always followed by the
Fetch Cycle. For both fetch and execute cycles, the next cycle depends on the state of the system.
We assumed a new 2-bit register called Instruction Cycle Code (ICC). The ICC designates the state of
processor in terms of which portion of the cycle it is in:- 00 : Fetch Cycle
01 : Indirect Cycle 10 : Execute Cycle 11 : Interrupt Cycle
At the end of the each cycles, the ICC is set appropriately.The above flowchart
of Instruction Cycle describes the complete sequence of micro-operations, depending only on the instruction
sequence and the interrupt pattern(this is a simplified example). The operation of the processor is described as
the performance of a sequence of micro- operation.
Different Instruction Cycles:
The Fetch Cycle –
At the beginning of the fetch cycle, the address of the next instruction to be executed is in the Program
Counter(PC).
Step 1: The address in the program counter is moved to the memory address register(MAR), as this is the only
register which is connected to address lines of the system bus.

Step 2: The address in MAR is placed on the address bus, now the control unit issues a READ command on
the control bus, and the result appears on the data bus and is then copied into the memory buffer
register(MBR). Program counter is incremented by one, to get ready for the next instruction.(These two action
can be performed simultaneously to save time)
Step 3: The content of the MBR is moved to the instruction register(IR).

Thus, a simple Fetch Cycle consist of three steps and four micro-operation. Symbolically, we can write these
sequence of events as follows:-
Here ‘I’ is the instruction length. The notations (t1, t2, t3) represents successive time units. We assume that a
clock is available for timing purposes and it emits regularly spaced clock pulses. Each clock pulse defines a
time unit. Thus, all time units are of equal duration. Each micro-operation can be performed within the time of
a single time unit.
First time unit: Move the contents of the PC to MAR.
Second time unit: Move contents of memory location specified by MAR to MBR. Increment content of PC by
I.
Third time unit: Move contents of MBR to IR.
Note: Second and third micro-operations both take place during the second time unit.
The Indirect Cycles –
Once an instruction is fetched, the next step is to fetch source operands. Source Operand is being fetched by
indirect addressing( it can be fetched by
any addressing mode, here its done by indirect addressing). Register-based operands need not be fetched. Once
the opcode is executed, a similar process may be needed to store the result in main memory. Following micro-
operations takes place:-
Step 1: The address field of the instruction is transferred to the MAR. This is used to fetch the address of the
operand.
Step 2: The address field of the IR is updated from the MBR.(So that it now contains a direct addressing rather
than indirect addressing)
Step 3: The IR is now in the state, as if indirect addressing has not been occurred.
Note: Now IR is ready for the execute cycle, but it skips that cycle for a moment to consider the Interrupt
Cycle .
The Execute Cycle
The other three cycles(Fetch, Indirect and Interrupt) are simple and predictable. Each of them requires simple,
small and fixed sequence of micro-operation. In each case same micro-operation are repeated each time
around.
Execute Cycle is different from them. Like, for a machine with N different opcodes there are N different
sequence of micro-operations that can occur.
Lets take an hypothetical example :- consider an add instruction:

Here, this instruction adds the content of location X to register R. Corresponding micro-operation will be:-

We begin with the IR containing the ADD instruction. Step 1: The address portion of IR is loaded into the
MAR.
Step 2: The address field of the IR is updated from the MBR, so the reference
memory location is read.
Step 3: Now, the contents of R and MBR are added by the ALU. Lets take a complex example :-

Here, the content of location X is incremented by 1. If the result is 0, the next instruction will be skipped.
Corresponding sequence of micro-operation will be :-

Here, the PC is incremented if (MBR) = 0. This test (is MBR equal to zero or not) and action (PC is
incremented by 1) can be implemented as one micro-operation. Note : This test and action micro-operation can
be performed during the same time unit during which the updated value MBR is stored back to memory.
The Interrupt Cycle:
At the completion of the Execute Cycle, a test is made to determine whether any enabled interrupt has
occurred or not. If an enabled interrupt has occurred then Interrupt Cycle occurs. The natare of this cycle
varies greatly from one machine to another.
Lets take a sequence of micro-operation:-
Step 1: Contents of the PC is transferred to the MBR, so that they can be saved for return.
Step 2: MAR is loaded with the address at which the contents of the PC are to be saved.
PC is loaded with the address of the start of the interrupt-processing routine. Step 3: MBR, containing the old
value of PC, is stored in memory.
Note: In step 2, two actions are implemented as one micro-operation. However, most processor provide
multiple types of interrupts, it may take one or more micro- operation to obtain the save_address and the
routine_address before they are transferred to the MAR and PC respectively.

Difference between Horizontal and Vertical micro- programmed Control Unit

Basically, control unit (CU) is the engine that runs the entire functions of a computer with the help of control
signals in the proper sequence. In the micro-
programmed control unit approach, the control signals that are associated with the operations are stored in
special memory units. It is convenient to think of sets of control signals that cause specific micro-operations to
occur as being “microinstructions”. The sequences of microinstructions could be stored in an internal
“control” memory.
Micro-programmed control unit can be classified into two types based on the type of Control Word stored in
the Control Memory, viz., Horizontal micro-programmed control unit and Vertical micro-programmed control
unit.
In Horizontal micro-programmed control unit, the control signals are represented in the decoded binary
format, i.e., 1 bit/CS. Here ‘n’ control signals require n bit encoding. On the other hand.
In Vertical micro-programmed control unit, the control signals are represented in the encoded binary format.
Here ‘n’ control signals require log2n bit encoding.

RISC

RISC (reduced instruction set computer) is a microprocessor that is designed to perform a smaller number
of computer instruction types, so it can operate at a higher speed, performing more millions of instructions per
second, or MIPS. Since each instruction type that a computer performs requires additional transistors and
circuitry, a larger list or set of computer instructions tends to make the microprocessor more complicated and
operate slower.
  The RISC architecture utilises simple instructions.
 RISC synthesises complex data types and supports few simple data types.
 RISC makes use of simple addressing modes and fixed length instructions for pipelining.
 RISC allows any register to be used in any context.
 RISC has only one cycle for execution time.
 The work load of a computer that has to be performed is reduced by operating the “LOAD” and
“STORE” instructions.
 RISC prevents various interactions with memory, it does this by have a large number of registers.
 Pipelining in RISC is carried out relatively simply. This is due to the execution of instructions being
done in a uniform interval of time (i.e. one click).
 More RAM is required to store assembly level instructions.
 Reduced instructions need a smaller number of transistors in RISC.
 RISC utilises the Harvard architecture
 To execute the conversion operation, a compiler is used. This allows the conversion of high-level
language statements into code of its form.
 RISC processors utilise pipelining.
 Pipelining is a process that involves improving the performance of the CPU.
 The process is completed by fetching, decoding, and executing cycles of three separate instructions
at the same time.
Advantages of RISC processors
 Due to the architecture having a set of instructions, this allows high level language compilers to
produce more efficient code.
 This RISC architecture allows simplicity, which therefore means that it allows developers the freedom
to utilise the space on the microprocessor.
 RISC processors make use of the registers to pass arguments and to hold local variables.
 RISC makes use of only a few parameters, furthermore RISC processors cannot call instructions, and
therefore, use a fixed length instruction, which is easy to pipeline.
 Using RISC, allows the execution time to be minimised, whilst increasing the speed of the overall
operation, maximising efficiency.
  As mentioned above, RISC is relatively simple, this is due to having very few instructional formats,
and a small number of instructions and a few addressing modes required.
Disadvantages of RISC processors
 The performance of RISC processors depends on the compiler or the programmer. The following
instructions might rely on the previous instruction to finish their execution.
 RISC processors require very fast memory systems to feed various instructions, thus a large memory
cache is required.

Pipelining

Pipelining is the process of accumulating instruction from the processor through a pipeline. It allows storing
and executing instructions in an orderly process. It is also known as pipeline processing.

Pipelining is a technique where multiple instructions are overlapped during execution. Pipeline is divided into
stages and these stages are connected with one another to form a pipe like structure. Instructions enter from
one end and exit from another end.

Pipelining increases the overall instruction throughput.

In pipeline system, each segment consists of an input register followed by a combinational circuit. The register
is used to hold data and combinational circuit performs operations on it. The output of combinational circuit is
applied to the input register of the next segment.

Pipeline system is like the modern day assembly line setup in factories. For example in a car manufacturing
industry, huge assembly lines are setup and at each point, there are robotic arms to perform a certain task, and
then the car moves on ahead to the next arm.
 Types of Pipeline

It is divided into 2 categories:

1. Arithmetic Pipeline

2. Instruction Pipeline

Arithmetic Pipeline

Arithmetic pipelines are usually found in most of the computers. They are used for floating point operations,
multiplication of fixed point numbers etc. For example: The input to the Floating Point Adder pipeline is:

X = A*2^a

Y = B*2^b

Here A and B are mantissas (significant digit of floating point numbers), while a and b are exponents.

The floating point addition and subtraction is done in 4 parts:

1. Compare the exponents.

2. Align the mantissas.

3. Add or subtract mantissas

4. Produce the result.

Registers are used for storing the intermediate results between the above operations.

Instruction Pipeline
In this a stream of instructions can be executed by overlapping fetch, decode and execute phases of an
instruction cycle. This type of technique is used to increase the throughput of the computer system.
An instruction pipeline reads instruction from the memory while previous instructions are being executed in
other segments of the pipeline. Thus we can execute multiple instructions simultaneously. The pipeline will be
more efficient if the instruction cycle is divided into segments of equal duration.

Pipeline Conflicts
There are some factors that cause the pipeline to deviate its normal performance. Some of these factors are
given below:
1. Timing Variations
All stages cannot take same amount of time. This problem generally occurs in instruction processing where
different instructions have different operand requirements and thus different processing time.

2. Data Hazards
When several instructions are in partial execution, and if they reference same data then the problem arises. We
must ensure that next instruction does not attempt to access data before the current instruction, because this
will lead to incorrect results.

3. Branching
In order to fetch and execute the next instruction, we must know what that instruction is. If the present
instruction is a conditional branch, and its result will lead us to the next instruction, then the next instruction
may not be known until the current one is processed.

4. Interrupts
Interrupts set unwanted instruction into the instruction stream. Interrupts effect the execution of instruction.

5. Data Dependency
It arises when an instruction depends upon the result of a previous instruction but this result is not yet
available.

Advantages of Pipelining
1. The cycle time of the processor is reduced.
2. It increases the throughput of the system
3. It makes the system reliable.

Disadvantages of Pipelining
1. The design of pipelined processor is complex and costly to manufacture.
2. The instruction latency is more.
 Differences between Hardwired Control unit and Micro-programmed Control unit

There are various differences between Micro-programmed CU and Hardwired CU, which are described as
follows:

Hardwired Control Unit Micro-programmed Control Unit

With the help of a hardware circuit, we can implement While with the help of programming, we can
the hardwired control unit. In other words, we can say implement the micro-programmed control unit.
that it is a circuitry approach.

The hardwired control unit uses the logic circuit so that The micro-programmed CU uses microinstruction so
it can generate the control signals, which are required that it can generate the control signals. Usually,
for the processor. control memory is used to store these
microinstructions.

In this CU, the control signals are going to be It is very easy to modify the micro-programmed
generated in the form of hard wired. That's why it is control unit because the modifications are going to be
very difficult to modify the hardwired control unit. performed only at the instruction level.

In the form of logic gates, everything has to be realized The micro-programmed control unit is less costly as
in the hardwired control unit. That's why this CU is compared to the hardwired CU because this control
more costly as compared to the micro-programmed unit only requires the microinstruction to generate the
control unit. control signals.

The complex instructions cannot be handled by a The micro-programmed control unit is able to handle
hardwired control unit because when we design a the complex instructions.
circuit for this instruction, it will become complex.

Because of the hardware implementation, the The micro-programmed control unit is able to
hardwired control unit is able to use a limited number generate control signals for many instructions.
of instructions.

The hardwired control unit is used in those types of The micro-programmed control unit is used in those
computers that also use the RISC (Reduced instruction types of computers that also use the CISC (Complex
Set Computers). instruction Set Computers).

In the hardwired control unit, the hardware is used to In this CU, the microinstructions are used to generate
generate only the required control signals. That's why the control signals. That's why this CU is slower than
this control unit is faster as compared to the micro- the hardwired control unit.
programmed control unit.
Comparison between Horizontal micro-programmed control unit and Vertical micro- programmed control
unit:

HORIZONTAL Μ-PROGRAMMED CU VERTICAL Μ-PROGRAMMED CU

It supports longer control word. It supports shorter control word.
It allows higher degree of parallelism. If degree
is n, then n Control Signals are enabled at a It allows low degree of parallelism i.e., degree of
time. parallelism is either 0 or 1.
Additional hardware in the form of decoders are required to
No additional hardware is required. generate control signals.
It is faster than Vertical micro- programmed it is slower than Horizontal micro-programmed control
control unit. unit.
It is less flexible than Vertical micro- It is more flexible than Horizontal micro- programmed
programmed control unit. control unit.
Horizontal micro-programmed control unit uses
horizontal microinstruction, where every bit in Vertical micro-programmed control unit uses vertical
the control field microinstruction, where a code is used for each action to be
attaches to a control line. performedand thedecoder
translates this code into individual control
Example: Consider a hypothetical Control Unit which supports 4 k words. The Hardware contains 64 control
signals and 16 Flags. What is the size of control word used in bits and control memory in byte using:
Horizontal Programming
Vertical programming
Solution:

a)For Horizontal

64 bits for 64 signals

Control Word Size = 4 + 64 + 12 = 80 bits

Control Memory = 4 kW = ( (4* 80) / 8 ) = 40 kByte

a)For Vertical
6 bits for 64 signals i.e log264

Control Word Size = 4 + 6 + 12 = 22 bits

Control Memory = 4 kW = ( (4* 22) / 8 ) = 11 kByte