VietNam National University

University of Engineering and Technology

EMBEDDED SYSTEM FUNDAMENTALS

(ELT3240, NHẬP MÔN HỆ THỐNG NHÚNG)

Dr. Nguyễn Kiêm Hùng

Email: [email protected]
 Introduction to VietNam National University
Week
Embedded Systems 1-2
University of Engineering
Introduction to CandWeek
Technology
Languague 3

CPU: Week
ARM Cortex-M 4

Curriculum Memory
and Bus
Week
5-6

Path I/O Interfaces Week

7

Embedded Software Week

8-9

Real-time Week
Operating systems 10-12

Interfacing Embedded Week

With Real-World 13-14

Project Week
15
 Objectives

In this lecture you will be introduced to:

– Input and output mechanisms: Polling and
Interrupt
– Interrupt Concepts and Operation

3
 Outline
• Input and Output Programming
• I/O Mechanism: Polling vs. Interrupt
• Interrupt Mechanism
• Summary

4
 I/O devices
• Usually includes some analog or nonelectronic component.
• Typical digital interface to CPU:
– Includes data, status, and control registers accessed by CPU.
– Some registers may be read-only, while others may be
readable or writable

Ctrl,
Status

mechanism
regs
CPU
data
regs

5
 I/O Addressing: memory-mapped I/O and standard I/O

• Processor talks to both memory and peripherals using

same bus – two ways to talk to peripherals
– Memory-mapped I/O
• Peripheral registers occupy addresses in same address space as
memory
• e.g., Bus has 16-bit address
– lower 32K addresses may correspond to memory
– upper 32K addresses may correspond to peripherals
– Standard I/O (I/O-mapped I/O)
• Additional pin (M/IO) on bus indicates whether a memory or
peripheral access
• e.g., Bus has 16-bit address
– all 64K addresses correspond to memory when M/IO set to 0
– all 64K addresses correspond to peripherals when M/IO set to 1

6
 I/O Programming
• Two types of instructions can support I/O:
– special-purpose I/O instructions;
– memory-mapped load/store instructions.
• Intel x86 provides in, out instructions.
– provide a separate address space for I/O devices
• Most other CPUs (e.g. ARM processors) use
memory-mapped I/O:
– Memory-mapped I/O enables software to view these registers
as locations in memory.
– These registers can be accessed using only Load and Store
instructions
• I/O instructions do not preclude memory-mapped
I/O.

7
 ARM memory-mapped I/O

• Define location for device:

DEV1 EQU 0x1000
• Read/write code:
LDR r1,#DEV1 ; set up device adrs
LDR r0,[r1] ; read DEV1
MOV r0,#8 ; set up value to write
STR r0,[r1] ; write value to device

8
 I/O Programming
• A peripheral requires an initialization
process before it can be used
• Initialization process includes:
– Programming the clock control circuitry
– Configuring the operation mode of the I/O pins
• multiplexed I/O pins that can be used for multiple purposes be
necessary to configure to the expected modes (input/output
direction, function, etc.) electrical characteristics (e.g. voltage, pull
up/down, open drain, etc.).
– Peripheral configuration
– Interrupt configuration

9
 Outline
• Input and Output Programming
• I/O Mechanism: Polling vs. Interrupt
• Interrupt Mechanism
• Summary

11
 Polling vs. Interrupt
• Suppose a peripheral intermittently receives
data, which must be serviced by the processor
– The processor can poll the peripheral regularly to
see if data has arrived – wasteful (S/W solution)
– The peripheral can interrupt the processor when it
has data
• Int (H/W solution) requires an extra pin or pins:
If Int is 1, processor suspends current program,
jumps to an Interrupt Service Routine (ISR)
– Known as interrupt-driven I/O
– Essentially, “polling” of the interrupt pin is built-into
the hardware, so no extra time!
12
 Polling
Polling
 Continuously
checking the status of a
peripheral; e.g. read
data from an input
keyboard.

 Polling is relatively
straightforward in
design and
programming with the
sacrifice of system
performance.

13
 Interrupt
• Polling is very inefficient.
– CPU can’t do other work while testing device,
therefore hard to do simultaneous I/O.
– it is difficult to define priorities between different
services using polling
– it is not energy efficient
• Interrupts allow a device to change the flow of
control in the CPU.
– Causes subroutine call to handle device (interrupt
handler).
14
 Interrupt
Interrupt Process
 Device “interrupts” CPU to
indicate that it needs service. (These
events only occur if the interrupt is
enabled.)
 CPU waits until the current
instruction has finished being
executed.
 Save the contents of internal
registers of the CPU & the state
information within Control Unit
 The PC is loaded with address of
the Interrupt Service Routine (ISR)
 ISR is executed.
 CPU returns to where it left off in
15
the main program.
 Polling vs. Interrupt
Polling Interrupt

16
 Outline
• Programming Input and Output
• Polling vs. Interrupt
• Interrupt Mechanism
• Summary

17
 Interrupt
Interrupt Handler Features:
• Differs from subroutine because it is executed at any time due to
interrupt, not due to Call

• Should be implemented as small as possible

• Should be executed in short-time.

18
 Debugging interrupt code
• What if you forget to save registers?
– Foreground program can exhibit mysterious bugs.
– Bugs will be hard to repeat---depend on interrupt
timing.
Foreground Code:
y = Ax + b:
for (i = 0; i < M; i++) {
y[i] = b[i];
for (j = 0; j < N; j++)
y[i] = y[i] + A[i,j]*x[j];
}

19
 Interrupt
• How to determine the address (interrupt
address vector) of the ISR?
– Fixed interrupt
• Address built into microprocessor, cannot be changed
• Either ISR stored at address or a jump to actual ISR
stored if not enough bytes available
– Vectored interrupt
• Peripheral must provide the address
• Common when microprocessor has multiple peripherals
connected by a system bus

20
 Interrupt-driven I/O using fixed ISR location

1(a): P is executing its main Program memory μP Data memory

program ISR
16: MOV R0, 0x8000
System bus
1(b): P1 receives input data in a 17: # modifies R0
register with address 0x8000. 18: MOV 0x8001, R0
19: RETI # ISR return
... Int P1 P2
Main program
... PC 0x8000 0x8001
100: instruction
101: instruction

22
 Interrupt-driven I/O using fixed ISR location

2: P1 asserts Int to request Program memory μP Data memory

servicing by the microprocessor ISR
16: MOV R0, 0x8000
System bus
17: # modifies R0
18: MOV 0x8001, R0
19: RETI # ISR return
... Int P1 P2
Main program 1
... PC 0x8000 0x8001
100: instruction
101: instruction

23
 Interrupt-driven I/O using fixed ISR location

3: After completing instruction at Program memory μP Data memory

100, P sees Int asserted, saves ISR
the PC’s value of 100, and sets 16: MOV R0, 0x8000
System bus
PC to the ISR fixed location of 16. 17: # modifies R0
18: MOV 0x8001, R0
19: RETI # ISR return
... Int P1 P2
Main program
... PC 0x8000 0x8001
100: instruction
101: instruction 100

24
 Interrupt-driven I/O using fixed ISR location

4(a): The ISR reads data from Program memory μP Data memory
0x8000, modifies the data, and ISR
writes the resulting data to 16: MOV R0, 0x8000
17: # modifies R0 System bus
0x8001.
18: MOV 0x8001, R0
4(b): After being read, P1 19: RETI # ISR return
... Int P1 P1 P2
deasserts Int.
Main program 0
... PC 0x8000 0x8001
100: instructio
101: ninstruction 100

25
 Interrupt-driven I/O using fixed ISR location

5: The ISR returns, thus restoring Program memory μP Data memory

PC to 100+1=101, where P ISR
resumes executing. 16: MOV R0, 0x8000
System bus
17: # modifies R0
18: MOV 0x8001, R0
19: RETI # ISR return
... Int P1 P2
Main program
... PC 0x8000 0x8001
100: instruction
100 +1
101: instruction

26
Interrupt-driven I/O using vectored interrupt

intr request
status

mechanism
intr ack reg
PC
IR

CPU
data/address data
reg

• CPU and device are connected by CPU bus.

• CPU and device handshake:
– device asserts interrupt request;
– CPU asserts interrupt acknowledge when it can handle the
interrupt.
– peripheral provides this address on the data bus 27
Interrupt-driven I/O using vectored interrupt

:CPU :device

receive
request
receive
ack
receive
vector

28
Interrupt-driven I/O using vectored interrupt

1(a): µP is executing its main Program memory μP Data memory

program ISR
1(b): P1 receives input data in a 16: MOV R0, 0x8000
17: # modifies R0 System bus
register with address 0x8000.
18: MOV 0x8001, R0
19: RETI # ISR return
... Inta P1 P2
Main program Int
... PC 16
100: instruction 0x8000 0x8001
101: instruction 100

30
Interrupt-driven I/O using vectored interrupt

2: P1 asserts Int to request servicing Program memory μP Data memory

by the microprocessor ISR
16: MOV R0, 0x8000
17: # modifies R0 System bus
18: MOV 0x8001, R0
19: RETI # ISR return
... Inta P1 P2
Main program Int
... PC 1 16
100: instruction 0x8000 0x8001
101: instruction 100

31
Interrupt-driven I/O using vectored interrupt

3: After completing instruction at Program memory μP Data memory

100, μP sees Int asserted, saves the ISR
PC’s value of 100, and asserts Inta 16: MOV R0, 0x8000
17: # modifies R0 System bus
18: MOV 0x8001, R0
19: RETI # ISR return 1
... Inta P1 P2
Main program Int
... PC 16
100: instruction 0x8000 0x8001
101: instruction 100

32
Interrupt-driven I/O using vectored interrupt

4: P1 detects Inta and puts interrupt Program memory μP Data memory

address vector 16 on the data bus ISR
16: MOV R0, 0x8000
17: # modifies R0 16 System bus
18: MOV 0x8001, R0 bus
19: RETI # ISR return
... Inta P1 P2
Main program Int
... PC 16
16
100: instruction 0x8000 0x8001
101: instruction 100

33
Interrupt-driven I/O using vectored interrupt

5(a): PC jumps to the address on the Program memory μP Data memory

bus (16). The ISR there reads data ISR
from 0x8000, modifies the data, and 16: MOV R0, 0x8000
17: # modifies R0 System bus
writes the resulting data to 0x8001. bus
18: MOV 0x8001, R0
5(b): After being read, P1 deasserts 19: RETI # ISR return
... Inta P1 P1 P2 P2
Int. Int
Main program
... PC 0 16
100: instruction 0x8000 0x8001
101: instruction 100

34
Interrupt-driven I/O using vectored interrupt

6: The ISR returns, thus restoring Program memory μP Data memory

the PC to 100+1=101, where the μP ISR
resumes 16: MOV R0, 0x8000
17: # modifies R0 System bus
18: MOV 0x8001, R0
19: RETI # ISR return
... Int P1 P2
Main program
... PC 0x8000 0x800
100: instructio
100 + 1
101: ninstruction
instruction
1

35
 Quiz

What Are the Difference between Exceptions

and Interrupts ?

• Exceptions/Interrupts are events that cause changes in program

flow control outside a normal code sequence.
• The events could either be external or internal:
• External source : Interrupt or interrupt request (IRQ)
• Interrupt handler, or interrupt service routine (ISR)
• Internal source: Exceptions
• Exception handler

37
 Priorities and vectors
• Two mechanisms allow us to make interrupts
more flexible:
– Priorities determine what interrupt gets CPU first.
– Interrupt vectors Table allows the different
interrupting devices to be handled by different
handler
• Vectors number (or Interrupt number) determine what
code is called for each type of interrupt.
• Handler address points to Interrupt entry point in memory
• Mechanisms are orthogonal: most CPUs provide
both.
38
 Interrupt vectors
Vector Number
Addres of handler 0 Vector 0
Addres of handler 1 Vector 1
Addres of handler 2 Vector 2

Addres of handler 3 Vector 3

• CPU acknowledges request.

• Device sends vector.
• CPU calls handler.
• Software processes request.
• CPU restores state to foreground program. 39
 Prioritized interrupts
• Prioritized interrupts allow the CPU to ignore less important
interrupt requests while it handles more important requests

device 1 device 2 device n

interrupt
Acknowledge
(m bits)
L1 L2 .. Ln
CPU

40
 Prioritized interrupts

• The priority mechanism must ensure that a

lower-priority interrupt does not occur when
a higher-priority interrupt is being handled.
• Masking: interrupt with priority lower than
current priority is not recognized until
pending interrupt is complete.
• Non-maskable interrupt (NMI): highest-
priority, never masked.
– Often used for power-down.
41
 Example: Prioritized I/O

:interrupts :foreground :A :B :C

A,B

42
 Prioritized interrupts

How to solve the case in which the number of I/O

devices is more than the number of interrupt priority
levels?

Device 0 Device 1 Device 2 Device 3 Device 4

L1 L2 L3
CPU 43
 Prioritized interrupts

Device 1 Device 1 Device 2 Device 3 Device 3

L1 L2 L3
CPU

Use a mixture of interrupt-driven and polling methods to construct the

program
44
 Outline
• Programming Input and Output
• Polling vs. Interrupt
• Interrupt Mechanism
– Interrupt implementation in Cortex-M
• Summary

46
Interrupt Management in Cortex-M Processors
• Nested Vectored Interrupt Controller (NVIC)

4747
 ARM Cortex-M’s Exception Model
• An exception may be an
internal interrupt or a
hardware error.
• Each exception has exception
number, priority number and
vector address
• Vector table base address is
fixed at 0x00
• Vector table is normally
defined in the startup codes
(startup.s)
48
 ARM Cortex-M3’s Exception Model
 SP value: the reset value of the
stack pointer.
 Reset is invoked on power up or a
warm reset
 A Non-Maskable Interrupt (NMI)
 A HardFault is an exception that
occurs because of an error.
• A Supervisor Call (SVC) is an
exception that is triggered by the
SVC instruction
• PendSV is an interrupt-driven
request for system-level service
• a SysTick exception is generated
when the SysTick timer reaches
zero
49
 ARM Cortex-M’s Exception Model
• Interrupt management
Excp. Number Exception Type Priority Excp. Number Exception Type Priority

1 Reset -3 (highest) 13 Reserved NA

2 NMI -2 14 PendSV Programmable

3 Hard Fault -1 15 SysTick Programmable

4 MemManage Fault Programmable 16 Interrupt #0 Programmable

5 Bus Fault Programmable 17 Interrupt #1 Programmable

6 Usage Fault Programmable …

7-10 Reserved NA 47 Interrupt #31 Programmable

11 SVC Programmable …

12 Debug Monitor Programmable 255 Interrupt #239 Programmable

5050
ARM Cortex-M’s Exception Model

Vector Table Usage:

In the case of an exception,
the core:

• Reads the vector handler

address for the exception
from the vector table

• Branches to the handler

5151
ARM Cortex-M’s Exception Model
Vector Table Implementation (Startup.s in uVision):
; Vector Table Mapped to Address 0 at Reset

AREA RESET, DATA, READONLY

EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
…

5353
 ARM Exception Sequence

• CPU actions:
– Save PC. Copy CPSR to SPSR.
– Force bits in CPSR to record interrupt.
– Force PC to Exception handler.
• Handler responsibilities:
– Restore proper PC.
– Restore CPSR from SPSR.
– Clear interrupt disable flags.

54
 ARM Exception Sequence
An exception entrance sequence contains:
1. Stacking of a number of registers
2. Fetching the exception vector
3. Fetching the instructions for the exception handler to be
executed.
4. Update NVIC and core registers

5555
 ARM Exception Sequence

Exception handler execution:

1. The processor is in Handler mode
– The Main Stack Pointer (MSP) is used for stack
operations
– The processor is executing in privileged access
level
2. Nested Interrupt: If a higher-priority
exception arrives, the currently executing
handler will be suspended and pre-empted
5656
 Interrupt Latency
• Interrupt latency refers to the delay from the
start of the interrupt request to the start of the
interrupt handler execution.
• The best-case latency for Cortex-M3/4 is 12
cycles, including:
– Cycles for stacking the registers, vector fetch, and
fetching instructions for the interrupt handler
– Memory system has zero latency,
– The bus system design allows vector fetch and
stacking to happen at the same time.
58
 Exception handling optimization
Cortex-M processors use a number of methods to
reduce the latency of servicing interrupts:
• Tail chaining

• Late arrival

• Pop preemption

5959
 Exception handling optimization

Tail chaining:

6060
 Exception handling optimization

Late arrival:

6161
 Exception handling optimization

Pop preemption:

6262
 Summary
• The two major styles of I/O are polled and interrupt driven
– Interrupts may be vectorized and prioritized
– Nested Vectored Interrupt Controller (NVIC) for interrupt handling

63
 Quiz

Q1: Why do most computer systems use memory-mapped I/O?

Q2: Why do most programs use interrupt-driven I/O over polling?
Q3: Write ARM code that tests a register at location ds1 and continues execution
only when the register is nonzero.
Q3: Write ARM code that waits for the low-order bit of device register ds1
to become 1 and then reads a value from register dd1.
Q4: What is polling? Draw a software flow diagram for polling three I/O
peripheral devices? What are drawbacks of polling method?
Q5: What is interrupt-driven I/O? Draw a software flow diagram for interrupt-
driven access of three I/O peripheral devices?
Q6: Describe steps performed by an CPU when it responds to an interrupt
Q7: Distinguish between interrupt, exception.

64
 Quiz

Q9: Why do most programs use interrupt-driven I/O over polling I/O? When
would you prefer to use polling I/O over interrupt-driven I/O?

65