Module -IV

Registers
• A register is a group of flip‐flops, each one of which shares a
common clock and is capable of storing one bit of
information.
• An n ‐bit register consists of a group of n flip-flops capable of
storing n bits of binary information.
• In its broadest definition, a register consists of a group of
flip-flops together with gates that affect their operation.
• The flip-flops hold the binary information, and the gates
determine how the information is transferred into the
register.
 Register with Parallel Load
• The transfer of new information into a register is
referred to as loading or updating the register. If all
the bits of the register are loaded simultaneously
with a common clock pulse, we say that the loading
is done in parallel.
• A four-bit data-storage register with a load control
input that is directed through gates and into the D
inputs of the flip‐flops is shown in Fig .
• The load input to the register
determines the action to be taken
with each clock pulse.
• When the load input is 1, the data at
the four external inputs are
transferred into the register with the
next positive edge of the clock.
• When the load input is 0, the outputs
of the flip-flops are connected to their
respective inputs.
• The feedback connection from output
to input is necessary because a D
flip‐flop does not have a “no change”
condition. With each clock edge, the D
input determines the next state of the
register.
• To leave the output unchanged, it is
necessary to make the D input equal
to the present value of the output
 SHIFT REGISTERS
• A register capable of shifting the binary information held in
each cell to its neighboring cell, in a selected direction, is
called a shift register.
• The logical configuration of a shift register consists of a chain
of flip-flops in cascade, with the output of one flip-flop
connected to the input of the next flip-flop.
• All flip-flops receive common clock pulses, which activate the
shift of data from one stage to the next.
• The simplest possible shift register is one that uses only
flip-flops. The output of a given flip-flop is connected to the D
input of the flip‐flop at its right.
• This shift register is unidirectional (left-to-right). Each clock
pulse shifts the contents of the register one bit position to the
right.
 Sequential Logic
Counters and Registers

 Synchronous (Parallel) Counters

 Up/Down Synchronous Counters
 Designing Synchronous Counters
 Decoding A Counter
 Counters with Parallel Load
 Sequential Logic
Counters and Registers
Counters
 Introduction: Counters
 Asynchronous (Ripple) Counters
 Asynchronous Counters with MOD number <
n
2
 Asynchronous Down Counters
 Sequential Logic
Counters and Registers
Registers
 Introduction: Registers
 Simple Registers
 Registers with Parallel Load
 Using Registers to implement Sequential Circuits
 Shift Registers
 Serial In/Serial Out Shift Registers
 Serial In/Parallel Out Shift Registers
 Parallel In/Serial Out Shift Registers
 Parallel In/Parallel Out Shift Registers
 Sequential Logic
Counters and Registers

 Bidirectional Shift Registers

 Shift Register Counters
Ring Counters
Johnson Counters

 Random-Access Memory (RAM)

 Introduction: Counters
 Counters are circuits that cycle through a specified
number of states.
 Two types of counters:
 synchronous (parallel) counters
 asynchronous (ripple) counters
 Ripple counters allow some flip-flop outputs to be
used as a source of clock for other flip-flops.
 Synchronous counters apply the same clock to all
flip-flops.
Synchronous (Parallel) Counters
 Synchronous (parallel) counters: the flip-flops are
clocked at the same time by a common clock pulse.
 We can design these counters using the sequential
logic design process .
 Example: 2-bit synchronous binary counter (using T
flip-flops, or JK flip-flops with identical J,K inputs).

Present Next Flip-flop

state state inputs
00 01 A1 A0 A1+ A0+ TA1 TA0
0 0 0 1 0 1
11 10 0 1 1 0 1 1
1 0 1 1 0 1
1 1 0 0 1 1
Synchronous (Parallel) Counters
 Example: 2-bit synchronous binary counter (using T
flip-flops, or JK flip-flops with identical J,K inputs).
Present Next Flip-flop
state state inputs
A1 A0 A1+ A0+ TA1 TA0 TA1 = A0
0 0 0 1 0 1
0 1 1 0 1 1 TA0 = 1
1 0 1 1 0 1
1 1 0 0 1 1

A0 J A1
J Q Q
C C
Q' K Q'
K

CLK
Synchronous (Parallel) Counters
 Example: 3-bit synchronous binary counter (using T
flip-flops, or JK flip-flops with identical J, K inputs).
Present Next Flip-flop
state state inputs
A2 A1 A0 A2+ A1+ A0+ TA2 TA1 TA0
0 0 0 0 0 1 0 0 1
0 0 1 0 1 0 0 1 1
0 1 0 0 1 1 0 0 1
0 1 1 1 0 0 1 1 1
1 0 0 1 0 1 0 0 1
1 0 1 1 1 0 0 1 1
1 1 0 1 1 1 0 0 1
1 1 1 0 0 0 1 1 1
A1 A1 A1
1 1 1 1 1 1 1
A2 1 A2 1 1 A2 1 1 1 1

A0 A0 A0
TA2 = A1.A0 TA1 = A0 TA0 = 1
Synchronous (Parallel) Counters
 Example: 3-bit synchronous binary counter (cont’d).
TA2 = A1.A0 TA1 = A0 TA0 = 1

A2 A1 A0

Q Q Q
J K J K J K
CP
1
Synchronous (Parallel) Counters
 Example: 4-bit synchronous binary counter.
TA3 = A2 . A1 . A0
TA2 = A1 . A0
TA1 = A0
TA0 = 1

1 A1.A0 A2.A1.A0

A0 J A1 J A2 J A3
J Q Q Q Q
C C C C
Q' K Q' K Q' K Q'
K

CLK
Synchronous (Parallel) Counters
 Example: Synchronous decade/BCD counter.
Clock pulse Q3 Q2 Q1 Q0
Initially 0 0 0 0
1 0 0 0 1 T0 = 1
2 0 0 1 0
3 0 0 1 1 T1 = Q3'.Q0
4 0 1 0 0
5 0 1 0 1 T2 = Q1.Q0
6 0 1 1 0
7 0 1 1 1 T3 = Q2.Q1.Q0 + Q3.Q0
8 1 0 0 0
9 1 0 0 1
10 (recycle) 0 0 0 0
Synchronous (Parallel) Counters
 Example: Synchronous decade/BCD counter
(cont’d).
T0 = 1
T1 = Q3'.Q0
T2 = Q1.Q0
T3 = Q2.Q1.Q0 + Q3.Q0

Q0

1 T T Q1 T Q2 T Q3
Q Q Q Q
C C C C
Q' Q' Q' Q'

CLK
Up/Down Synchronous Counters
 Up/down synchronous counter: a
bidirectional counter that is capable of
counting either up or down.
 An input (control) line Up/Down (or simply
Up) specifies the direction of counting.
 Up/Down = 1  Count upward
 Up/Down = 0  Count downward
Up/Down Synchronous Counters
 Example: A 3-bit up/down synchronous
binary counter.
Clock pulse Up Q2 Q1 Q0 Down
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1

TQ0 = 1 Up counter Down counter

TQ1 = (Q0.Up) + (Q0'.Up' ) TQ0 = 1 TQ0 = 1
TQ2 = ( Q0.Q1.Up ) + (Q0'. Q1'. Up' ) TQ1 = Q0 TQ1 = Q0’
TQ2 = Q0.Q1 TQ2 = Q0’.Q1’
Up/Down Synchronous Counters
 Example: A 3-bit up/down synchronous
binary counter (cont’d).
TQ0 = 1
TQ1 = (Q0.Up) + (Q0'.Up' )
TQ2 = ( Q0.Q1.Up ) + (Q0'. Q1'. Up' )

Q0 Q1

1 T T T Q2
Q Q Q
Up C C C
Q' Q' Q'

CLK
Designing Synchronous Counters
 Example: A 3-bit Gray 100
000
001
code counter (using JK 101 011
flip-flops).
111 010
110
Present Next Flip-flop
state state inputs
Q2 Q1 Q0 Q2+ Q1+ Q0+ JQ2 KQ2 JQ1 KQ1 JQ0 KQ0
0 0 0 0 0 1 0 X 0 X 1 X
0 0 1 0 1 1 0 X 1 X X 0
0 1 0 1 1 0 1 X X 0 0 X
0 1 1 0 1 0 0 X X 0 X 1
1 0 0 0 0 0 X 1 0 X 0 X
1 0 1 1 0 0 X 0 0 X X 1
1 1 0 1 1 1 X 0 X 0 1 X
1 1 1 1 0 1 X 0 X 1 X 0
Designing Synchronous Counters
 3-bit Gray code counter: flip-flop inputs.

Q1Q0 Q1Q0 Q1Q0

Q2 Q2 00 01 11 10 Q2 00 01 11 10
00 01 11 10
0 0 1 X X 0 1 X X
1
1 X X X X 1 X X 1 X X 1

JQ2 = Q1.Q0' JQ1 = Q2'.Q0 JQ0 = Q2.Q1 + Q2'.Q1'

= (Q2  Q1)'
Q1Q0 Q1Q0 Q1Q0
Q2 00 01 11 10 Q2 00 01 11 10 Q2 00 01 11 10
0 X X X X 0 X X 0 X 1 X
1 1 1 X X 1 1 X 1 X
KQ2 = Q1'.Q0' KQ1 = Q2.Q0 KQ0 = Q2.Q1' + Q2'.Q1
= Q2  Q1
Designing Synchronous Counters
 3-bit Gray code counter: logic diagram.
JQ2 = Q1.Q0' JQ1 = Q2'.Q0 JQ0 = (Q2  Q1)'
KQ2 = Q1'.Q0' KQ1 = Q2.Q0 KQ0 = Q2  Q1

Q0 Q1 Q2
J Q J Q J Q
C C C
Q1 Q2
K Q' K Q' ' K Q' '
Q0
'
CLK
Asynchronous (Ripple) Counters
 Asynchronous counters: the flip-flops do not
change states at exactly the same time as they do
not have a common clock pulse.
 Also known as ripple counters, as the input clock
pulse “ripples” through the counter – cumulative
delay is a drawback.
n
 n flip-flops  a MOD (modulus) 2 counter.
(Note: A MOD-x counter cycles through x states.)
 Output of the last flip-flop (MSB) divides the
input clock frequency by the MOD number of the
counter, hence a counter is also a frequency
divider.
• To understand the operation of the four-bit binary ripple counter, refer to
the first nine binary numbers listed in Table

• The count starts with binary 0 and increments by 1 with each count pulse
input. After the count of 15, the counter goes back to 0 to repeat the
count.
• The least significant bit, A0, is complemented with each count pulse
input. Every time that A0 goes from 1 to 0, it complements A1. Every time
that A1 goes from 1 to 0, it complements A2. Every time that A2 goes
from 1 to 0, it complements A3, and so on for any other higher order bits
of a ripple counter.
4 bit binary ripple counter
Asynchronous (Ripple) Counters
 Example: 4-bit ripple binary counter (negative-
edge triggered).
HIGH
Q0 Q1 Q2 Q3
J J J J
CLK C C C C
K K K K
FF0 FF1 FF2 FF3

CLK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Q0

Q1

Q2

Q3
Asynchronous (Ripple) Counters
 Example: 2-bit ripple binary counter.
 Output of one flip-flop is connected to the clock
input of the next more-significant flip-flop.
HIGH

J Q0 J Q1
CLK C C
Q0
K K

FF0 FF1

CLK 1 2 3 4

Q0 Timing diagram
Q0 0 1 0 1 0 00  01  10  11  00 ...
Q1 0 0 1 1 0
Asynchronous (Ripple) Counters
 Example: 3-bit ripple binary counter.
HIGH

J Q0 J Q1 J Q2
CLK C Q0 C Q1 C
K K K
FF0 FF1 FF2

CLK 1 2 3 4 5 6 7 8

Q0 0 1 0 1 0 1 0 1 0

Q1 0 0 1 1 0 0 1 1 0

Q2 0 0 0 0 1 1 1 1 0

Recycles back to 0
Asynchronous (Ripple) Counters
 Propagation delays in an asynchronous (ripple-
clocked) binary counter.
 If the accumulated delay is greater than the clock
pulse, some counter states may be misrepresented!

CLK 1 2 3 4

Q0

Q1

Q2
tPHL (CLK to Q0) tPHL (CLK to Q0)
tPLH (Q0 to Q1) tPHL (Q0 to Q1)
tPLH
(CLK to Q0) tPLH (Q1 to Q2)
 n
Asyn. Counters with MOD no. < 2
 States may be skipped resulting in a truncated
sequence.
 Technique: force counter to recycle before going
through all of the states in the binary sequence.
 Example: Given the following circuit, determine the
counting sequence (and hence the modulus no.)

C B A
Q J Q J Q J
All J, K CLK CLK CLK
inputs Q K Q K Q K
CLR CLR CLR
are 1
(HIGH). B
C
 n
Asyn. Counters with MOD no. < 2
 Example (cont’d):
C B A
Q J Q J Q J
All J, K CLK CLK CLK
inputs Q K Q K Q K
CLR CLR CLR
are 1
(HIGH). B
C

1 2 3 4 5 6 7 8 9 10 11 12
Clock MOD-6 counter
A produced by
clearing (a MOD-8
B
binary counter)
C when count of six
NAND 1 (110) occurs.
Output 0
 n
Asyn. Counters with MOD no. < 2
 Example (cont’d): Counting sequence of
circuit (in CBA order).
1 2 3 4 5 6 7 8 9 10 11 12
Clock
A 0 1 0 1 0 1 0 1
B 0 0 1 1 0 0 0 0
C 0 0 0 0 1 1 0 0
NAND 1
Output 0

111 000
Temporary 001
state
Counter is a MOD-6
110 010 counter.

101 011
100
 n
Asyn. Counters with MOD no. < 2
 Exercise: How to construct an asynchronous MOD-
5 counter? MOD-7 counter? MOD-12 counter?
 Question: The following is a MOD-? counter?
F E D C B A
Q J Q J Q J Q J Q J Q J

Q K Q K Q K Q K Q K Q K
CLR CLR CLR CLR CLR CLR

C
D
E All J = K = 1.
F
 n
Asyn. Counters with MOD no. < 2
 Decade counters (or BCD counters) are counters
with 10 states (modulus-10) in their sequence.
They are commonly used in daily life (e.g.: utility
meters, odometers, etc.).
 Design an asynchronous decade counter.
(A.C)'

HIGH
D C B A
J Q J Q J Q J Q

CLK C C C C
K K K K
CLR CLR CLR CLR
 n
Asyn. Counters with MOD no. < 2
 Asynchronous decade/BCD counter (cont’d).
HIGH D C B A
J Q J Q J Q J Q (A.C)'
CLK C C C C
K K K K
CLR CLR CLR CLR

1 2 3 4 5 6 7 8 9 10 11
Clock
D 0 1 0 1 0 1 0 1 0 1 0
C 0 0 1 1 0 0 1 1 0 0 0
B 0 0 0 0 1 1 1 1 0 0 0
A 0 0 0 0 0 0 0 0 1 1 0
NAND
output
Asynchronous Down Counters
 So far we are dealing with up counters. Down
counters, on the other hand, count downward
from a maximum value to zero, and repeat.
3
 Example: A 3-bit binary (MOD-2 ) down counter.
1
Q0 Q1 Q2
J Q J Q J Q 3-bit binary
CLK C C C up counter
Q' K Q' K Q'
K

1
Q0 Q1 Q2
J Q J Q J Q 3-bit binary
CLK C C C down counter
Q' K Q' K Q'
K
Asynchronous Down Counters
 Example: A 3-bit binary (MOD-8) down counter.
000
001 111
1
Q0 Q1 Q2
J Q J Q J Q 010 110
CLK C C C
Q' K Q' K Q'
K
011 101
100

CLK 1 2 3 4 5 6 7 8

Q0 0 1 0 1 0 1 0 1 0

Q1 0 1 1 0 0 1 1 0 0

Q2 0 1 1 1 1 0 0 0 0
Cascading Asynchronous Counters
 Larger asynchronous (ripple) counter can be
constructed by cascading smaller ripple counters.
 Connect last-stage output of one counter to the
clock input of next counter so as to achieve higher-
modulus operation.
 Example: A modulus-32 ripple counter constructed
from a modulus-4 counter and a modulus-8
counter.
Q0 Q1 Q2 Q3 Q4

J Q J Q J Q J Q J Q
CLK C C C C C
Q' K Q' Q' K Q' K Q'
K K

Modulus-4 counter Modulus-8 counter

Cascading Asynchronous Counters
 Example: A 6-bit binary counter (counts from
0 to 63) constructed from two 3-bit counters.
A0 A1 A2 A3 A4 A5

Count 3-bit 3-bit

binary counter binary counter
pulse

A5 A4 A3 A2 A1 A0
0 0 0 0 0 0
0 0 0 0 0 1
0 0 0 : : :
0 0 0 1 1 1
0 0 1 0 0 0
0 0 1 0 0 1
: : : : : :
 Introduction: Registers
 An n-bit register has a group of n flip-flops and
some logic gates and is capable of storing n bits of
information.
 The flip-flops store the information while the gates
control when and how new information is
transferred into the register.
 Some functions of register:
 retrieve data from register
 store/load new data into register (serial or parallel)
 shift the data within register (left or right)
 Simple Registers
 No external gates.
 Example: A 4-bit register. A new 4-bit data is
loaded every clock cycle.
A3 A2 A1 A0

Q Q Q Q
D D D D
CP

I3 I2 I1 I0
 Registers With Parallel Load
 Instead of loading the register at every clock pulse,
we may want to control when to load.
 Loading a register: transfer new information into
the register. Requires a load control input.
 Parallel loading: all bits are loaded simultaneously.
Registers With Parallel Load
Load'.A0 + Load. I0
Load
D Q A0
I0

D Q A1
I1

D Q A2
I2

D Q A3
I3

CLK
CLEAR

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 Shift Registers
 Another function of a register, besides storage, is to
provide for data movements.
 Each stage (flip-flop) in a shift register represents
one bit of storage, and the shifting capability of a
register permits the movement of data from stage
to stage within the register, or into or out of the
register upon application of clock pulses.
 Shift Registers
 Basic data movement in shift registers (four
bits are used for illustration).
Data in Data out Data out Data in

(a) Serial in/shift right/serial out (b) Serial in/shift left/serial out

Data in Data in
Data in

Data out
Data out
(c) Parallel in/serial out (d) Serial in/parallel out
Data out
(e) Parallel in /
parallel out

(f) Rotate right (g) Rotate left

Serial In/Serial Out Shift Registers
 Accepts data serially – one bit at a time – and
also produces output serially.

Serial data Q0 Q1 Q2 Q3 Serial data

D Q D Q D Q D Q
input output
C C C C

CLK

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Serial In/Serial Out Shift Registers
 Application: Serial transfer of data from one
register to another.

SI SO SI SO
Shift register A Shift register B

Clock CP
Shift control

Clock

Shift Wordtime
control

CP
T1 T2 T3 T4
Serial In/Serial Out Shift Registers
 Serial-transfer example.
Timing Pulse Shift register A Shift register B Serial output of B
Initial value 1 0 1 1 0 0 1 0 0
After T1 1 1 0 1 1 0 0 1 1
After T2 1 1 1 0 1 1 0 0 0
After T3 0 1 1 1 0 1 1 0 0
After T4 1 0 1 1 1 0 1 1 1
Serial In/Parallel Out Shift Registers
 Accepts data serially.
 Outputs of all stages are available simultaneously.
Data input D Q D Q D Q D Q
C C C C

CLK

Q0 Q1 Q2 Q3

Data input D SRG 4

CLK C Logic symbol

Q0 Q1 Q 2 Q3
Parallel In/Serial Out Shift Registers
 Bits are entered simultaneously, but output is serial.
Data input

D0 D1 D2 D3
SHIFT/LOAD

Serial
D Q D Q D Q D Q data
Q0 Q1 Q2 Q3 out
C C C C

CLK
SHIFT.Q0 + SHIFT'.D1

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Parallel In/Serial Out Shift Registers
 Bits are entered simultaneously, but output is serial.

Data in

D0 D1 D2 D3

SHIFT/LOAD SRG 4
Serial data out
CLK C

Logic symbol

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Parallel In/Parallel Out Shift Registers
 Simultaneous input and output of all data bits.
Parallel data inputs

D0 D1 D2 D3

D Q D Q D Q D Q
C C C C

CLK

Q0 Q1 Q2 Q3

Parallel data outputs

 Bidirectional Shift Registers
Data can be shifted either left or right, using a control line RIGHT/LEFT (or simply RIGHT) to
indicate the direction.

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 Bidirectional Shift Registers
 Data can be shifted either left or right, using a
control line RIGHT/LEFT (or simply RIGHT) to
indicate the direction.

RIGHT/LEFT

Serial
data in

RIGHT.Q0 + D Q D Q D Q D Q Q3
RIGHT'.Q2 Q1 Q2
C C C C

Q0
CLK
 Shift Register Counters
 Shift register counter: a shift register with the serial
output connected back to the serial input.
 They are classified as counters because they give a
specified sequence of states.
 Two common types: the Johnson counter and the
Ring counter.
 Ring Counters
 One flip-flop (stage) for each state in the sequence.
 The output of the last stage is connected to the D
input of the first stage.
 An n-bit ring counter cycles through n states.
 No decoding gates are required, as there is an
output that corresponds to every state the counter
is in.
 Ring Counters
 Example: A 6-bit (MOD-6) ring counter.
PRE
Q0 Q1 Q2 Q3 Q4 Q5
D Q D Q D Q D Q D Q D Q

CLR
CLK

Clock Q0 Q1 Q2 Q3 Q4 Q5 100000
0 1 0 0 0 0 0
000001 010000
1 0 1 0 0 0 0
2 0 0 1 0 0 0
3 0 0 0 1 0 0 000010 001000
4 0 0 0 0 1 0
5 0 0 0 0 0 1 000100
 Johnson Counters
 The complement of the output of the last stage is
connected back to the D input of the first stage.
 Also called the twisted‐ring counter.
 Require fewer flip-flops than ring counters but
more flip-flops than binary counters.
 An n-bit Johnson counter cycles through 2n states.
 Require more decoding circuitry than ring counter
but less than binary counters.
 Johnson Counters
 Example: A 4-bit (MOD-8) Johnson counter.
Q0 Q1 Q2
D Q D Q D Q D Q
Q'
Q3'
CLR
CLK

Clock Q0 Q1 Q2 Q3 0000
0 0 0 0 0
0001 1000
1 1 0 0 0
2 1 1 0 0
3 1 1 1 0 0011 1100
4 1 1 1 1
5 0 1 1 1 0111 1110
6 0 0 1 1
7 0 0 0 1 1111
 Johnson Counters
 Decoding logic for a 4-bit Johnson counter.
Clock A B C D Decoding A'
0 0 0 0 0 A'.D' State 0
D'
1 1 0 0 0 A.B'
2 1 1 0 0 B.C' A
3 1 1 1 0 C.D' State 1
B'
4 1 1 1 1 A.D
5 0 1 1 1 A'.B B
State 2
6 0 0 1 1 B'.C C'
7 0 0 0 1 C'.D
C
State 3
D'
B' A
State 6 State 4
C D
C' A'
State 7 State 5
D B
Moore and Mealy state Machines:

https://www.youtube.com/watch?v=0_OZKWdCixw

https://www.youtube.com/watch?v=vdZKehWMJSM.

https://www.youtube.com/watch?v=HEVWx4irOx4.

https://www.youtube.com/watch?v=rkgbhngdJ5Y.

Sequence detectors:

https://www.youtube.com/watch?v=HXG_YPVNIsM

https://www.youtube.com/watch?v=XNAK-L7NlOM
 Using Registers to implement
Sequential Circuits
 A sequential circuit may consist of a register
(memory) and a combinational circuit.
Next-state value

Register Combin-
Clock ational
circuit
Inputs Outputs

 The external inputs and present states of the register

determine the next states of the register and the
external outputs, through the combinational circuit.
 The combinational circuit may be implemented by any
of the methods covered in MSI components and
Programmable Logic Devices.
 Using Registers to implement
Sequential Circuits
 Example 1:
A1+ = S m(4,6) = A1.x'
A2+ = S m(1,2,5,6) = A2.x' + A2'.x = A2  x
y = S m(3,7) = A2.x
Present Next
state Input State Output
A1 A2 x A1+ A2+ y
0 0 0 0 0 0 A1.x' A
0 0 1 0 1 0 1

0 1 0 0 1 0 A2x A2
0 1 1 0 0 1
1 0 0 1 0 0
x y
1 0 1 0 1 0
1 1 0 1 1 0
1 1 1 0 0 1