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layout

The document provides a step-by-step guide for designing the layout of a CMOS inverter using a specific software tool. It outlines the process of creating the layout, connecting components, placing pins, and performing design rule checks (DRC) and layout versus schematic (LVS) checks. The instructions include specific commands and settings to ensure proper alignment and connectivity of the circuit elements.

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dcdon4343
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Download as PDF, TXT or read online on Scribd
2 views

layout

The document provides a step-by-step guide for designing the layout of a CMOS inverter using a specific software tool. It outlines the process of creating the layout, connecting components, placing pins, and performing design rule checks (DRC) and layout versus schematic (LVS) checks. The instructions include specific commands and settings to ensure proper alignment and connectivity of the circuit elements.

Uploaded by

dcdon4343
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Layout Design of CMOS inverter

(1) Draw the circuit as shown below. To make the layout, all dc sources such as Vdc, ground should
be removed from the circuit and only the pins should be placed.
Press “p” to place pins.
Input pins are “vin, gnd, vdd” (direction “input”) and output pin is “vout” (direction “output”) (you
can name the pins as per your choice)

Click on “check and save”


(2) click on launch→layout XL→click on “create new, automatic” (if you are designing layout for the
first time, and if it is already designed then click on “open existing, automatic”)→OK
Don’t change any name in the opened window and check that view is “layout”

After that if any window comes, press “ok”


(3) “virtuoso layout” window will be minimized, open that window, it will look like as the following.

(4) click on “connectivity”→generate→all from source, the following window will be opened.

You can also untick the “In boundary” if you don’t want the boundary, there will be no affect on the
layout.
On the above window click on “I/O” pins, and change “layer” to “Metal 1 pin”, press “ok”
A window like below will be opened. The size of the devices may be different for everyone according
to the width of the devices.

(5) Press “E” and change the “snap modes” as create→anyangle, and edit→anyangle, click OK

Press “shift F”, something like below will be there.


(6) Drag the pmos or nmos by clicking on it. The “gate” (polysilicon/green rectangle) should be in
line for both pmos and nmos and there should be a vertical gap/space of atleast 1 um between PMOS
and NMOS as shown below. (use “k” to measure the space and “esc” to free exit from “k”)

(7) adjust the outer boundary if requires, press “s” (s for stretch), click on the line to be stretched and
drag the mouse and then click again. It will be stretched. (this step is not required if the boundary is
not selected in step 4)

(8) Make the connection as per CMOS circuit


(a) gate to gate connection: press “p”, place the mouse on “gate terminal” (green rectangle) of any
NMOS or PMOS and connect it with the other by clicking the mouse (it is the same thing like wire is
connected in the schematic).
The gate terminals of both the NMOS and PMOS should be properly aligned. (see the image)
Press “O”, select “via definition→M1_POLY1”→click “hide” and place the green box at the
connection of two gate terminals.

Press “p” and create a wire from “M1_POLY1” via as shown below.
(b) drain to drain connection: similarly, connect drain to drain, after pressing “p”, like previous step.

(c) PMOS source to VDD connection: right click on PMOS layout→ properties→click on
“parameter”, Change “bodytie type”→detached→press “ok”

Connect
these two by
pressing “p”
(d) NMOS source to bulk connection: right click on NMOSlayout→properties→Parameter→bodytie
type→detached→OK

Connect
these two by
pressing “p”

(9) Now place all the “pins” as per their need. Place “in” pin on the input wire, place VDD pin on the
source/body of the PMOS, place GND pin on the source/body of the NMOS and place “out” pin on
the drain to drain connection.

Save the layout after each 2-3 steps and save in the last.
(10) Click on “assura”→technology file→click on the three dots→then click on “two dots” on the
“file selector window”.
Browse the path “/home/install//Foundary/analog/180nm” then select “assura_tech.lib”, click “OK”
(if the technology file is already there as “assura_tech.lib” then this step is not required)
Design rule check (DRC) procedure:
(1) click assura→run DRC→select technology→gpdk180→press OK

(2) Wait for the progress or click OK, after that click “yes”
Following window should appear,

If above window is not there, then it will show about the errors in the layout, remove the errors.
Layout v/s Schematic (LVS) procedure:
(1) click assura→run LVS→change technology gpdk180→ok, if any message appears, click OK

After that following window should appear which shows that there are no LVS errors

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