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Introduction to FinFET

The document discusses Double-gate FET (DGFET) and FinFET technology, highlighting their structures, construction processes, and advantages over traditional MOSFETs. FinFETs provide better control over the channel, reduced short-channel effects, and lower leakage currents, making them suitable for advanced CMOS scaling. However, they also present challenges such as higher fabrication costs and difficulties in controlling dynamic threshold voltage.

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Shivam Kumar
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5 views

Introduction to FinFET

The document discusses Double-gate FET (DGFET) and FinFET technology, highlighting their structures, construction processes, and advantages over traditional MOSFETs. FinFETs provide better control over the channel, reduced short-channel effects, and lower leakage currents, making them suitable for advanced CMOS scaling. However, they also present challenges such as higher fabrication costs and difficulties in controlling dynamic threshold voltage.

Uploaded by

Shivam Kumar
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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INTRODUCTION

Double-gate FET (DGFET) can reduce Short Channel Effects (SCEs)


 Reduce Drain-Induced-Barrier-Lowering
 Improve Subthreshold Swing S
 A fin field-effect transistor (FinFET) is a multigate device, a
MOSFET (metal-oxide-semiconductor field-effect transistor) built
on a substrate where the gate is placed on two, three, or four sides of
the channel or wrapped around the channel, forming a double or
even multi gate structure.
STRUCTURE
Finfet structure and symbol:
Three Types of Double-gate FET

Quasi-CMOS structure
Relatively simple FAB
CONSTRUCTION OF A BULK SILICON-BASED FINFET
Substrate
Basis for a FinFET is a lightly p-doped substrate with a hard mask on top
(e.g. silicon nitride) as well as a patterned resist layer

Fin etch
The fins are formed in a highly anisotropic etch process. Since there is
no stop layer on a bulk wafer as it is in SOI, the etch process has to be
time based. In a 22 nm process the width of the fins might be 10 to 15
nm, the height would ideally be twice that or more.
Oxide deposition
To isolate the fins from each other a oxide deposition with a high
aspect ratio filling behavior is needed.

Planarization
The oxide is planarized by chemical mechanical polishing. The hard
mask acts as a stop layer.
Recess etch
Another etch process is needed to recess the oxide film to form a lateral
isolation of the fins.

Gate oxide
On top of the fins the gate oxide is deposited via thermal oxidation to
isolate the channel from the gate elctrode. Since the fins are still
connected underneath the oxide, a high-dose angled implant at the base of
the fin creates a dopant junction and completes the isolation (not
illstrated).
Deposition of the gate
Finally a highly n+-doped poly silicon layer is deposited on top of the fins,
thus up to three gates are wrapped around the channel: one on each side of
the fin, and - depending on the thickness of the gate oxide on top - a third
gate above.
The influence of the top gate can also be inhibited by the deposition of a
nitride layer on top of the channel.
Since there is an oxide layer on an SOI wafer, the channels are isolated
from each other anyway. In addition the etch process of the fins is
simplified as the process can be stopped on the oxide easily.
FINFET LAYOUT

 Layouts of FinFETs patterned with directlithography and spacer lithography


are analysed from a circuit density perspective.

 Requirements on the height of the fin to obtain competitive layout density


are derived.

 Spacer lithography will be required to obtain the layout density target with
reasonable values of fin height.
➢ FinFET like device architectures are expected to enable
CMOS scaling to 45nm.

➢ In such devices, the current flows on the vertical walls of


the fins and hence the effective device width (WEFF) is
different from the layout width.

➢ One of the primary requirements for FinFET’s to be a


technology enabler is that they must have at least the same
current drive as the planar technology for identical layout
area.

➢ We analyze the FinFET layouts for two patterning


technologies
(i) direct lithography patterning
(ii)spacer patterning.
➢ Layouts used for comparison are shown in above fig Mesa
isolation is adequate for FinFETs and is assumed in the
respective layouts.

➢ W is the width of the activeregion and S its length. L is the gate length
 Analysis

There are two components to the layout area

(i) width
(ii) the length of the active regions.

We analyse these components separately.

The result will be combined to derive conditions


for competitive layout area density.
 Device Width

For FinFETs,the effective device width is given by

WEFF = 2n HFIN (1)

where, n and HFIN are the number and height of the


fins respectively. For direct litho patterning the
layout width is given by

W = (n-1) PRX + WFINM (2)


n = 2,3,4,….
Length Of Active Region

 In the calculation of the length of the active area, the


dimensions of the source and drain areas are
constrained by the contact design rules, which are
assumed to be identical for planar and FinFET process
technologies.

 For direct lithography patterning


S (FFDL) = S + 2 DPCDL
Where, FFDL refers to FinFET direct lithography and
DPCDL is the gate to S/D edge design rule.
Mosfet Finfet
MOSFET is having four terminals Source, FinFET is totally different from the MOSFET.
Drain, Gate and Body. It is also known as In FinFET source and drain structure is look
Insulated gate FET. like a Fin and that Fin is incusing into the
substrate.

MOSFET is a transistor and it is used in both The channel surface is fully surrounded by the
digital and analog circuits. It is voltage control gate. Because to get the good command on the
device channel.
MOSFET having two mode, one is Depletion In FinFET, doping of impurities is very less
Mode and an-other one is Enhancement Mode. compared to the MOSFET

Current leakage and Drain Induced Barrier There are two ways to increase the drive
Lowering are more compared to the FinFET. current of FinFET device.

In MOSFET, while decreasing the Nano-meter One way of increasing the width of the channel
technology short channel effect is increases. It and another way is construct and connect the
consumes more power compared to the FinFET multi-Fins together.
technology.

In Depletion mode already inversion layer In FinFET, direct connection between source,
present without giving any voltage at gate drain and substrate due to this connection some
terminal. amount of leakage takes place. Due to the good
control on the channel by gate terminal,
Leakage Current

s.no Devices Leakage


Current
1 mosfet High
2 finfet Less (8.62x10^-8
nA)

Short Channel
Effect

s.no devices sce


1 mosfet high
2 finfet less
FINFET ADVANTAGES

 Better control over the channel


 Suppressed short-channel effects

 Lower static leakage current

 Faster switching speed

 Higher drain current (More drive-current per footprint)

 Lower switching voltage

 Low power consumption


FINFET DISADVANTAGES

 Difficult to control dynamic Vth


 Quantized device-width. It is impossible to make
fractions of the fins, whereby designers can only specify
the devices’ dimensions in multiples of whole fins.
 Higher parasitics due to 3-D profile

 Very high capacitances

 Corner effect: electric field at the corner is always


amplified compared to the electric field at the sidewall.
This can be minimized using a nitrate layer in corners.
 High fabrication cost
Thank you

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