The 8085 Memory:

o Memory is actually a circuit that can store bits__ high or low,

generally voltage levels or capacitive charges representing 1 and 0. A
flip-flop or a latch is a basic element of memory.

The memory stores binary instructions and data for the microprocessor.
The number of bits stored in a register is called a memory word. The
memory word length for 8-bit microprocessor should be 8 bits. (3b)

o In a memory chip, all registers are arranged in a sequence & identified

by binary numbers called memory addresses.
The 8085 has 16 address lines. That means it can address 216 = 64𝐾
memory locations. Then, it’ll need 1 memory chip with 64𝐾 locations,
or 2 chips with 32 K in each, or 4 chips with 16 K each or 16 chips of
the 4 K, etc.
how would we use these address lines to control the multiple
chips?
The Memory Organization (R/W Memory):
To communicate with the memory, the MPU should be able to
 Select the chip
 Identify the register
 Read from or write into the register (4)

Consider an 8-bit hypothetical memory chip of 8 registers with three

address lines, one chip select (𝐶𝑆) line, one read/write (R/W) line, and
eight I/O lines as shown in Fig below. The MPU uses the (𝐶𝑆) line to
select the chip and the (R/𝑊 ) line to control the data flow.

o The registers of a hypothetical chip are arranged sequential and

numbered 0002 to 1112 . These numbers are called memory
addresses for identifying each register as a memory location.

The 8085 MPU with its sixteen address lines is capable of identifying
or addressing 65,536 (64K) such memory registers or location. (5)
o For example, to read from or write
into a memory location or register 5,
the MPU places 𝟏𝟎𝟏𝟐 address on the
address bus and this register is
identified by decoding its address by
the decoder.
The control signal (R/𝑊 ) enables
the I/O lines, and the data byte is
either read from or stored in the
memory location. The chip select
Figure: A Memory Chip with 08
(𝐶𝑆) line also known as (𝐶𝐸) is
Registers.
needed to select one particular
memory chip from several memory
chips in a system.
Memory Map:
“The assignment of addresses to memory registers in various memory
chips in a system is called the memory map.” (6)
For example, memory map of 8085 μ-processor based system ranges
from 0000H to 𝐹𝐹𝐹𝐹H (216 = 65,536), which is analogous to identical
houses built in a sequence and their postal addresses (numbers).
o Assuming 10,000 houses are numbered by 04-digit decimal
numbers. In order to avoid cumbersomeness, the numbering scheme
can be devised with the concept of a block (row) and each block will
have 100 houses to be numbered with the last 02 digits from 00 to 99.
o Similarly, the blocks are also identified by the first two decimal digits,
e.g. a house with the number 0247is house number 47 in block 02.
In the binary number system, 16 binary digits can have 65,536 (216 )
different combinations. In the hexadecimal number system, 16
binary bits are equivalent to 04 Hex digits that can be used to assign
addresses to 65,536 memory registers from 0000H to FFFFH ---- 256
pages with 256 lines each (256 x 256 = 65,536). (7)
o So, a line (register) is equivalent to a house, a page is equivalent to a
block, and eight flip-flops in a register are equivalent to eight rooms in
in a house.
For example, the memory address 020FH represents line 15
(register) on page 2, the address 07FFH represents line 255 (register)
on page 7, and the address 1064H represents line 100 (register) on
page 16 (64H = 10010 and 10H = 1610 ).

Example: Illustrate the memory map of the chip with 256 bytes
(registers) of memory and 8 I/O lines as shown in Fig (a), and explain
how the memory map can be changed by altering the hardware of the
chip select (𝐶𝑆) line as shown in Fig (b).
o The memory size of this chip is expressed as 256 × 8. It has 08
address lines, one Chip Select (𝑪𝑺) line (active low), & one (R/𝑊 ) line.
The 08 address lines (𝐴7 − 𝐴0 ) of the MPU are required to identify 256
(28 ) memory registers. The 08 other address lines (𝐴15 − 𝐴8 ) are
connected to the Chip select (𝐶𝑆) line through inverters and NAND
gate. When this Chip select line goes low, the memory chip is enabled,
so the (𝐴15 − 𝐴8 ) should be at logic 0.
o Once the memory chip is selected, the address lines (𝐴7 − 𝐴0 ) can
assume any combination from 00H to FFH , and identify any one of
the 256 memory locations through its decoder. The control signal
(R/𝑊 ) enables data flow.
Chip Select Logic
𝐴15 𝐴14 𝐴13 𝐴12 𝐴11 𝐴10 𝐴9 𝐴8 𝐴7 𝐴6 𝐴5 𝐴4 𝐴3 𝐴2 𝐴1 𝐴0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = 0000H

0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 = 00FFH
(8)
(Memory Map)
o The memory map of the chip can be changed by modifying the
hardware; e.g. if the inverter on line 𝐴15 is removed as shown in Fig.
(b), the address required on lines (𝐴15 − 𝐴8 ) to enable the chip is:
𝐴15 𝐴14 𝐴13 𝐴12 𝐴11 𝐴10 𝐴9 𝐴8 (Memory Map)
1 0 0 0 0 0 0 0 = 80H 8000H to 80FFH
Important Points Regarding The Memory Map:
o Sixteen address lines (16 bits) of 8085 μ-processor can address
65,536 memory registers.
o In memory addressing, low-order addresses from 00H to 𝐹𝐹H are
viewed as line number and high-order addresses are viewed as page
numbers.
o For a given memory chip, the number of address lines required to
identify the registers is determined by number of registers in the
chip. The remaining address lines can be used for selecting the chip.
o The memory map of a given chip can be changed by changing the
hardware of the chip select (𝐶𝑆) or chip enable (𝐶𝐸) line.
Example: Memory Map of a 1K (𝟏𝟎𝟐𝟒 × 𝟖) Memory Chip
o The memory chip has 1024 registers, so 10 address lines (𝐴9 − 𝐴0 ) of
the MPU are needed to identify registers and the remaining 6 address
lines (𝐴15 − 𝐴10 ) are used for the chip select (𝐶𝑆).
o The memory chip is enabled, when the address lines (𝐴15 − 𝐴10 ) are
at logic 0. While the address lines (𝐴9 − 𝐴0 ) can assume any address
of the 1024 registers starting from all 0’s to all 1’s as:
Chip Select Logic
𝐴15 𝐴14 𝐴13 𝐴12 𝐴11 𝐴10 𝐴9 𝐴8 𝐴7 𝐴6 𝐴5 𝐴4 𝐴3 𝐴2 𝐴1 𝐴0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = 0000H

0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 = 03FFH
(9)
(Memory Map)
o The memory map ranges from from 0000H to 03FFH . In terms of
page analogy, this can be represented as memory having 04 pages:
00 00 Page 0 with 256 lines. 01 00 Page 1 with 256 lines.
00 FF 01 FF
02 00 Page 2 with 256 lines. 03 00 Page 3 with 256 lines.
02 FF 03 FF
o The memory map of 1K memory chip
can be altered to any other location
by changing the hardware of the
(𝐶𝑆) line; e.g. If the inverter of the
line 𝐴15 is removed, the memory map
will range from 8000H to 83FFH .

Memory Address Lines:

o It is necessary to know the relationship
b/w the number of registers in a
memory chip and the number of
address lines. Fig: Memory Map of 1024 bytes of
memory
For a chip with 256 registers, we
need 256 binary numbers to identify each register; and each address
line can assume only two logic sates: i.e. 0 and 1, so; it requires to find
the power of 2 that will give 256 combinations. It implies that:
Find 𝑥 where 2𝑥 = 256. By taking the log of both sides, we have:
• Here 𝑥 represents the number of address lines needed to obtain 256
binary numbers.
Example: Calculate the address lines required for an 8K-byte
(1024 × 8 = 8192 registers) memory chip.
log 8192
Solution: Number of address lines 𝑥 = = 13 address lines
log 2

Memory Word Size:

The size of a memory device (chip) is generally
specified in terms of the total number of bits it can store. The
memory chips are available in various word sizes like: 1, 4, & 8.
• On the other hand, the memory size in a given system is generally
specified in terms of bytes. Therefore, it is necessary to design a byte-
size memory word. For example, a memory chip of size 1024 × 4 has
1024 registers and each register can store 04 bits; it means it can store
a total of 4096 (1024 × 4 = 4096) bits.
• To design 1K-byte (1024 × 8) memory, two chips are required and
each chip will provide 04 data lines.
Example: Calculate the number of memory chips needed to design
8K-byte memory if the memory chip size is 1024 × 1.
8192 ×8
Solution: Number of memory chips= = 64
1024 ×1
Note: It means the chip 1024 × 1 has 1024 (1K) registers and each
registers can store 01-bit with 01 data line. 08 data lines are needed
for byte-size memory. So, 08 chips are necessary for 1K-byte memory.
For 8K-byte memory, we will need 64 chips.
Memory and Instruction Fetch: (How a Program is Executed)
o The Intel microprocessors work on the stored program concept, i.e.
instructions/programs and data are stored in memory. The memory
provide that information to MPU whenever the MPU requests for it.
To execute a program, microprocessor fetches the instructions one by
one from the memory and executes them in the same sequence. (10)
Example:
The instruction code
0100 1111 (4FH ) is
stored in memory
location 2005H .
Illustrate the data
flow and list the
sequence of events
when the instruction
code is fetched by the
MPU.
o The microprocessor performs the following steps to execute the
stored program:
1. The program counter places the 16-bit address 2005H of the
memory location having instruction on the address bus.
2. The control unit sends the memory read control signal (MEMR,
active low) to tell the memory that the MPU wants to read the
memory and thereby memory enable the addressed memory location.
3. The 8-bit instruction (4F) code in the memory location is placed
on the data bus and transferred (copied) to the instruction register (IR).
4. From IR, The opcode is then transferred to the instruction decoder
and machine cycle encoder. From there, the meaning of the opcode is
decoded and the number of machine cycles required to execute the
complete instruction.
5. The decoded opcode information is sent to the control unit so
that the control unit can generate the suitable control signal to execute
the instruction.
Types of Memory:
Memory can be classified into two groups, i.e. Prime (main) or
Storage memory. Prime memory is the memory, the MPU uses for
executing and storing programs, such as R/WM and ROM. The detail
classification is given in the Figure below. (10B)

o The storage memory includes, cassette tape, magnetic tape, flash

drive, and hard disk.
R/W Memory:
Also known as Random Access Memory (RAM) is volatile and made up
of registers, and each register has a group of flip-flops that stores bits of
information.
The number of bits stored in a register is known as a memory word
such as the memory word length of 8085 μ-processor should be eight
bits. (11)

The MPU can read or write into this memory. Two types of R/W memory
are available: Static and Dynamic,
o Static memory is made up of flip-flops that store a bit information as
voltage. The memory chip has low density but high speed.
o Dynamic memory is made up of a large number of MOSFET transistor
gates can be placed on a memory chip, which stores a bit as charge.
It has high density and is faster than static memory.
o The disadvantage is that the charge (information) leaks, that’s why
refreshing the memory is done which requires additional circuitry.
ROM:
ROM is nonvolatile memory that retains the stored information even if
the power is turned off. The information is permanently stored in the
ROM, like a song is recorded on a record. (12)

o ROM memory can be represented

functionally by matrix format of the
diodes as shown in the Fig. The
presence of a diode stores 1, and its
absence stores 0. This representation
is the simplified version of the actual
MOS FET memory cell.
o Each of the 8 horizontal rows can
be viewed as a register with binary
addresses ranging from 000 to 111.
When a register is selected, the
voltage of that line goes high, hence the output lines, where diodes are
connected, go high.
 For example, when the memory register 111 is selected, the data
byte 0111 1000 (78H ) can be read at the data lines 𝐷7 to 𝐷0 .
 MASKED ROM:
‒ a bit pattern is permanently recorded by the masking &
metallization process which is an expensive and specialized
process.
‒ it is economical only for production quantities in the thousands.

 PROM (Programmable Read-Only Memory):

‒ Nichrome or poly-silicon wires arranged in a matrix format and
functionally viewed as diodes or fuses as shown in above Fig.
‒ Can be programmed by the user with a special PROM programmer
that selectively burns the PROM according the bit pattern. The
information in the bit pattern stored permanent.

 EPROM (Erasable Programmable Read-Only Memory):

‒ The information stored in this memory is semi permanent, so the
memory chip can be reprogrammed again and again.
 ‒ All the information can be erased by exposing the memory to UV
light through a quartz window installed on the chip.
‒ Commonly used in product development/experimental projects.
 EEPROM (Electrically Erasable PROM):
‒ Functionally similar to EPROM, except the information can be
altered by using electrical signals at the register level rather than
erasing all the information.
‒ Its manufacturing process is quite complex, so it is expensive and
not in common use.

 In microprocessor controlled oven, programs are stored in ROM

while data which is likely to vary (baking period, temperature,
starting time) are entered in R/W memory through the keyboard.
 When microcomputer are used for developing software, programs
are written in R/W memory then stored on storage memory such
as cassette tape. (13)
 Flash Memory:
‒ This is a variation of EE-PROM that is becoming popular. The
major difference between the flash memory and EE-PROM is in
the erasure procedure. The EE-PROM can be erased at a register
level, but the flash memory must be erased either in its entirety
or at the sector (block) level.
‒ These can be erased and programmed at least a million times and
the power supply needed is around 12 V.