1) In bus arbitration interrupt, the

A) CPU detects interrupt first before mastering the bus B) various modules can master the bus at the same time
C) module places its vector on data bus first D) module masters the bus before it can raise interrupt
2) Each 80x86 can be connected directly to ______ interrupt controller(s) such as 8259A
A) one B) two C) multiple D) none of the above
3) The method which offers higher speeds of I/O transfers is
A) Interrupts B) DMA C) Memory D) Program I/O
mapping
4) In single bus-detached DMA module, the CPU is suspended
A) one time B) two times C) three times D) no times
5) The ______is used to separate high-performance from lower-performance bus
A) North bridge B) South bridge C) Bridge D) I/O module
6) The DMA transfers are performed by a circuit called
A) DMA interface B) DMA latch C) DMA controller D) DMA bus
7) After the completion of the DMA transfer, the processor is notified by
A) completion signal B) Acknowledge signal C) WMFC signal D) Interrupt signal
8) In memory-mapped I/O, the
A) I/O devices and the memory share the same address space B) I/O devices have a separate address space
C) memory and I/O devices have an associated address space D) part of the memory is specifically set aside for
the I/O operation
9) To resolve the clash over the access of the system BUS we use ______
A) Multiple BUS B) BUS arbitrator C) Priority access D) daisy chaining
10) The process wherein the processor constantly checks the I/O devices is called
A) Polling B) interrupting C) memory-mapped D) arbitration
11) The method which offers higher speeds of I/O transfers is called
A) Interrupts B) Memory mapping C) Program-controlled I/O D) DMA
12) The interrupt-request line may be considered as a part of the
A) data bus B) control bus C) address bus D) handshaking signals
13) The return address from the interrupt-service routine is stored on a
A) special stack B) register C) bus D) memory address
14) The signal sent to the device from the processor after receiving an interrupt is
A) end signal B) interrupt signal C) Interrupt-acknowledge D) Permission signal
15) When the process is returned after an interrupt service ______ should be loaded again.
A) Register contents B) Condition codes C) PC contents D) all of the above
16) A single Interrupt line can be used to service n different devices. This sentence is
A) True B) False C) There is no interrupt line D) no one can know
17) When dealing with multiple devices interrupts, ____ may be the best method
A) Vectored interrupts B) Interrupt nesting C) daisy chain interrupt D) no one can know
18) Daisy chaining interrupt problem(s) is/are
A) the priority of each unit cannot be changed B) if a device is blocked, all subsequent devices cannot
access the CPU bus
C) high-priority device can lock a low-priority device D) All of above
19) ____ are used to synchronize the I/O devices with the microprocessor
A) Handshaking signals B) control signals C) buffers D) latches

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20) In Harvard memory architecture,
A) separate address, data, and control buses for each memory B) Data and instructions have different
space memories
C) instruction and data fetches can occur concurrently D) all of the above
21) The interrupt vector is the
A) address at which an interrupt service routine lies B) signals that CPU returns when interrupt is applied
C) interrupt handler D) memory used while the execution of the interrupt
22) The _____ determines the cause of the interrupt, performs the necessary processing and
executes a return from the interrupt instruction to return the CPU to the execution state prior to
the interrupt.
A) interrupt request line B) device driver C) interrupt handler D) all of the mentioned
23) The DMA transfer is initiated by _____
A) Processor B) The process being executed C) I/O devices D) OS
24) When a process requests for a DMA transfer,
A) Then the process is temporarily suspended B) The process continues execution
C) process is temporarily suspended & Another process gets executed D) Another process gets executed
25) The technique where the controller is given complete access to main memory is __________
A) Cycle stealing B) Memory stealing C) Memory Con D) Burst mode
26) A single DMA controller can perform operations on ______disk/s simultaneously?
A) only one B) only two C) multiple (limited number) D) no one can know
27) The DMA differs from the interrupt mode by __________
A) The method of accessing the I/O devices B) The amount of data transfer possible
C) The involvement of the processor for the operation D) None of the mentioned

28) Bit stiffing is used in NRZI encoding when

A) long series of zeros are transmitted B) short series of zeros are transmitted
C) no data is transmitted for a long time D) None of the above
29) SPI and I2C are
A) specialized protocols of parallel interfacing B) encoding techniques
C) analog to digital converting modules D) None of the above
30) CRC is
A) a shake-handing signal B) an error detecting method
C) a sending and receiving technique D) an interrupt handler method
31) The ______responsible of issue error messages for an I/O peripheral
A) CPU B) I/O controller C) I/O bus D) CPU and the I/O
controller
32) The ISA bus is _________ than the PCI bus.
A) slower B) faster C) wider D) easier in installation
33) The PCI and ISA BUS are used as
A) extension for the memory BUS B) replacement of the I/O peripherals
C) extension for the processor BUS D) all of the above
34) When the USB is connected to a system, its root hub is connected to the ________
A) PCI bus B) ISA bus C) CPU bus D) Any of the
mentioned

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35) ______ gives the PCI its plug and plays capability.
A) Configuration B) Multiple I/O C) Bus width D) PCI interface
address space types
36) ______making the PCI bus independent of processor type and architecture
A) PCI switch B) PCI memory C) PCI Bridge D) PCI interface
37) Command to PCI peripheral appears on the ____ pins
A) Frame B) C/BE C) address D) data
38) ________ is an extension of the processor BUS
A) USB B) PCI bus C) bridge D) none of the
above
39) The bus parameters may include
A) bus width B) transfer C) synchronization D) all of the above
width type
40) I/O and Peripheral busses (such as PCI, ISA, USB, … etc) are
A) Longer, slower, & narrower B) Short, fast, & wide
C) fixed topology, designed as a D) connected directly to the CPU
“chipset”
41) AGP is connected to the CPU bus
A) through the south B) through a C) directly D) PCI
bridge bridge
42) The bus used to connect the monitor to the CPU is ______
A) PCI bus B) AGP bus C) Memory bus D) CPU internal
bus

Q2. [5 points] What are steps of reading multiple bytes in SPI? Indicate
your answer with drawing timing diagram?
Q3. [5 points] Compare CISC and RISC computers from the following
point of view: instruction time, memory, and compiler. Show an example
of each of them.
Q4. [5 points] Compare SPI and I2C. Draw a diagram for each one
showing the main connections.
Q5. [5 points] If the following raw data are sent on the USB, draw the
waveform of the signal found on the USB: (1100110000110011011010).

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