NATIONAL UNIVERSITY OF HO CHI MINH CITY

UNIVERSITY OF INFORMATION TECHNOLOGY

FACULTY OF COMPUTER ENGINEERING

CHAPTER 2: VERILOG LANGUAGE CONCEPTS

Ho Ngoc Diem

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Content
 Hierarchical structure
 Modules
 Instances
 Lexical convention
 Verilog data types

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 Hierarchical structure
 Modules to be embedded within other modules.
 Higher level modules create instances of lower level modules
and communicate with them through input, output, and
bidirectional ports.
 Module input/output (I/O) ports can be scalar or vector.

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Hierarchical structure
 Top-down design methodology
Top-level block

identify
enough
to build

Cannot further be divided

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Hierarchical structure
 Bottom-up design methodology
Top-level block, the
final block in design

build

Building blocks that are

available is identified
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Hierarchical structure
Example: 4-bit Ripple Carry Counter

Ripple Carry Counter T-flipflop

Design Hierarchy 7
 Module
 A module is the basic building block in Verilog
- Can be an element or a collection of lower-level design blocks
- Provide functionality for higher-level block through its port
interface
- Hide internal implementation
- Is used at many places in the design
- Allows designers modify module internals without effecting the
rest of design

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 Module
Example: 4-bit Ripple Carry Counter

Ripple Carry Counter Module T-flipflop

Module

Module

Design Hierarchy 9
Module
 Typical Module Components Diagram
Module name, Port list (optional, if there are ports)

Port declaration

Data type declaration (wires, reg, integer etc.)

Instantiation of inner (lower-level) modules

Structural statements (i.e., assign and gates)

Procedural blocks (i.e., always and initial blocks)

Tasks and functions

endmodule declaration
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Module
 Module description

module module name ( port name, port name,…);

module_port declaration
module
data type declaration
logic description part
A part of a chip, or
endmodule the whole chip

A module definition

The file name for RTL source must be

“module name.v”

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 Module
 Module port declaration
module module name ( port name, port name,…);
module_port declaration Declare whether the ports are input and/or output
input <port_size> port name, port name, …;
output <port_size> port name, port name, …;
inout <port_size> port name, port name, …;

module
module data_conv ( a, b, …);
4 4
input [3:0] a; a e
input [7:0] b;
8
b
A part of a chip, 4
1 or whole the f 16
output [3:0] e, f; c g
1 chip
output [15:0] g; d
inout c, d;

ports 12
 Module
 Data type declaration
module module name ( port name, port name,…);
module_port declaration
Data type declaration Declare characteristics of variables
for net data type
wire <size> variable name, variable name, …;
wire <size> variable name, variable name, …;

module
wire [3:0] a;
4 q1 4
wire [7:0] b; a q3 e
8 SEL 4
wire c, d; b f
1 16
wire [3:0] f; c g
1 q2 sel3
wire [7:0] q1, q2, q3, q4; d
wire sel3, …;
…. 13
 Module
 Logic description part
module module name ( port name, port name,…);
module_port declaration
Data type declaration
Logic description part The main part of logic
is written here. module
endmodule
4 4
a e
8 4
b f
1 16
c g
1
Logic is coded in this part using various d
operator including connections to lower
level blocks.

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 Instance
Example: 4-bit Ripple Carry Counter

Ripple Carry Counter T-flipflop module

module
Module Module

Instanc Instanc Instanc Instanc Instanc Instanc

e1 D_FF e1 e1 T_FF e2 T_FF e3 T_FF e4 T_FF
Inverter

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 Instances
Example: 4-bit Ripple Carry Counter
module ripple_carry_counter(q, clk, reset);
output [3:0] q; // module D_FF with synchronous reset
input clk, reset; module D_FF(q, d, clk, reset);
//4 instances of the module T_FF are created. output q;
T_FF tff0(q[0],clk, reset); input d, clk, reset;
T_FF tff1(q[1],q[0], reset); reg q;
T_FF tff2(q[2],q[1], reset); // Lots of new constructs. Ignore the
T_FF tff3(q[3],q[2], reset); //functionality of the
endmodule // constructs.
// Concentrate on how the design block is
module T_FF(q, clk, reset); //built in a top-down fashion.
output q; always @(posedge reset or negedge clk)
input clk, reset; if (reset)
wire d; q <= 1'b0;
D_FF dff0(q, d, clk, reset); else
not n1(d, q); // not is a Verilog-provided primitive. q <= d;
endmodule endmodule
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 Instance
 Connecting module instance port by ordered list
The port expressions listed for the module instance shall be in the
same order as the ports listed in the module declaration.
module topmod;
wire [4:0] v;
wire a,b,c,w;
modB b1 (v[0], v[3], w, v[4]);
endmodule

module modB (wa, wb, c, d);

inout wa, wb;
input c, d;
tranif1 g1 (wa, wb, cinvert);
not #(2, 6) n1 (cinvert, int);
and #(6, 5) g2 (int, c, d);
endmodule
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 Instance
 Connecting module instance port by name
Connections are made by name, the order in which they appear is
irrelevant.
module topmod;
wire [4:0] v;
wire a,b,c,w;
modB b1 (.wb(v[3]),.wa(v[0]),.d(v[4]),.c(w));
endmodule

module modB(wa, wb, c, d);

inout wa, wb;
input c, d;
tranif1 g1(wa, wb, cinvert);
not #(6, 2) n1(cinvert, int);
and #(5, 6) g2(int, c, d);
endmodule
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Content
 Hierarchical structure
 Modules
 Instances
 Lexical convention
 Verilog data types

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 Lexical convention
 Verilog is a case-sensitive language.
 Whitespace: \b blank, \t tab, \n new line
 Comment: /*..*/ or //……..
 Operator: unary, binary, ternary (more detail in chapter 5)
a = ~ b; // ~ is a unary operator. b is the operand
a = b && c; // && is a binary operator. b and c are operands
a = b ? c : d; // ?: is a ternary operator. b, c and d are operands

 Keywords: module, end module, inout, reg…

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Lexical convention
 Number
- Two forms to express numbers:
* 37 : 32 bit decimal 37, or
* <size>’<base_format><number>
Ex:
10’hFA 10 bits hexadecimal number FA (00_1111_1010)
1’b0 1 bit binary number 0 (0)
6’d30 6 bits decimal number (011110), decimal 30
15’o10752 15 bits octal number (001,000,111,101,010),
decimal 4586
4’b0 is equal to 4’b0000
4’b1 is equal to 4’b0001
4’bz is equal to 4’bzzzz
4’bx is equal to 4’bxxxx
-8 ’d 6 The two’s complement of 6, held in 8 bits

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 Lexical convention
 Strings are stored as a sequence of 8 bit ASCII values
 Strings are variables of reg type

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Lexical convention
Keyword
 Keywords are used to define the language constructs. There are a
lot of keywords in Verilog HDL. (Refer to Verilog books)
 All keywords are defined in lower case
 Do not use keywords as user’s definition.
Examples:
module, endmodule fork, join
input, output, inout specific, endspecific
reg, integer, real, time timescale
not, and, nand, or, nor, xor include
parameter undef
begin, end nmos, pmos,…
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 Lexical convention
System task & function
 Standard system tasks for certain routine operations
 Appear in form: $<keyword>
 Introduce most useful system tasks, more are listed in
IEEE specification
 Functions: Displaying on screen, monitor values on net…
 $display, $monitor, $stop, $finish

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 Lexical convention
Compiler directive
 `define: define text macro in Verilog (similar to #define in
C)

 `include: include content of a Verilog source file in another

Verilog file
 `ifdef, `timescale
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Data types
 Value set: Four basic values:
0 – represents a logic zero, logic low, ground or false condition.
1 – represents a logic one, logic high, power or true condition.
x – represents an unknown logic value.
z – represents a high-impedance, unconnected, tri-state.

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Data types
 2 main groups: Net and Variable
 The net data types represent physical connections between structural
entities, such as gates.
 Net: does not store a value, except “trireg” net
 Default value is z (trireg default value is x)
 Net types:

(Ref. Verilog IEEE book for detail of net types)

Ex:
- wire w1, w2; // declare 2 wires
- wand w;

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Data types
 Net
- Nets present the physical connections between devices. A net
does not store a value, it must be driven by a gate or a
continuous assignment. If a net variable has no driver, then it
has a high-impedance value (z).
- Verilog automatically propagates new values onto a net when
the drivers change value.
- Cannot be assigned in an initial or always block

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Data types
 Variable: hold a value until another value assigned to it
- Used in behavioral description (procedural assignment)
reg : unsigned integer variables of varying bit width
integer : 32-bit signed integer
time : 64-bit unsigned integer
real : signed floating-point
realtime: store time as a real value
- reg, time, integer (default value is x),
real , realtime (default value is 0)

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 Data types
 Vector: Multiple net or reg data types are declared by
specifying a range, is known as a vector

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 Data types
 Array declaration for a net or variable that is either scalar
or vector

 Memory: is one-dimension array with element of type reg.

These memories can be used to model ROM, RAM, or reg
files

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Data types
 Parameters do not belong to net or variable. Parameters
are constants
 2 types: module parameter (defparam) and
specify parameter (specparam)

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 Data types in Module
 Correct data types for ports

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 Module port rules Outside connectors
to internal ports, i.e.,
 Port rules diagram variables corresponding
to ports in instantiation
EXTERNAL
of internal module
MODULE wire
Example:
module external
reg a; wire inout
wire b;
internal in(a, b); //instantiation
… Internal ports
endmodule input
connector

output
module internal(x, y) reg or wire wire wire
port-

INTERNAL reg or wire

input x;
MODULE
output y;
wire x;
reg y;
…
endmodule General rule (with few exceptions) Ports in all modules except for the
stimulus module should be wire. Stimulus module has registers to set data for
internal modules and wire ports only to read data from internal modules. 34
 Module port rules
 Mistakes and correct on register and net data type
module1 module2
reg
reg wire wire wire reg wire wire

reg module2_1
reg
reg reg
wire wire
reg wire wire
reg

The output of memory element They must be defined as wire at

must be defined as reg these points.

: memory element 35
 Module port rules
 Mistakes and correct on register and net data type
module1 module2

reg reg reg wire wire wire reg reg reg

wire reg module2_1

wire reg
wire wire
reg reg reg wire
wire
wire wire

wire Assume gates are not defined by using

wire reg always nor function statements
wire
wire
wire Suppose this part is programmed
by using always statement.
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 Module port rules
 Mistakes and correct on register and net data type
Note: reg data type cannot be declared as an input !!!
module1 module2
wire wire wire wire
reg reg reg wire wire wire reg reg reg

wire reg module2_1 wire

wire reg
reg
wire wire wire wire
reg reg reg wire
wire reg
wire wire

wire Explain later

reg reg
wire
reg wire
wire
wire Suppose this part is programmed
by using always statement. 37
 Verilog model for hardware design
Verilog design
RTL Design

Gate/Switch level modeling Dataflow modeling Behavioral modeling

- Primitive switch, gate - Continuous assignment - Procedural assignment

- User defined primitive - Expression (operators) - initial, always block
- Conditional statement…

 There are different ways of modeling a hardware design. Choose an

appropriate model to design Combinational or Sequential Circuit.
 Some books do not classify Dataflow modeling is a separate modeling type,
but belongs to Behavioral modeling.

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