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Intel® Virtualization Technology for
Directed I/O
Architecture Specification

June 2016

Order Number: D51397-008, Rev. 2.4

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*Other names and brands may be claimed as the property of others.

Intel® Virtualization Technology for Directed I/O

Architecture Specification, Rev. 2.4 June 2016
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Contents—Intel® Virtualization Technology for Directed I/O

Contents

1 Introduction
1.1 Audience ........................................................................................................ 1-1
1.2 Glossary ........................................................................................................ 1-2
1.3 References ..................................................................................................... 1-3
2 Overview
2.1 Intel® Virtualization Technology Overview .......................................................... 2-1
2.2 VMM and Virtual Machines ................................................................................ 2-1
2.3 Hardware Support for Processor Virtualization ..................................................... 2-1
2.4 I/O Virtualization............................................................................................. 2-2
2.5 Intel® Virtualization Technology For Directed I/O Overview ................................... 2-2
2.5.1 Hardware Support for DMA Remapping..................................................... 2-3
2.5.1.1 OS Usages of DMA Remapping................................................... 2-3
2.5.1.2 VMM Usages of DMA Remapping ................................................ 2-4
2.5.1.3 DMA Remapping Usages by Guests............................................. 2-4
2.5.1.4 Interaction with Processor Virtualization...................................... 2-5
2.5.2 Hardware Support for Interrupt Remapping .............................................. 2-6
2.5.2.1 Interrupt Isolation.................................................................... 2-6
2.5.2.2 Interrupt Migration................................................................... 2-6
2.5.2.3 x2APIC Support ....................................................................... 2-6
2.5.3 Hardware Support for Interrupt Posting .................................................... 2-7
2.5.3.1 Interrupt Vector Scalability........................................................ 2-7
2.5.3.2 Interrupt Virtualization Efficiency ............................................... 2-7
2.5.3.3 Virtual Interrupt Migration......................................................... 2-7
3 DMA Remapping
3.1 Types of DMA requests..................................................................................... 3-1
3.2 Domains and Address Translation ...................................................................... 3-1
3.3 Remapping Hardware - Software View................................................................ 3-2
3.4 Mapping Devices to Domains ............................................................................ 3-2
3.4.1 Source Identifier ................................................................................... 3-3
3.4.2 Root-Entry & Extended-Root-Entry .......................................................... 3-3
3.4.3 Context-Entry ....................................................................................... 3-4
3.4.4 Extended-Context-Entry ......................................................................... 3-5
3.5 Hierarchical Translation Structures..................................................................... 3-7
3.6 First-Level Translation...................................................................................... 3-9
3.6.1 Translation Faults ................................................................................ 3-11
3.6.2 Access Rights ..................................................................................... 3-11
3.6.3 Accessed, Extended Accessed, and Dirty Flags ........................................ 3-12
3.6.4 Snoop Behavior................................................................................... 3-13
3.6.5 Memory Typing ................................................................................... 3-13
3.6.5.1 Selecting Memory Type from Page Attribute Table ...................... 3-14
3.6.5.2 Selecting Memory Type from Memory Type Range Registers ........ 3-14
3.6.5.3 Selecting Effective Memory Type.............................................. 3-15
3.7 Second-Level Translation................................................................................ 3-16
3.7.1 Translation Faults ................................................................................ 3-19
3.7.2 Access Rights ..................................................................................... 3-19
3.7.3 Snoop Behavior................................................................................... 3-20
3.7.4 Memory Typing ................................................................................... 3-20
3.8 Nested Translation ........................................................................................ 3-21
3.8.1 Translation Faults ................................................................................ 3-22
3.8.2 Access Rights ..................................................................................... 3-22
3.8.3 Snoop Behavior................................................................................... 3-23
3.8.4 Memory Typing ................................................................................... 3-24

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 Intel® Virtualization Technology for Directed I/O—Contents

3.9 Identifying Origination of DMA Requests ........................................................... 3-25

3.9.1 Devices Behind PCI-Express to PCI/PCI-X Bridges ....................................3-25
3.9.2 Devices Behind Conventional PCI Bridges ................................................3-25
3.9.3 Root-Complex Integrated Devices ..........................................................3-25
3.9.4 PCI-Express Devices Using Phantom Functions.........................................3-25
3.10 Handling Requests from Processor Graphics Device ............................................ 3-26
3.11 Handling Requests Crossing Page Boundaries .................................................... 3-26
3.12 Handling of Zero-Length Reads........................................................................ 3-26
3.13 Handling Requests to Interrupt Address Range .................................................. 3-27
3.14 Handling Requests to Reserved System Memory ................................................ 3-27
3.15 Root-Complex Peer to Peer Considerations ........................................................ 3-28
4 Support For Device-TLBs
4.1 Device-TLB Operation...................................................................................... 4-1
4.1.1 Translation Request .............................................................................. 4-2
4.1.2 Translation Completion .......................................................................... 4-2
4.1.3 Translated Request ............................................................................... 4-3
4.1.4 Invalidation Request & Completion .......................................................... 4-3
4.2 Remapping Hardware Handling of Device-TLBs ................................................... 4-4
4.2.1 Handling of ATS Protocol Errors .............................................................. 4-4
4.2.2 Root-Port Control of ATS Address Types................................................... 4-4
4.2.3 Handling of Translation Requests ............................................................ 4-4
4.2.3.1 Accessed, Extended Accessed, and Dirty Flags ............................ 4-8
4.2.3.2 Translation Requests for Multiple Translations ............................. 4-9
4.2.4 Handling of Translated Requests ............................................................. 4-9
4.3 Handling of Device-TLB Invalidations ................................................................ 4-10
5 Interrupt Remapping and Interrupt Posting
5.1 Interrupt Remapping ....................................................................................... 5-1
5.1.1 Identifying Origination of Interrupt Requests ............................................ 5-1
5.1.2 Interrupt Request Formats On Intel® 64 Platforms ................................... 5-2
5.1.2.1 Interrupt Requests in Compatibility Format ................................. 5-2
5.1.2.2 Interrupt Requests in Remappable Format .................................. 5-3
5.1.3 Interrupt Remapping Table .................................................................... 5-4
5.1.4 Interrupt-Remapping Hardware Operation................................................ 5-4
5.1.4.1 Interrupt Remapping Fault Conditions ........................................ 5-6
5.1.5 Programming Interrupt Sources To Generate Remappable Interrupts ........... 5-6
5.1.5.1 I/OxAPIC Programming ............................................................ 5-7
5.1.5.2 MSI and MSI-X Register Programming........................................ 5-8
5.1.6 Remapping Hardware - Interrupt Programming......................................... 5-9
5.1.7 Programming in Intel® 64 xAPIC Mode .................................................... 5-9
5.1.8 Programming in Intel® 64 x2APIC Mode..................................................5-10
5.1.9 Handling of Platform Events ..................................................................5-10
5.2 Interrupt Posting ........................................................................................... 5-11
5.2.1 Interrupt Remapping Table Support for Interrupt Posting ..........................5-11
5.2.2 Posted Interrupt Descriptor ...................................................................5-12
5.2.3 Interrupt-Posting Hardware Operation ....................................................5-12
5.2.4 Ordering Requirements for Interrupt Posting ...........................................5-13
5.2.5 Using Interrupt Posting for Virtual Interrupt Delivery ................................5-13
5.2.6 Interrupt Posting for Level Triggered Interrupts .......................................5-15
6 Caching Translation Information
6.1 Caching Mode................................................................................................. 6-1
6.2 Address Translation Caches.............................................................................. 6-1
6.2.1 Tagging of Cached Translations .............................................................. 6-2
6.2.2 Context-cache ...................................................................................... 6-2

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6.2.2.1 Context-Entry Programming Considerations................................. 6-4

6.2.3 PASID-cache ........................................................................................ 6-4
6.2.4 IOTLB .................................................................................................. 6-5
6.2.4.1 Details of IOTLB Use ................................................................ 6-6
6.2.4.2 Global Pages ........................................................................... 6-7
6.2.5 Caches for Paging Structures .................................................................. 6-7
6.2.5.1 PML4-cache ............................................................................ 6-8
6.2.5.2 PDPE-cache............................................................................. 6-9
6.2.5.3 PDE-cache ............................................................................ 6-11
6.2.5.4 Details of Paging-Structure Cache Use ...................................... 6-12
6.2.6 Using the Paging-Structure Caches to Translate Requests ......................... 6-13
6.2.7 Multiple Cached Entries for a Single Paging-Structure Entry....................... 6-14
6.3 Translation Caching at Endpoint Device ............................................................ 6-15
6.4 Interrupt Entry Cache .................................................................................... 6-15
6.5 Invalidation of Translation Caches ................................................................... 6-15
6.5.1 Register-based Invalidation Interface ..................................................... 6-16
6.5.1.1 Context Command Register ..................................................... 6-16
6.5.1.2 IOTLB Registers..................................................................... 6-16
6.5.2 Queued Invalidation Interface ............................................................... 6-17
6.5.2.1 Context-cache Invalidate Descriptor ......................................... 6-19
6.5.2.2 PASID-cache Invalidate Descriptor ........................................... 6-20
6.5.2.3 IOTLB Invalidate Descriptor..................................................... 6-21
6.5.2.4 Extended IOTLB Invalidate Descriptor....................................... 6-22
6.5.2.5 Device-TLB Invalidate Descriptor ............................................. 6-24
6.5.2.6 Extended Device-TLB Invalidate Descriptor................................ 6-25
6.5.2.7 Interrupt Entry Cache Invalidate Descriptor ............................... 6-26
6.5.2.8 Invalidation Wait Descriptor .................................................... 6-27
6.5.2.9 Hardware Generation of Invalidation Completion Events.............. 6-27
6.5.2.10 Hardware Handling of Queued Invalidation Interface Errors ......... 6-28
6.5.2.11 Queued Invalidation Ordering Considerations............................. 6-29
6.5.3 IOTLB Invalidation Considerations ......................................................... 6-29
6.5.3.1 Implicit Invalidation on Page Requests ...................................... 6-29
6.5.3.2 Caching Fractured Translations ................................................ 6-30
6.5.3.3 Recommended Invalidation ..................................................... 6-30
6.5.3.4 Optional Invalidation .............................................................. 6-31
6.5.3.5 Delayed Invalidation .............................................................. 6-32
6.5.4 TLB Shootdown Optimization for Root-Complex Integrated Devices ............ 6-32
6.5.4.1 Deferred Invalidation.............................................................. 6-33
6.5.4.2 PASID-State Table ................................................................. 6-34
6.5.4.3 Remapping Hardware Handling of PASID State-Update Requests .. 6-35
6.5.4.4 Root-Complex Integrated Device Handling of PASID State-Update
Responses ............................................................................ 6-35
6.5.4.5 Ordering of PASID State-Update Requests and Responses ........... 6-36
6.5.4.6 Example TLB Shootdown using Deferred Invalidations................. 6-36
6.5.5 Draining of Requests to Memory............................................................ 6-36
6.5.6 Interrupt Draining ............................................................................... 6-37
6.6 Set Root Table Pointer Operation ..................................................................... 6-38
6.7 Set Interrupt Remapping Table Pointer Operation .............................................. 6-38
6.8 Write Buffer Flushing ..................................................................................... 6-39
6.9 Hardware Register Programming Considerations ................................................ 6-39
6.10 Sharing Remapping Structures Across Hardware Units........................................ 6-39
7 Translation Faults
7.1 Interrupt Translation Faults .............................................................................. 7-1
7.2 Address Translation Faults ................................................................................ 7-1
7.2.1 Non-Recoverable Address Translation Faults ............................................. 7-2
7.2.1.1 Non-Recoverable Faults for Untranslated Requests Without PASID .. 7-2

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 Intel® Virtualization Technology for Directed I/O—Contents

7.2.1.2 Non-Recoverable Faults for Untranslated Requests With PASID...... 7-3

7.2.1.3 Non-Recoverable Faults for Translation Requests Without PASID.... 7-6
7.2.1.4 Non-Recoverable Faults for Translation Requests With PASID ........ 7-6
7.2.1.5 Non-Recoverable Faults for Translated Requests.......................... 7-8
7.2.2 Recoverable Address Translation Faults ................................................... 7-9
7.3 Non-Recoverable Fault Reporting ..................................................................... 7-10
7.3.1 Primary Fault Logging...........................................................................7-11
7.3.2 Advanced Fault Logging ........................................................................7-11
7.4 Non-Recoverable Fault Event........................................................................... 7-12
7.5 Recoverable Fault Reporting ............................................................................ 7-13
7.5.1 Handling of Page Requests ....................................................................7-13
7.5.1.1 Page Request Descriptor .........................................................7-15
7.6 Recoverable Fault Event ................................................................................. 7-17
7.7 Servicing Recoverable Faults ........................................................................... 7-18
7.7.1 Page Group Response Descriptor ...........................................................7-19
7.7.2 Page Stream Response Descriptor..........................................................7-20
7.8 Page Request Ordering and Draining ................................................................ 7-21
7.9 Page Response Ordering and Draining .............................................................. 7-21
7.10 Pending Page Request Handling on Terminal Conditions ...................................... 7-22
7.11 Software Steps to Drain Page Requests & Responses .......................................... 7-22
7.12 Revoking PASIDs with Pending Page Faults ....................................................... 7-23
8 BIOS Considerations
8.1 DMA Remapping Reporting Structure................................................................. 8-1
8.2 Remapping Structure Types ............................................................................. 8-2
8.3 DMA Remapping Hardware Unit Definition Structure ............................................ 8-3
8.3.1 Device Scope Structure ......................................................................... 8-4
8.3.1.1 Reporting Scope for I/OxAPICs.................................................. 8-6
8.3.1.2 Reporting Scope for MSI Capable HPET Timer Block ..................... 8-6
8.3.1.3 Reporting Scope for ACPI Name-space Devices............................ 8-6
8.3.1.4 Device Scope Example ............................................................. 8-6
8.3.2 Implications for ARI .............................................................................. 8-8
8.3.3 Implications for SR-IOV ......................................................................... 8-8
8.3.4 Implications for PCI/PCI-Express Hot Plug ................................................ 8-8
8.3.5 Implications with PCI Resource Rebalancing ............................................. 8-8
8.3.6 Implications with Provisioning PCI BAR Resources ..................................... 8-8
8.4 Reserved Memory Region Reporting Structure .................................................... 8-9
8.5 Root Port ATS Capability Reporting Structure..................................................... 8-10
8.6 Remapping Hardware Static Affinity Structure.................................................... 8-11
8.7 ACPI Name-space Device Declaration Structure ................................................. 8-12
8.8 Remapping Hardware Unit Hot Plug .................................................................. 8-12
8.8.1 ACPI Name Space Mapping ...................................................................8-12
8.8.2 ACPI Sample Code ...............................................................................8-13
8.8.3 Example Remapping Hardware Reporting Sequence..................................8-14
9 Translation Structure Formats
9.1 Root Entry ..................................................................................................... 9-1
9.2 Extended Root Entry ....................................................................................... 9-3
9.3 Context Entry................................................................................................. 9-5
9.4 Extended-Context-Entry .................................................................................. 9-8
9.5 PASID Entry.................................................................................................. 9-15
9.6 PASID-State Entry ......................................................................................... 9-17
9.7 First-Level Paging Entries................................................................................ 9-18
9.8 Second-Level Paging Entries............................................................................ 9-25
9.9 Fault Record ................................................................................................. 9-32
9.10 Interrupt Remapping Table Entry (IRTE) for Remapped Interrupts ........................ 9-34

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9.11 Interrupt Remapping Table Entry (IRTE) for Posted Interrupts ............................. 9-39
9.12 Posted Interrupt Descriptor (PID) .................................................................... 9-42
10 Register Descriptions
10.1 Register Location........................................................................................... 10-1
10.2 Software Access to Registers .......................................................................... 10-1
10.3 Register Attributes ........................................................................................ 10-2
10.4 Register Descriptions ..................................................................................... 10-3
10.4.1 Version Register.................................................................................. 10-7
10.4.2 Capability Register .............................................................................. 10-8
10.4.3 Extended Capability Register............................................................... 10-13
10.4.4 Global Command Register .................................................................. 10-17
10.4.5 Global Status Register........................................................................ 10-22
10.4.6 Root Table Address Register ............................................................... 10-24
10.4.7 Context Command Register ................................................................ 10-25
10.4.8 IOTLB Registers ................................................................................ 10-28
10.4.8.1 IOTLB Invalidate Register ..................................................... 10-29
10.4.8.2 Invalidate Address Register ................................................... 10-32
10.4.9 Fault Status Register ......................................................................... 10-34
10.4.10Fault Event Control Register ............................................................... 10-36
10.4.11Fault Event Data Register ................................................................... 10-38
10.4.12Fault Event Address Register .............................................................. 10-39
10.4.13Fault Event Upper Address Register ..................................................... 10-40
10.4.14Fault Recording Registers [n] .............................................................. 10-41
10.4.15Advanced Fault Log Register ............................................................... 10-44
10.4.16Protected Memory Enable Register....................................................... 10-45
10.4.17Protected Low-Memory Base Register................................................... 10-47
10.4.18Protected Low-Memory Limit Register .................................................. 10-48
10.4.19Protected High-Memory Base Register .................................................. 10-49
10.4.20Protected High-Memory Limit Register.................................................. 10-50
10.4.21Invalidation Queue Head Register ........................................................ 10-51
10.4.22Invalidation Queue Tail Register .......................................................... 10-52
10.4.23Invalidation Queue Address Register .................................................... 10-53
10.4.24Invalidation Completion Status Register ............................................... 10-54
10.4.25Invalidation Event Control Register ...................................................... 10-55
10.4.26Invalidation Event Data Register ......................................................... 10-56
10.4.27Invalidation Event Address Register ..................................................... 10-57
10.4.28Invalidation Event Upper Address Register ............................................ 10-58
10.4.29Interrupt Remapping Table Address Register......................................... 10-59
10.4.30Page Request Queue Head Register ..................................................... 10-60
10.4.31Page Request Queue Tail Register........................................................ 10-61
10.4.32Page Request Queue Address Register ................................................. 10-62
10.4.33Page Request Status Register ............................................................. 10-63
10.4.34Page Request Event Control Register ................................................... 10-64
10.4.35Page Request Event Data Register ....................................................... 10-65
10.4.36Page Request Event Address Register................................................... 10-66
10.4.37Page Request Event Upper Address Register ......................................... 10-67
10.4.38MTRR Capability Register.................................................................... 10-68
10.4.39MTRR Default Type Register................................................................ 10-69
10.4.40Fixed-Range MTRRs ........................................................................... 10-70
10.4.41Variable-Range MTRRs ....................................................................... 10-72
A Non-Recoverable Fault Reason Encodings ................................................................. 1

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Figures
Figure 1-1. General Platform Topology ......................................................................... 1-1
Figure 2-2. Example OS Usage of DMA Remapping ........................................................ 2-3
Figure 2-3. Example Virtualization Usage of DMA Remapping .......................................... 2-4
Figure 2-4. Interaction Between I/O and Processor Virtualization ..................................... 2-5
Figure 3-5. DMA Address Translation ........................................................................... 3-2
Figure 3-6. Requester Identifier Format........................................................................ 3-3
Figure 3-7. Device to Domain Mapping Structures using Root-Table ................................. 3-4
Figure 3-8. Device to Domain Mapping Structures using Extended-Root-Table ................... 3-6
Figure 3-9. Address Translation to a 4-KByte Page......................................................... 3-7
Figure 3-10. Address Translation to a 2-MByte Large Page................................................ 3-8
Figure 3-11. Address Translation to a 1-GByte Large Page ................................................ 3-8
Figure 3-12. Nested Translation with 4-KByte pages .......................................................3-21
Figure 4-13. Device-TLB Operation ................................................................................ 4-1
Figure 5-14. Compatibility Format Interrupt Request........................................................ 5-2
Figure 5-15. Remappable Format Interrupt Request......................................................... 5-3
Figure 5-16. I/OxAPIC RTE Programming ....................................................................... 5-7
Figure 5-17. MSI-X Programming .................................................................................. 5-8
Figure 5-18. Remapping Hardware Interrupt Programming in Intel® 64 xAPIC Mode............ 5-9
Figure 5-19. Remapping Hardware Interrupt Programming in Intel® 64 x2APIC Mode .........5-10
Figure 6-20. Context-cache Invalidate Descriptor ...........................................................6-19
Figure 6-21. PASID-cache Invalidate Descriptor .............................................................6-20
Figure 6-22. IOTLB Invalidate Descriptor.......................................................................6-21
Figure 6-23. Extended IOTLB Invalidate Descriptor .........................................................6-22
Figure 6-24. Device-TLB Invalidate Descriptor................................................................6-24
Figure 6-25. Extended Device-TLB Invalidate Descriptor ..................................................6-25
Figure 6-26. Interrupt Entry Cache Invalidate Descriptor .................................................6-26
Figure 6-27. Invalidation Wait Descriptor ......................................................................6-27
Figure 7-28. Page Request Descriptor ...........................................................................7-15
Figure 7-29. Page Group Response Descriptor................................................................7-19
Figure 7-30. Page Stream Response Descriptor ..............................................................7-20
Figure 8-31. Hypothetical Platform Configuration............................................................. 8-7
Figure 9-32. Root-Entry Format .................................................................................... 9-1
Figure 9-33. Extended-Root-Entry Format ...................................................................... 9-3
Figure 9-34. Context-Entry Format ................................................................................ 9-5
Figure 9-35. Extended-Context-Entry Format.................................................................. 9-8
Figure 9-36. PASID Entry Format .................................................................................9-15
Figure 9-37. PASID-State Entry Format.........................................................................9-17
Figure 9-38. Format for First-Level Paging Entries ..........................................................9-18
Figure 9-39. Format for Second-Level Paging Entries ......................................................9-25
Figure 9-40. Fault-Record Format.................................................................................9-32
Figure 9-41. Interrupt Remap Table Entry Format for Remapped Interrupts .......................9-34
Figure 9-42. Interrupt Remap Table Entry Format for Posted Interrupts.............................9-39
Figure 9-43. Posted Interrupt Descriptor Format ............................................................9-42
Figure 10-44. Version Register ......................................................................................10-7
Figure 10-45. Capability Register ...................................................................................10-8
Figure 10-46. Extended Capability Register ................................................................... 10-13
Figure 10-47. Global Command Register ....................................................................... 10-17
Figure 10-48. Global Status Register ............................................................................ 10-22
Figure 10-49. Root Table Address Register .................................................................... 10-24
Figure 10-50. Context Command Register ..................................................................... 10-25
Figure 10-51. IOTLB Invalidate Register........................................................................ 10-29
Figure 10-52. Invalidate Address Register ..................................................................... 10-32
Figure 10-53. Fault Status Register .............................................................................. 10-34

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Figure 10-54. Fault Event Control Register.................................................................... 10-36

Figure 10-55. Fault Event Data Register ....................................................................... 10-38
Figure 10-56. Fault Event Address Register................................................................... 10-39
Figure 10-57. Fault Event Upper Address Register.......................................................... 10-40
Figure 10-58. Fault Recording Register ......................................................................... 10-41
Figure 10-59. Advanced Fault Log Register ................................................................... 10-44
Figure 10-60. Protected Memory Enable Register ........................................................... 10-45
Figure 10-61. Protected Low-Memory Base Register ....................................................... 10-47
Figure 10-62. Protected Low-Memory Limit Register....................................................... 10-48
Figure 10-63. Protected High-Memory Base Register ...................................................... 10-49
Figure 10-64. Protected High-Memory Limit Register ...................................................... 10-50
Figure 10-65. Invalidation Queue Head Register ............................................................ 10-51
Figure 10-66. Invalidation Queue Tail Register .............................................................. 10-52
Figure 10-67. Invalidation Queue Address Register ........................................................ 10-53
Figure 10-68. Invalidation Completion Status Register.................................................... 10-54
Figure 10-69. Invalidation Event Control Register .......................................................... 10-55
Figure 10-70. Invalidation Event Data Register.............................................................. 10-56
Figure 10-71. Invalidation Event Address Register ......................................................... 10-57
Figure 10-72. Invalidation Event Upper Address Register ................................................ 10-58
Figure 10-73. Interrupt Remapping Table Address Register ............................................. 10-59
Figure 10-74. Page Request Queue Head Register.......................................................... 10-60
Figure 10-75. Page Request Queue Tail Register ............................................................ 10-61
Figure 10-76. Page Request Queue Address Register...................................................... 10-62
Figure 10-77. Page Request Status Register.................................................................. 10-63
Figure 10-78. Page Request Event Control Register........................................................ 10-64
Figure 10-79. Page Request Event Data Register ........................................................... 10-65
Figure 10-80. Page Request Event Address Register ....................................................... 10-66
Figure 10-81. Page Request Event Upper Address Register.............................................. 10-67
Figure 10-82. MTRR Capability Register ........................................................................ 10-68
Figure 10-83. MTRR Default Type Register .................................................................... 10-69
Figure 10-84. Fixed-Range MTRR Format ...................................................................... 10-70
Figure 10-85. Variable-Range MTRR Format .................................................................. 10-72

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Tables
Table 1. Glossary .................................................................................................. 1-2
Table 2. References ............................................................................................... 1-3
Table 3. First-level Paging Structures ....................................................................... 3-9
Table 4. Effective Memory Types ............................................................................3-15
Table 5. Second-level Paging Structures ..................................................................3-17
Table 6. Address Fields in Remappable Interrupt Request Format ................................ 5-3
Table 7. Data Fields in Remappable Interrupt Request Format ..................................... 5-4
Table 8. Interrupt Remapping Fault Conditions .......................................................... 5-6
Table 9. Index Mask Programming..........................................................................6-26
Table 10. Interrupt Remapping Fault Conditions .......................................................... 7-1
Table 11. Non-Recoverable Faults for Untranslated Requests Without PASID ................... 7-2
Table 12. Non-Recoverable Faults for Untranslated Requests With PASID ....................... 7-3
Table 13. Non-Recoverable Faults For Translation Requests Without PASID..................... 7-6
Table 14. Non-Recoverable Faults For Translation Requests With PASID ......................... 7-7
Table 15. Non-Recoverable Faults For Translated Requests ........................................... 7-9
Table 16. Recoverable Fault Conditions For Translation Requests ..................................7-10
Table 17. Response Codes.......................................................................................7-20
Table 18. Format of PML4E that references a Page-Directory-Pointer Table ....................9-19
Table 19. Format of PDPE that maps a 1-GByte Page .................................................9-20
Table 20. Format of PDPE that references a Page-Directory Table .................................9-21
Table 21. Format of PDE that maps a 2-MByte Page ..................................................9-22
Table 22. Format of PDE that references a Page Table.................................................9-23
Table 23. Format of PTE that maps a 4-KByte Page ...................................................9-24
Table 24. Format of SL-PML4E referencing a Second-Level-Page-Directory-Pointer Table .9-26
Table 25. Format of SL-PDPE that maps a 1-GByte Page .............................................9-27
Table 26. Format of SL-PDPE that references a Second-Level-Page-Directory .................9-28
Table 27. Format of SL-PDE that maps to a 2-MByte Page ...........................................9-29
Table 28. Format of SL-PDE that references a Second-Level-Page Table ........................9-30
Table 29. Format of SL-PTE that maps 4-KByte Page ..................................................9-31
Table 30. Address Mapping for Fixed-Range MTRRs .................................................. 10-71

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Revision History

Date Revision Description

March 2006 Draft • Preliminary Draft Specification

May 2007 1.0 • 1.0 Specification
September 2007 1.1 • Specification update for x2APIC support
• Miscellaneous documentation fixes/clarifications, including BIOS support for NUMA, hot-
September 2008 1.2
plug
February 2011 1.3 • Fixed documentation errors; Added BIOS support to report X2APIC_OPT_OUT
• Updated chapter 8 (BIOS requirements) to comprehend platforms with ACPI devices
January 2012 2.0 capable of generating DMA requests (such as Low Power Subsystem (LPSS) on client
platforms).
• Extended page group request with a stream response requested flag to request stream
responses for page requests except the last request in group.
August 2013 2.1 • Added an Blocked-On-Fault field to page requests requesting stream response as a hint
to indicate the respective fault caused a blocking condition on the endpoint device.
• Clarified hardware behavior on page requests received when page request queue is full.
• Added support for Shared Virtual Memory (SVM) capability.
• Fixed ANDD structure definition in DMAR ACPI table to support 2-byte length field.
September 2013 2.2
• Fixed invalidation granularity encoding for extended IOTLB invalidation descriptor.
• Updated bit positions of fields in PASID-State table entry.
• Added support for Interrupt Posting capability support.
• Clarified specific registers whose read completions are required to drain various types of
interrupt requests generated by the remapping hardware.
• Fixed typo in effective memory-type computation for first-level paging entry accesses
when nested translations are enabled with Extended Memory Type disabled in second-
level translation tables.
• Fixed Page Request Status Register and Page Request Event Control Register
descriptions to clarify that queueing of any page_req_desc in the page request queue
results in hardware setting the Pending Page Request (PPR) field.
October 2014 2.3
• Fixed Supervisor Request Enable (SRE) field location from Extended-context-entry to
PASID-entry, to distinguish privileged versus non-privileged PASIDs of a device.
• Fixed Extended Access Flag Enable (EAFE) field location from PASID-entry to Extended-
Context-entry.
• Relaxed context-entry programming considerations to clarify software requirement to
ensure self-consistency when modifying present root, extended-root, context or
extended-context entries.
• Reserved Translation Type (TT) field encoding of 110b and 111b in extended-context-
entries (previously documented incorrectly as PASID-only translation types).
• Fixed location of PASID Support enumeration field in ECAP_REG from bit28 to bit 40.
• Fixed typo in Section 4.2.3 to clarify that for translation-requests-with-PASID with PR=1,
remapping hardware supporting supervisor-requests (SRS=1) return PRIV bit as always
1. Previous versions of the spec. incorrectly specified hardware returning PRIV bit as 1
only if the U/S field is 0 in at least one of the first-level paging-structure entries
controlling the translation.
• Clarified the ordering requirement to be followed by remapping hardware on page
request descriptor writes and recoverable fault reporting event interrupt.
• Updated Chapter 6 to include Device-TLB invalidation throttling support for SR-IOV
devices. New Device-TLB Invalidation Throttling (DIT) capability field added to
June 2016 2.4 ECAP_REG.
• Updated Chapter 6 to include a new Page-request Drain (PD) flag in inv_wait_dsc for
page request draining.
• Updated Chapter 7 to include details on page request and page response ordering and
draining, including handling of terminal conditions on device with pending page faults.
• Added ECAP_REG capability fields to report support for Device-TLB invalidation throttling
and page-request draining.
• Clarified Caching Mode (CM=1) behavior to indicate that the reserved Domain-ID of 0 is
used only for context-cache and rest of the caching structures follow same tagging for
cached entries for CM=0 and CM =1(including for cached faulting entries when CM=1).

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Introduction—Intel® Virtualization Technology for Directed I/O

1 Introduction

This document describes the Intel® Virtualization Technology for Directed I/O (“Intel® VT for Directed
I/O”); specifically, it describes the components supporting I/O virtualization as it applies to platforms
that use Intel® processors and core logic chipsets complying with Intel® platform specifications.

Figure 1-1 illustrates the general platform topology.

P ro c e s s o r P ro c e s s o r

S y s te m B u s

N o rth B rid g e
D M A & In te rru p t R e m a p p in g
DRAM
In te g ra te d
D e v ic e s

P C I E x p re s s S o u th P C I, L P C ,
D e v ic e s B rid g e L e g a c y d e v ic e s

Figure 1-1. General Platform Topology

The document includes the following topics:

• An overview of I/O subsystem hardware functions for virtualization support
• A brief overview of expected usages of the generalized hardware functions
• The theory of operation of hardware, including the programming interface

The following topics are not covered (or are covered in a limited context):
• Intel® Virtualization Technology for Intel® 64 Architecture. For more information, refer to the
“Intel® 64 Architecture Software Developer's Manual, Volume 3B: System Programming Guide”.

1.1 Audience
This document is aimed at hardware designers developing Intel platforms or core-logic providing
hardware support for virtualization. The document is also expected to be used by Operating System
(OS) and Virtual Machine Monitor (VMM) developers utilizing the I/O virtualization hardware
functions.

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1.2 Glossary
The document uses the terms listed in the following table.

Table 1. Glossary

Term Definition

A hardware representation of state that identifies a device and the domain to which the
Context
device is assigned.

Context-
Remapping hardware cache that stores device to domain mappings
cache

Device-TLB A translation cache at the endpoint device (as opposed to in the platform).

DMA Direct Memory Access: Address routed in-bound requests from I/O devices

DMA
The act of translating the address in a DMA request to a host physical address (HPA).
Remapping

A collection of physical, logical, or virtual resources that are allocated to work together.
Domain
Used as a generic term for virtual machines, partitions, etc.

Address in a DMA request: Depending on the software usage and hardware capabilities,
DMA
DMA address can be Guest Physical Address (GPA), Guest Virtual Address (GVA), Virtual
Address
Address (VA), or I/O Virtual Address (IOVA).

First-Level Paging structures used for address translation of DMA requests with Process Address
Paging Space ID (PASID)

Translation caches used by remapping hardware units to cache intermediate (non-leaf)

First-Level
entries of the first-level paging structures. These include PML4 cache, PDP cache, and
Caches
PDE cache.

GAW Guest Address Width: Physical addressability limit within a partition (virtual machine)

Guest Physical Address: the view of physical memory from software running in a
GPA
partition (virtual machine).

Guest Software running within a virtual machine environment (partition).

Guest Virtual Address: Processor virtual address used by software running in a partition
GVA
(virtual machine).

HAW Host Address Width: the DMA physical addressability limit for a platform.

Host Physical Address: Physical address used by hardware to access memory and
HPA
memory-mapped resources.

Interrupt Entry Cache: A translation cache in remapping hardware unit that caches
IEC
frequently used interrupt-remapping table entries.

I/O Translation Lookaside Buffer: an address translation cache in remapping hardware

IOTLB
unit that caches effective translations from DVA (GPA) to HPA.

I/OxAPIC I/O Advanced Programmable Interrupt Controller

IOVA I/O Virtual Address: Virtual address created by software for use in I/O requests.

Interrupt
The act of translating an interrupt request before it is delivered to the CPU complex.
Remapping

Maximum Guest Address Width: the maximum DMA virtual addressability supported by a
MGAW
remapping hardware implementation.

MSI Message Signalled Interrupts.

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Table 1. Glossary

Term Definition

Second- Translation caches used by remapping hardware units to cache intermediate (non-leaf)
Level entries of the second-level (SL) paging structures. For hardware supporting 48-bit Guest
Caches Address Width, these include SL-PML4 cache, SL-PDP cache, and SL-PDE cache.

Process Address Space Identifier: DMA requests with virtual address (or guest virtual
PASID address) are tagged with a PASID value that identifies the targeted virtual address
space.

PASID- Remapping hardware cache that caches frequently accessed PASID-table entries used to
cache translate DMA requests with PASID.

Data structure used by hardware to report to software if a given PASID is active at a

PASID State
endpoint device or not. PASID state is used by software to implement optimizations for
Table
IOTLB invalidations.

Second-
Paging Structures used for address translation of DMA requests without Process Address
Level
Space ID (PASID).
Paging

A 16-bit identification number to identify the source of a DMA or interrupt request. For
Source ID PCI family devices this is the ‘Requester ID’ which consists of PCI Bus number, Device
number, and Function number.

Root- Refers to one or more hardware components that connect processor complexes to the
Complex I/O and memory subsystems. The chipset may include a variety of integrated devices.

VA Virtual Address: Virtual address used by software on a host processor.

Virtual Machine Monitor: a software layer that controls virtualization. Also referred to as
VMM
hypervisor in this document.

The extension of xAPIC architecture to support 32-bit APIC addressability of processors

x2APIC
and associated enhancements.

1.3 References
Table 2. References

Description

®
Intel 64 Architecture Software Developer's Manuals
http://developer.intel.com/products/processor/manuals/index.htm

PCI-Express* Base Specifications

http://www.pcisig.com/specifications/pciexpress

PCI-Express Address Translation Services Specification, Revision 1.1

http://www.pcisig.com/specifications/iov

PCI-Express Process Address Space ID, and PASID Translation ECNs

PCI-Express Alternative Routing-ID Interpretation (ARI) ECN

PCI-Express Single-Root I/O Virtualization and Sharing (SR-IOV) Specification, Revision 1.0
http://www.pcisig.com/specifications/iov

ACPI Specification
http://www.acpi.info/

PCI-Express to PCI/PCI-X Bridge Specification, Revision 1.0

http://www.pcisig.com/specifications/pciexpress/bridge

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2 Overview

This chapter provides a brief overview of Intel® VT, the virtualization software ecosystem it enables,
and hardware support offered for processor and I/O virtualization.

2.1 Intel® Virtualization Technology Overview

Intel® VT consists of technology components that support virtualization of platforms based on Intel
processors, thereby enabling the running of multiple operating systems and applications in
independent partitions. Each partition behaves like a virtual machine (VM) and provides isolation and
protection across partitions. This hardware-based virtualization solution, along with virtualization
software, enables multiple usages such as server consolidation, activity partitioning, workload
isolation, embedded management, legacy software migration, and disaster recovery.

2.2 VMM and Virtual Machines

Intel® VT supports virtual machine architectures comprised of two principal classes of software:
• Virtual-Machine Monitor (VMM): A VMM acts as a host and has full control of the processor(s)
and other platform hardware. VMM presents guest software (see below) with an abstraction of a
virtual processor and allows it to execute directly on a logical processor. A VMM is able to retain
selective control of processor resources, physical memory, interrupt management, and I/O.
• Guest Software: Each virtual machine is a guest software environment that supports a stack
consisting of an operating system (OS) and application software. Each operates independently of
other virtual machines and uses the same interface to processor(s), memory, storage, graphics,
and I/O provided by a physical platform. The software stack acts as if it were running on a
platform with no VMM. Software executing in a virtual machine must operate with reduced
privilege so that the VMM can retain control of platform resources.

The VMM is a key component of the platform infrastructure in virtualization usages. Intel® VT can
improve the reliability and supportability of virtualization infrastructure software with programming
interfaces to virtualize processor hardware. It also provides a foundation for additional virtualization
support for other hardware components in the platform.

2.3 Hardware Support for Processor Virtualization

Hardware support for processor virtualization enables simple, robust and reliable VMM software. VMM
software relies on hardware support on operational details for the handling of events, exceptions, and
resources allocated to virtual machines.

Intel® VT provides hardware support for processor virtualization. For Intel® 64 processors, this
support consists of a set of virtual-machine extensions (VMX) that support virtualization of processor
hardware for multiple software environments by using virtual machines.

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2.4 I/O Virtualization

A VMM must support virtualization of I/O requests from guest software. I/O virtualization may be
supported by a VMM through any of the following models:
• Emulation: A VMM may expose a virtual device to guest software by emulating an existing
(legacy) I/O device. VMM emulates the functionality of the I/O device in software over whatever
physical devices are available on the physical platform. I/O virtualization through emulation
provides good compatibility (by allowing existing device drivers to run within a guest), but pose
limitations with performance and functionality.
• New Software Interfaces: This model is similar to I/O emulation, but instead of emulating legacy
devices, VMM software exposes a synthetic device interface to guest software. The synthetic
device interface is defined to be virtualization-friendly to enable efficient virtualization compared
to the overhead associated with I/O emulation. This model provides improved performance over
emulation, but has reduced compatibility (due to the need for specialized guest software or
drivers utilizing the new software interfaces).
• Assignment: A VMM may directly assign the physical I/O devices to VMs. In this model, the driver
for an assigned I/O device runs in the VM to which it is assigned and is allowed to interact directly
with the device hardware with minimal or no VMM involvement. Robust I/O assignment requires
additional hardware support to ensure the assigned device accesses are isolated and restricted to
resources owned by the assigned partition. The I/O assignment model may also be used to create
one or more I/O container partitions that support emulation or software interfaces for virtualizing
I/O requests from other guests. The I/O-container-based approach removes the need for running
the physical device drivers as part of VMM privileged software.
• I/O Device Sharing: In this model, which is an extension to the I/O assignment model, an I/O
device supports multiple functional interfaces, each of which may be independently assigned to a
VM. The device hardware itself is capable of accepting multiple I/O requests through any of these
functional interfaces and processing them utilizing the device's hardware resources.

Depending on the usage requirements, a VMM may support any of the above models for I/O
virtualization. For example, I/O emulation may be best suited for virtualizing legacy devices. I/O
assignment may provide the best performance when hosting I/O-intensive workloads in a guest.
Using new software interfaces makes a trade-off between compatibility and performance, and device
I/O sharing provides more virtual devices than the number of physical devices in the platform.

2.5 Intel® Virtualization Technology For Directed I/O

Overview
A general requirement for all of above I/O virtualization models is the ability to isolate and restrict
device accesses to the resources owned by the partition managing the device. Intel® VT for Directed
I/O provides VMM software with the following capabilities:
• I/O device assignment: for flexibly assigning I/O devices to VMs and extending the protection and
isolation properties of VMs for I/O operations.
• DMA remapping: for supporting address translations for Direct Memory Accesses (DMA) from
devices.
• Interrupt remapping: for supporting isolation and routing of interrupts from devices and external
interrupt controllers to appropriate VMs.
• Interrupt posting: for supporting direct delivery of virtual interrupts from devices and external
interrupt controllers to virtual processors.
• Reliability: for recording and reporting of DMA and interrupt errors to system software that may
otherwise corrupt memory or impact VM isolation.

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2.5.1 Hardware Support for DMA Remapping

To generalize I/O virtualization and make it applicable to different processor architectures and
operating systems, this document refers to domains as abstract isolated environments in the platform
to which a subset of host physical memory is allocated.

DMA remapping provides hardware support for isolation of device accesses to memory, and enables
each device in the system to be assigned to a specific domain through a distinct set of paging
structures. When the device attempts to access system memory, the DMA-remapping hardware
intercepts the access and utilizes the page tables to determine whether the access can be permitted;
it also determines the actual location to access. Frequently used paging structures can be cached in
hardware. DMA remapping can be configured independently for each device, or collectively across
multiple devices.

2.5.1.1 OS Usages of DMA Remapping

There are several ways in which operating systems can use DMA remapping:
• OS Protection: An OS may define a domain containing its critical code and data structures, and
restrict access to this domain from all I/O devices in the system. This allows the OS to limit
erroneous or unintended corruption of its data and code through incorrect programming of
devices by device drivers, thereby improving OS robustness and reliability.
• Feature Support: An OS may use domains to better manage DMA from legacy devices to high
memory (For example, 32-bit PCI devices accessing memory above 4GB). This is achieved by
programming the I/O page-tables to remap DMA from these devices to high memory. Without
such support, software must resort to data copying through OS “bounce buffers”.
• DMA Isolation: An OS may manage I/O by creating multiple domains and assigning one or more
I/O devices to each domain. Each device-driver explicitly registers its I/O buffers with the OS, and
the OS assigns these I/O buffers to specific domains, using hardware to enforce DMA domain
protection. See Figure 2-2.
• Shared Virtual Memory: For devices supporting appropriate PCI-Express1 capabilities, OS may use
the DMA remapping hardware capabilities to share virtual address space of application processes
with I/O devices. Shared virtual memory along with support for I/O page-faults enable application
programs to freely pass arbitrary data-structures to devices such as graphics processors or
accelerators, without the overheads of pinning and marshalling of data.

System Memory System Memory

Domain 1 Domain 2

OS Code & Driver A Driver B

Data I/O Buffers I/O Buffers
Driver A Driver B
I/O Buffers I/O Buffers I/O Buffers I/O Buffers

DMA-Remapping Hardware

I/O Devices Device A Device B

Device DMA without isolation Device DMA isolated using DMA remapping hardware

Figure 2-2. Example OS Usage of DMA Remapping

1. Refer to Process Address Space ID (PASID) capability in PCI-Express* base specification.

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2.5.1.2 VMM Usages of DMA Remapping

The limitations of software-only methods for I/O virtualization can be improved through direct
assignment of I/O devices to partitions. With this approach, the driver for an assigned I/O device runs
only in the partition to which it is assigned and is allowed to interact directly with the device hardware
with minimal or no VMM involvement. The hardware support for DMA remapping enables this direct
device assignment without device-specific knowledge in the VMM. See Figure 2-3.

Virtual Machine
VM (0) Virtual Machine
VM (n) Virtual Machine
VM (0) Virtual Machine
VM (n)

App App
App App App
App App App
App App App
App

Guest OS 0 Guest OS 0 Guest OS 0 Guest OS 0

Driver for Driver for Device A Device B

Virtual Devices Virtual Devices Driver Driver

Virtual Machine Monitor (VMM) or Hosting OS

Virtual Devices Emulation
Virtual Machine Monitor (VMM) or Hosting OS
Device A Device B
Driver Driver

DMA-Remapping Hardware

Physical Host Hardware

Device A Device B Device A Device B

Example Software-based
Direct Assignment of I/O Devices
I/O Virtualization

Figure 2-3. Example Virtualization Usage of DMA Remapping

In this model, the VMM restricts itself to enabling direct assignment of devices to their partitions.
Rather than invoking the VMM for all I/O requests from a partition, the VMM is invoked only when
guest software accesses protected resources (such as configuration accesses, interrupt management,
etc.) that impact system functionality and isolation.

To support direct assignment of I/O devices, a VMM must enforce isolation of DMA requests. I/O
devices can be assigned to domains, and the remapping hardware can be used to restrict DMA from
an I/O device to the physical memory presently owned by its domain. For domains that may be
relocated in physical memory, the remapping hardware can be programmed to perform the necessary
translation.

I/O device assignment allows other I/O sharing usages — for example, assigning an I/O device to an
I/O partition that provides I/O services to other user partitions. Remapping hardware enables
virtualization software to choose the right combination of device assignment and software-based
methods for I/O virtualization.

2.5.1.3 DMA Remapping Usages by Guests

A guest OS running in a VM may benefit from the availability of remapping hardware to support the
usages described in Section 2.5.1.1. To support such usages, the VMM may virtualize the remapping
hardware to its guests. For example, the VMM may intercept guest accesses to the virtual remapping
hardware registers, and manage a shadow copy of the guest remapping structures that is provided to
the physical remapping hardware. On updates to the guest I/O page tables, the guest software
performs appropriate virtual invalidation operations. The virtual invalidation requests may be
intercepted by the VMM, to update the respective shadow page tables and perform invalidations of

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remapping hardware. Due to the non-restartability of faulting DMA transactions (unlike CPU memory
management virtualization), a VMM cannot perform lazy updates to its shadow remapping structures.
To keep the shadow structures consistent with the guest structures, the VMM may expose virtual
remapping hardware with eager pre-fetching behavior (including caching of not-present entries) or
use processor memory management mechanisms to write-protect the guest remapping structures.

On hardware implementations supporting two levels of address translations (first-level translation to

remap a virtual address to intermediate (guest) physical address, and second-level translations to
remap a intermediate physical address to machine (host) physical address), a VMM may virtualize
guest OS use of first-level translations (such as for Shared Virtual Memory usages) without shadowing
page-tables, but by configuring hardware to perform nested translation of first and second-levels.

2.5.1.4 Interaction with Processor Virtualization

Figure 2-4 depicts how system software interacts with hardware support for both processor-level
virtualization and Intel® VT for Directed I/O.

Virtual Machines

App App App App App App

Guest Guest Guest
OS OS OS

Virtual Machine Monitor (VMM)

Physical Memory

DMA CPU Accesses

I/O Logical
Devices Processors
DMA CPU Memory
Remapping Virtualization

Figure 2-4. Interaction Between I/O and Processor Virtualization

The VMM manages processor requests to access physical memory via the processor’s memory
management hardware. DMA requests to access physical memory use remapping hardware. Both
processor memory management and DMA memory management are under the control of the VMM.

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2.5.2 Hardware Support for Interrupt Remapping

Interrupt remapping provides hardware support for remapping and routing of interrupt requests from
I/O devices (generated directly or through I/O interrupt controllers). The indirection achieved through
remapping enables isolation of interrupts across partitions.

The following usages are envisioned for the interrupt-remapping hardware.

2.5.2.1 Interrupt Isolation

On Intel architecture platforms, interrupt requests are identified by the Root-Complex as write
transactions targeting an architectural address range (0xFEEx_xxxxh). The interrupt requests are
self-describing (i.e., attributes of the interrupt request are encoded in the request address and data),
allowing any DMA initiator to generate interrupt messages with arbitrary attributes.

The interrupt-remapping hardware may be utilized by a Virtual Machine Monitor (VMM) to improve the
isolation of external interrupt requests across domains. For example, the VMM may utilize the
interrupt-remapping hardware to distinguish interrupt requests from specific devices and route them
to the appropriate VMs to which the respective devices are assigned. The VMM may also utilize the
interrupt-remapping hardware to control the attributes of these interrupt requests (such as
destination CPU, interrupt vector, delivery mode etc.).

Another example usage is for the VMM to use the interrupt-remapping hardware to disambiguate
external interrupts from the VMM owned inter-processor interrupts (IPIs). Software may enforce this
by ensuring none of the remapped external interrupts have attributes (such as vector number) that
matches the attributes of the VMM IPIs.

2.5.2.2 Interrupt Migration

The interrupt-remapping architecture may be used to support dynamic re-direction of interrupts when
the target for an interrupt request is migrated from one logical processor to another logical processor.
Without interrupt-remapping hardware support, re-balancing of interrupts require software to re-
program the interrupt sources. However re-programming of these resources are non-atomic (requires
multiple registers to be re-programmed), often complex (may require temporary masking of interrupt
source), and dependent on interrupt source characteristics (e.g. no masking capability for some
interrupt sources; edge interrupts may be lost when masked on some sources, etc.)

Interrupt-remapping enables software to efficiently re-direct interrupts without re-programming the

interrupt configuration at the sources. Interrupt migration may be used by OS software for balancing
load across processors (such as when running I/O intensive workloads), or by the VMM when it
migrates virtual CPUs of a partition with assigned devices across physical processors to improve CPU
utilization.

2.5.2.3 x2APIC Support

Intel® 64 x2APIC architecture extends the APIC addressability to 32-bits (from 8-bits). Refer to Intel®
64 Architecture Software Developer's Manual, Volume 3B: System Programming Guide for details.

Interrupt remapping enables x2APICs to support the expanded APIC addressability for external
interrupts without requiring hardware changes to interrupt sources (such as I/OxAPICs and MSI/MSI-
X devices).

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2.5.3 Hardware Support for Interrupt Posting

Interrupt posting includes hardware support for optimized processing of interrupt requests from I/O
devices (Physical Functions, or Single Root I/O Virtualization (SR-IOV) Virtual Functions) that are
directly assigned to a virtual machine. The following usages are envisioned for the interrupt-posting
hardware.

2.5.3.1 Interrupt Vector Scalability

Devices supporting I/O virtualization capabilities such as SR-IOV, virtually increases the I/O fan-out of
the platform, by allowing multiple Virtual Functions (VFs) to be enabled for a Physical Function (PF).
Any of these PFs or VFs can be assigned to a virtual machine. Interrupt requests from such assigned
devices are referred to as virtual interrupts as they target virtual processors of the assigned VM.

Each VF requires its own independent interrupt resources, resulting in more interrupt vectors needed
than otherwise required without such I/O virtualization. Without interrupt-posting hardware support,
all interrupt sources in the platform are mapped to the same physical interrupt vector space (8-bit
vector space per logical CPU on Intel®64 processors). For virtualization usages, partitioning the
physical vector space across virtual processors is challenging in a dynamic environment when there is
no static affinity between virtual process and logical processors.

Hardware support for interrupt posting addresses this vector scalability problem by allowing interrupt
requests from device functions assigned to virtual machines to operate in virtual vector space,
thereby scaling naturally with the number of virtual machines or virtual processors.

2.5.3.2 Interrupt Virtualization Efficiency

Without hardware support for interrupt posting, interrupts from devices assigned to virtual machines
are processed through the VMM software. Specifically, whenever an external interrupt destined for a
virtual machine is received by the CPU, control is transferred to the VMM, requiring the VMM to
process and inject corresponding virtual interrupt to the virtual machine. The control transfers
associated with such VMM processing of external interrupts incurs both hardware and software
overheads.

With hardware support for interrupt posting, interrupts from devices assigned to virtual machines are
posted (recorded) in memory descriptors specified by the VMM, and processed based on the running
state of the virtual processor targeted by the interrupt.

For example, if the target virtual processor is running on any logical processor, hardware can directly
deliver external interrupts to the virtual processor without any VMM intervention. Interrupts received
while the target virtual processor is pre-empted (waiting for its turn to run) can be accumulated in
memory by hardware for delivery when the virtual processor is later scheduled. This avoids disrupting
execution of currently running virtual processors on external interrupts for non-running virtual
machines. If the target virtual processor is halted (idle) at the time of interrupt arrival or if the
interrupt is qualified as requiring real-time processing, hardware can transfer control to VMM,
enabling VMM to schedule the virtual processor and have hardware directly deliver pending interrupts
to that virtual processor.

This target virtual processor state based processing of interrupts reduces overall interrupt latency to
virtual machines and reduces overheads otherwise incurred by the VMM for virtualizing interrupts.

2.5.3.3 Virtual Interrupt Migration

To optimize overall platform utilization, VMM software may need to dynamically evaluate the optimal
logical processor to schedule a virtual processor, and in that process, migrate virtual processors
across CPUs.

For virtual machines with assigned devices, migrating a virtual processor across logical processors
either incurs the overhead of forwarding interrupts in software (e.g. via VMM generated IPIs), or
complexity to independently migrate each interrupt targeting the virtual processor to the new logical

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processor. Hardware support for interrupt posting enables VMM software to atomically co-migrate all
interrupts targeting a virtual processor when the virtual processor is scheduled to another logical
processor.

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3 DMA Remapping

This chapter describes the hardware architecture for DMA remapping. The architecture envisions
remapping hardware to be implemented in Root-Complex components, such as the memory controller
hub (MCH) or I/O hub (IOH).

3.1 Types of DMA requests

Remapping hardware treats inbound memory requests from root-complex integrated devices and PCI-
Express attached discrete devices into two categories:
• Requests without address-space-identifier: These are the normal memory requests from endpoint
devices. These requests typically specify the type of access (read/write/atomics), targeted DMA
address/size, and identity of the device originating the request.
• Requests with address-space-identifier: These are memory requests with additional information
identifying the targeted process address space from endpoint devices supporting virtual memory
capabilities. Beyond attributes in normal requests, these requests specify the targeted process
address space identifier (PASID), and extended attributes such as Execute-Requested (ER) flag
(to indicate reads that are instruction fetches), and Privileged-mode-Requested (PR) flag (to
distinguish user versus supervisor access). For details, refer to the Process Address Space ID
(PASID) Capability in the PCI-Express specifications.

For simplicity, this document refers to these categories as Requests-without-PASID, and

Requests-with-PASID. Previous versions of this specification supported only remapping of
requests-without-PASID.

3.2 Domains and Address Translation

A domain is abstractly defined as an isolated environment in the platform, to which a subset of the
host physical memory is allocated. I/O devices that are allowed to access physical memory directly
are allocated to a domain and are referred to as the domain’s assigned devices. For virtualization
usages, software may treat each virtual machine as a separate domain.

The isolation property of a domain is achieved by blocking access to its physical memory from
resources not assigned to it. Multiple isolated domains are supported in a system by ensuring that all
I/O devices are assigned to some domain (possibly a null domain), and that they can only access the
physical resources allocated to their domain. The DMA remapping architecture facilitates flexible
assignment of I/O devices to an arbitrary number of domains. Each domain has a view of physical
address space that may be different than the host physical address space. Remapping hardware
treats the address in inbound requests as DMA Address. Depending on the software usage model, the
DMA address space may be the Guest-Physical Address (GPA) space of the virtual machine to which
the device is assigned, or application Virtual Address (VA) space defined by the PASID assigned to an
application, or some abstract I/O virtual address (IOVA) space defined by software. In all cases, DMA
remapping transforms the address in a DMA request issued by an I/O device to its corresponding
Host-Physical Address (HPA).

For simplicity, this document refers to address in requests-without-PASID as GPA, and address in
requests-with-PASID as Virtual Address (VA) (or Guest Virtual Address (GVA), if such request is from
a device assigned to a virtual machine). The translated address is referred to as HPA.

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Figure 3-5 illustrates DMA address translation. I/O devices 1 and 2 are assigned to domains 1 and 2,
respectively. The software responsible for creating and managing the domains allocates system
physical memory for both domains and sets up the DMA address translation function. DMA address in
requests initiated by devices 1 & 2 are translated to appropriate HPAs by the remapping hardware.

10000h

Domain 1 HPA = (G)VA/GPA

4000h
6000h HPA = = 4000h
6000h Device 1

CPU Assigned to
DM A Domain 1
Mem ory
Mem ory
Management
Managem ent

(G)VA/GPA
Dom ain 2 4000h HPA = HPA = = 4000h
Device 2
3000h 3000h

Assigned to
0h Domain 2
Physical
Memory

Figure 3-5. DMA Address Translation

The host platform may support one or more remapping hardware units. Each hardware unit supports
remapping DMA requests originating within its hardware scope. For example, a desktop platform may
expose a single remapping hardware unit that translates all DMA transactions at the memory
controller hub (MCH) component. A server platform with one or more core components may support
independent translation hardware units in each component, each translating DMA requests originating
within its I/O hierarchy (such as a PCI-Express root port). The architecture supports configurations in
which these hardware units may either share the same translation data structures (in system
memory) or use independent structures, depending on software programming.

The remapping hardware translates the address in a request to host physical address (HPA) before
further hardware processing (such as address decoding, snooping of processor caches, and/or
forwarding to the memory controllers).

3.3 Remapping Hardware - Software View

The remapping architecture allows hardware implementations supporting a single PCI segment group
to expose (to software) the remapping function either as a single hardware unit covering the entire
PCI segment group, or as multiple hardware units, each supporting a mutually exclusive subset of
devices in the PCI segment group hierarchy. For example, an implementation may expose a
remapping hardware unit that supports one or more integrated devices on the root bus, and
additional remapping hardware units for devices behind one or a set of PCI-Express root ports. The
platform firmware (BIOS) reports each remapping hardware unit in the platform to software. Chapter
8 describes a proposed reporting structure through ACPI constructs.

For hardware implementations supporting multiple PCI segment groups, the remapping architecture
requires hardware to expose independent remapping hardware units (at least one per PCI segment
group) for processing requests originating within the I/O hierarchy of each segment group.

3.4 Mapping Devices to Domains

The following sub-sections describe the DMA remapping architecture and data structures used to map
I/O devices to domains.

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3.4.1 Source Identifier

Each inbound request appearing at the address-translation hardware is required to identify the device
originating the request. The attribute identifying the originator of an I/O transaction is referred to as
the “source-id” in this document. The remapping hardware may determine the source-id of a
transaction in implementation-specific ways. For example, some I/O bus protocols may provide the
originating device identity as part of each I/O transaction. In other cases (for Root-Complex
integrated devices, for example), the source-id may be derived based on the Root-Complex internal
implementation.

For PCI-Express devices, the source-id is the requester identifier in the PCI-Express transaction layer
header. The requester identifier of a device, which is composed of its PCI Bus/Device/Function
number, is assigned by configuration software and uniquely identifies the hardware function that
initiated the request. Figure 3-6 illustrates the requester-id1 as defined by the PCI-Express
Specification.

1
5 87 3 2 0

Bus # Device # Function #

Figure 3-6. Requester Identifier Format

The following sections describe the data structures for mapping I/O devices to domains.

3.4.2 Root-Entry & Extended-Root-Entry

The root-table functions as the top level structure to map devices to their respective domains. The
location of the root-table in system memory is programmed through the Root Table Address Register
described in Section 10.4.6. The root-table is 4-KByte in size and contains 256 root-entries to cover
the PCI bus number space (0-255). The bus number (upper 8-bits) encoded in a request’s source-id
field is used to index into the root-entry structure.

Each root-entry contains the following fields:

• Present flag: The present field indicates the root-entry is present and the context-table pointer
(CTP) field is initialized. Software may Clear the present field for root entries corresponding to bus
numbers that are either not present in the platform, or don’t have any downstream devices
attached. DMA requests processed through root-entries with present field Clear result in
translation-fault.
• Context-table pointer: The context-table pointer references the context-table for devices on
the bus identified by the root-entry. Section 3.4.3 describes context-entries in the context-table.

Section 9.1 provides the exact root-table entry format.

For implementations supporting Extended-Context-Support (ECS=1 in Extended Capability Register),

the Root Table Address Register (RTADDR_REG) points to an extended-root-table when Root-Table-
Type field in the Register is Set (RTT=1). The extended-root-table is similar to the root-table (4KB in
size and containing 256 extended-root-entries to cover the 0-255 PCI bus number space), but has an
extended format to reference extended-context-tables.

Each extended-root-entry contains the following fields:

1. For PCI-Express devices supporting Alternative Routing-ID Interpretation (ARI), bits traditionally
used for the Device Number field in the Requester-id are used instead to expand the Function
Number field.

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• Lower Present flag: The lower-present field indicates the lower 64-bits of the extended-root-
entry is present and the lower-context-table pointer (LCTP) field is initialized. Software may Clear
the lower-present field for extended-root-entries corresponding to bus numbers that are either
not present in the platform, or don’t have downstream devices with device numbers 0-15
attached. DMA requests processed through the lower part of an extended-root-entry with the
lower-present field Clear result in translation-fault.
• Lower Context-table pointer: The lower-context-table pointer references the lower-context-
table for devices with device number 0-15, on the bus identified by the referencing extended-
root-entry. Section 3.4.4 describes extended-context-entries in the lower-context-table.
• Upper Present flag: The upper-present field indicates the upper 64-bits of the extended-root-
entry is present and the upper-context-table pointer (UCTP) field is initialized. Software may Clear
the upper-present field for extended-root-entries corresponding to bus numbers that are either
not present in the platform, or don’t have downstream devices with device numbers 16-31
attached. DMA requests processed through the upper part of an extended-root-entry with the
upper-present field Clear result in translation-fault.
• Upper Context-table pointer: The upper-context-table pointer references the upper-context-
table for devices with device number 16-31, on the bus identified by the referencing extended-
root-entry. Section 3.4.4 describes extended-context-entries in the upper-context-table.

Section 9.2 provides the exact extended-root-table entry format.

3.4.3 Context-Entry
A context-entry maps a specific I/O device on a bus to the domain to which it is assigned, and, in
turn, to the address translation structures for the domain. The context entries are programmed
through memory-resident context-tables. Each root-entry in the root-table contains the pointer to the
context-table for the corresponding bus number. Each context-table contains 256 entries, with each
entry corresponding to a PCI device function on the bus. For a PCI device, the device and function
numbers (lower 8-bits) of source-id are used to index into the context-table. Figure 3-7 illustrates
device to domain mapping through root-table.

(Dev 31, Func 7) Context-entry 255

(Dev 0, Func 1)

(Bus 255) Root-entry 255 (Dev 0, Func 0) Context-entry 0

Address Translation
Context-table for Structures for Dom ain A
Bus N
(Bus N) Root-entry N

(Bus 0) Root-entry 0

Root-table

Context-entry 255

Address Translation
Structures for Dom ain B
Context-entry 0
Context-table for
Bus 0

Figure 3-7. Device to Domain Mapping Structures using Root-Table

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Context-entries support only requests-without-PASID, and contains the following fields:

• Present Flag: The present field is used by software to indicate to hardware whether the context-
entry is present and initialized. Software may Clear the present field for context entries
corresponding to device functions that are not present in the platform. If the present field of a
context-entry used to process a request is Clear, the request is blocked, resulting in a translation-
fault.
• Translation Type: The translation-type field indicates what types of requests are allowed
through the context-entry, and the type of the address translation that must be used for such
requests.
• Address Width: The address-width field indicates the address-width of the domain to which the
device corresponding to the context-entry is assigned.
• Second-level Page-table Pointer: The second-level page-table pointer field provides the host
physical address of the address translation structure in system memory to be used for remapping
requests-without-PASID processed through the context-entry.
• Domain Identifier: The domain-identifier is a software-assigned field in a context-entry that
identifies the domain to which a device with the given source-id is assigned. Hardware may use
this field to tag its caching structures. Context entries programmed with the same domain
identifier must reference the same address translation structure. Context entries referencing the
same address translation structures are recommended to use the same domain-identifier for best
hardware efficiency.
• Fault Processing Disable Flag: The fault-processing-disable field enables software to
selectively disable recording and reporting of remapping faults detected for requests processed
through the context-entry.

Multiple devices may be assigned to the same domain by programming the context-entries for the
devices to reference the same translation structures, and programming them with the same domain
identifier. Section 9.3 provides the exact context-entry format.

3.4.4 Extended-Context-Entry
For implementations supporting Extended-Context-Support (ECS=1 in Extended Capability Register),
when using extended-root-table, each extended-root-entry references a lower-context-table and a
upper-context-table. The Lower-context-table is 4-KByte in size and contains 128 extended-context-
entries corresponding to PCI functions in device range 0-15 on the bus. The Upper-context-table is
also 4-KByte in size and contains 128 extended-context-entries corresponding to PCI functions in
device range 16-31 on the bus. Figure 3-8 illustrates device to domain mapping through extended-
root-table.

Extended-context-entries are capable of supporting both requests-without-PASID and requests-with-

PASID. For requests-without-PASID, it supports the same fields as in the regular context-entry
(described above). Section 9.4 provides the exact extended-context-entry format. For requests-with-
PASID, extended-context-entries contain the following additional fields:
• Extended Translation Type: The translation-type field is extended to provide additional
controls to specify how requests with and without PASID should be processed. Extended-context-
entries supports two levels of translation, referred to as first-level translation and second-level
translation. First-level translation applies to requests-with-PASID. Second-level translation applies
to requests-without-PASID. When nested translation is specified in the extended-context-entry,
requests-with-PASID are subject to nested first-level and second-level translation.
• Translation Structure Pointers: For first-level translation, the extended-context-entry contains
a pointer to a PASID-table. Each 8-byte PASID-table-entry corresponds to a PASID value, and
contains the root of first-level translation structures used to translate requests-with-PASID tagged
with the respective PASID. For second-level translation, extended-context-entry contains a
pointer to the second-level page-table, which is the same as the second-level page-table pointer
field in the regular context-entry (described in Section 3.4.3).

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• Translation Controls: These include additional controls such as Page-Global-Enable, Write-

Protect-Enable, No-Execute-Enable, Supervisor-Mode-Execute-Protection, etc. that are applied
when processing requests-with-PASID.
• Memory-type Attributes: Extended-context-entries support fields such as Page-Attribute-Table,
Extended-memory-type etc., that are used to compute the effective memory-type for requests-
with-PASID from devices operating in the processor coherency domain.
• Page Request Enable: The page-request-enable field in the extended-context-entry allows
software to selectively enable or disable page-fault requests from the device. When enabled,
page-requests from the device are reported to software through a memory-resident page-
request-queue. Chapter 7 provides details on page request processing.
• Deferred Invalidation Controls: The PASID-state table pointer field enables devices to
communicate whether a given address-space (PASID) is active or not at the device. Software can
utilize the PASID-state tables for deferred invalidation of cached mappings for inactive PASIDs in
translation caches (TLBs). Chapter 6 describes the various translation caching structures and
invalidation operations, including deferred invalidation support.

Figure 3-8 illustrates device to domain mapping using extended-root-table.

(Dev 31, Func 7) E xt-context-entry 127

(Dev 16, Func 1)

(Dev 16, Func 0) E xt-context-entry 0

U p p er-co n text-tab le
fo r B u s N
(Bus 255) E xt-root-entry 255

(Dev 15, Func 7) E xt-context-entry 127

(Bus N) Ext-root-entry N

S econd -level P aging

Structures for D om ain A
(Dev 0, Func 1)
(Dev 0, Func 0) E xt-context-entry 0
L o w er-co n text-tab le
fo r B u s N

E xt-context-entry 127
P A SID -entry P 2
F irst-level P aging
(Bus 0) E xt-root-entry 0 PA S ID -entry P 1 S tructures for
Process P 2
E xten d ed -ro o t-tab le
P AS ID -entry 0
P A S ID -T ab le fo r
D o m ain B
E xt-context-entry 0
U p p er-co n text-tab le
fo r B u s 0

F irst-level P aging
E xt-context-entry 127 S tructures for
Process P 1

S econd -level P aging

Structures for D om ain B

Ext-context-entry 0
L o w er-co n text-tab le
fo r B u s 0

Figure 3-8. Device to Domain Mapping Structures using Extended-Root-Table

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Exploring the Variety of Random
Documents with Different Content
Beauties of the Anti-Jacobin, The, its libel on C., 320 and note.

Becky Fall, 305 n.

Beddoes, Dr. Thomas, 157, 211, 338;

C.’s grief at his death, 543 and note, 544 and note;
his advice and sympathy in response to C.’s confession, 543 n.;
his character. 544.

Bedford, Grosvenor, 400 n.

Beet sugar, 299 and note.

Beguines, the, 327 n.

Bell, Rev. Andrew, D. D., 575, 582 and note, 605;

his Origin, Nature, and Object of the New System of Education,
581 and note, 582.

Bell, Rev. Andrew, Life of, by R. and C. C. Southey, 581 n.

Bellingham, John, 598 n.

Bell-ringing in Germany, 293.

Belper, Lord (Edward Strutt), 215 n.

Bennett, Abraham, his electroscope, 218 n., 219 n.

Bentley’s Quarto Edition of Horace, 68 and note.

Benvenuti, 498, 499.

Benyowski, Count, or the Conspiracy of Kamtschatka, a Tragi-

comedy, by Kotzebue, 236 and note.
Berdmore, Mr., 80, 82.

Bernard, Sir Thomas, 579 and notes, 580, 582, 585, 595 n., 599.

Betham, Matilda, To. From a Stranger, 404 n.

Bible, The, as literature, C.’s opinion of, 200;

slovenly hexameters in, 398.

Bibliography, Southey’s proposed work, 428-430.

Bibliotheca Britannica, or an History of British Literature, a proposed

work, 425-427, 429, 430.

Bigotry, 198.

Billington, Mrs. Elizabeth Weichsel, 368.

Bingen, 751.

Biographia Literaria, 3, 68 n., 74 n., 152 n., 164 n., 174 n., 232 n.,
257, 320 n., 498 n., 607 n., 669 n., 670 n.;
C. ill-used by the printer of, 673, 674;
679, 756 n.

Birmingham, 151, 152.

Bishop’s Middleham, 358 and note, 360.

Blackwood’s Magazine, 756.

Blake, William, as poet, painter, and engraver, 685 n., 686 n.;
C.’s criticism of his poems and their accompanying illustrations,
686-688;
his Songs of Innocence and Experience, 686 n.
Bloomfield, Robert, 395.

Blumenbach, Prof., 279, 298.

Book of the Church, The, 724.

Books, C.’s early taste in, 11 and note, 12;

in later life, 180, 181.

Booksellers, C.’s horror of, 548.

Borrowdale, 431.

Borrowdale mountains, the, 370.

Botany Bay Eclogues, by Robert Southey, 76 n., 116.

Bourbons, C.’s Essay on the restoration of the, 629 and note.

Bourne, Sturges, 542.

Bovey waterfall, 305 n.

Bowdon, Anne, marries Edward Coleridge, 53 n.

Bowdon, Betsy, 18.

Bowdon, John (C.’s uncle), C. goes to live with, 18, 19.

Bowdons, the, C.’s mother’s family, 4.

Bowles, the surgeon, 212.

Bowles, To, 111.

Bowles, Rev. William Lisle, C.’s admiration for his poems, 37, 42,
179;
63 n., 76 and note;
C.’s sonnet to, 111 and note;
115;
his sonnets, 177;
his Hope, an Allegorical Sketch, 179, 180;
196, 197, 211;
his translation of Dean Ogle’s Latin Iambics, 374 and note;
school life at Winchester, 374 n.;
C.’s, Southey’s, and Sotheby’s admiration of, and its effect on their
poems, 396;
borrows a line from a poem of C.’s, 396;
his second volume of poems, 403, 404;
637, 638, 650-652.

Bowscale, the mountain, 339.

Box, 631.

Boyce, Anne Ogden, her Records of a Quaker Family, 538 n.

Boyer, Rev. James, 61, 113, 768 n.

Brahmin creed, the, 229.

Brandes, Herr von, 279.

Brandl’s Samuel Taylor Coleridge and the English Romantic School,

258, 674 n., 740 n.

Bratha, 394, 535.

Bray, near Maidenhead, 69, 70.

Brazil, Emperor of, an enthusiastic student and admirer of C., 696.

Bread-riots, 643 n.

Brecon, 410, 411.

Bremhill, 650.

Brent, Mr., 598, 599.

Brent, Miss Charlotte, 520, 524-526;

C.’s affection for, 565;
577, 585, 600, 618, 643, 722 n.;
letter from C., 722.
See Morgan family, the.

Brentford, 326, 673 n.

Bridgewater, 164.

Bright, Henry A., 245 n.

Bristol, C.’s bachelor life in, 133-135;

138, 139, 163 n., 166, 167, 184, 326, 414, 520, 572 n., 621, 623,
624.

Bristol Journal, 633 n.

British Critic, the, 350.

Brookes, Mr., 80, 82.

Brothers, The, by Wordsworth, the original of Leonard in, 494 n.;

C. accused of borrowing a line from, 609 n.

Brown, John, printer and publisher of The Friend, 542 n.

Brun, Frederica, C.’s indebtedness to her for the framework of the

Hymn before Sunrise in the Vale of Chamouni, 405 n.

Bruno, Giordano, 371.

Brunton, Miss, 86 and note, 87, 89;

verses to, 94.

Brunton, Elizabeth, 86 n.

Brunton, John, 86 n., 87.

Brunton, Louisa, 86 n.

Bryant, Jacob, 216 n., 219.

Buchan, Earl of, 139.

Buclé, Miss, 136.

See Cruikshank, Mrs. John.

Buller, Sir Francis (Judge), 6 n.;

obtains a Christ’s Hospital Presentation for C., 18.

Buonaparte, 308, 327 n., 329 and note;

his animosity against C., 498 n.;
530 n.;
C.’s cartoon and lines on, 642.

Burdett, Sir Francis, 598.

Burke, Edmund, C.’s sonnet to, 116 n., 118;

his Letter to a Noble Lord, 157 and note;
Thelwall on, 166;
177.

Burnett, George, 74, 121, 140-142, 144-151, 174 n., 325, 467.
Burns, Robert, 196;
C.’s poem on, 206 and note, 207.

Burton, 326.

Burton’s Anatomy of Melancholy, 428.

Busts of C., 570 n., 571, 695 n.

Butler, Samuel (afterwards Head Master of Shrewsbury and Bishop

of Lichfield), 46 and note.

Buttermere, 393.

Byron, Lord, his Childe Harold, 583;

666, 694, 726.

Byron, Lord, Conversations of, by Capt. Thomas Medwin, 735 and

note.

Cabriere, Miss, 18.

Caermarthen, 411.

Caldbeck, 376 n., 724.

Calder, the river, 339.

Caldwell, Rev. George, 25 and note, 29, 71, 82.

Calne, Wiltshire, C.’s life at, 641-653.

Calvert, Raisley, 345 n.

Calvert, William, proposes to study chemistry with C. and
Wordsworth, 345;
his portrait in a poem of Wordsworth’s, 345 n.;
proposes to share his new house near Greta Hall with Wordsworth
and his sister, 346;
his sense and ability, 346;
347, 348.

Cambridge, description of, 39;

137, 270.

Cambridge, Reminiscences of, by Henry Gunning, 24 n., 363 n.

Cambridge Intelligencer, The, 93 n., 218 n.

Cambridge University, C.’s life at, 22-57, 70-72, 81-129;

C. thinks of leaving, 97 n.;
137.

Cameos and intaglios, casts of, 703 and note.

Campbell, James Dykes, 251 n., 337 n.;

his Samuel Taylor Coleridge, 269 n., 527 n., 572 n., 600 n., 631 n.,
653 n., 666 n., 667 n., 674 n., 681 n., 684 n., 698 n., 752 n., 753 n.,
772 n.

Canary Islands, 417, 418.

Canning, George, 542, 674.

Canova, Antonio, on Allston’s modelling, 573.

Cape Esperichel, 473.

Carlisle, Sir Anthony, 341 and note.

Carlton House, 392.

Carlyle, Thomas, his portrait of C. in the Life of Sterling, 771 n.

Carlyon, Clement, M. D., his Early Years and Late Recollections, 258,
298 n.

Carnosity, Mrs., 472.

Carrock, the mountain, a tempest on, 339, 340.

Carrock man, the, 339.

Cartwright, Major John, 635 and note.

Cary, Rev. Henry, his Memoir of H. F. Cary, 676 n.

Cary, H. F., Memoir of, by Henry Cary, 676 n.

Cary, Rev. H. F., his translation of the Divina Commedia, 676, 677
and note, 678, 679;
C. introduces himself to, 676 n.;
685, 699;
letters from C., 676, 677, 731, 760.

Casimir, the Barbou, 67 and notes, 68.

Castlereagh, Lord, 662.

Castle Spectre, The, a play by Monk Lewis, C.’s criticism of, 236 and
note, 237, 238;
626.

Catania, 458.

Cat-serenades in Malta, 483 n., 484 n.

Catherine II., Empress of Russia, 207 n.

Cathloma, 51.

Catholic Emancipation, C.’s Letters to Judge Fletcher on, 629 and

note, 634 and note, 635, 636, 642.

Catholicism in Germany, 291, 292.

Catholic question, the, letters in the Courier on, 567 and note;
C. proposes to again write for the Courier on, 660, 662;
arrangements for the proposed articles on, 664, 665.

Cattermole, George, 750 n.;

letter from C., 750.

Cattermole, Richard, 750 n.

Cattle, disposal of dead and sick, in Germany, 294.

Chalmers, Rev. Thomas, D. D., calls on C., 752 and note.

Chantrey, Mr. (afterwards Sir) Francis, R. A., C.’s impressions of, 699;
727.

Chapman, Mr., appointed Public Secretary of Malta, 491, 496.

Character, A, 631 n.

Charity, 110 n.

Chatterton, Monody on the Death of, 110 n., 158 n.;

C.’s opinion of it in 1797, 222, 223;
620 n.
Chatterton, Thomas, unpopularity of his poems, 221, 222;
Southey’s exertions in aid of his sister, 221, 222.

Chemistry, C. proposes to study, 345-347.

Chepstow, 139, 140 n.

Chester, John, accompanies C. to Germany, 259;

265, 267, 269 n., 272, 280, 281, 300.

Childe Harold, by Byron, 583.

Childhood, memory of, in old age, 428.

Children in cotton factories, legislation as to the employment of, 689

and note.

Christ, both God and man, 710.

Christabel, written in a dream or dreamlike reverie, 245 n.;

310, 313, 317, 337 and note, 342, 349;
Conclusion to Part II., 355 and note, 356 n.;
Part II., 405 n.;
a fine edition proposed, 421, 422;
437 n., 523;
C. quotes from, 609, 610;
the broken friendship commemorated in, 609 n.;
the copyright of, 669;
the Edinburgh Review’s unkind criticism of, 669 and note, 670;
Mr. Frere advises C. to finish, 674;
696.

Christianity, the one true Philosophy (C.’s magnum opus), outline of,
632, 633;
fragmentary remains of, 632 n.;
the sole motive for C.’s wish to live, 668;
 J. H. Green helps to lay the foundations of, 679 n.;
694, 753;
plans for, 772, 773.

Christian Observer, 653 n.

Christmas Carol, A, 330.

Christmas Indoors in North Germany, 257, 275 n.

Christmas Out of Doors, 257.

Christmas-tree, the German, 289, 290.

Christ’s Hospital, C.’s life at, 18-22;

173 n.

Christ’s Hospital Five and Thirty Years Ago, by Charles Lamb, 20 n.

Christ’s Hospital, List of Exhibitioners, from 1566-1885, 41 n.

Chronicle, Morning, 111 n., 114, 116 n., 119 n., 126, 162, 167, 505,
506, 606 n., 615, 616.

Chubb, Mr., of Bridgwater, 231.

Church, The Book of the, by Southey, 724.

Church, the English, 135, 306, 651-653, 676, 757.

Church, the Scottish, in a state of ossification, 744, 745.

Church, the Wesleyan, 769.

Cibber, Colley, and his son, Theophilus, 693.

Cibber, Theophilus, his reply to his father, 693.

Cintra, Wordsworth’s pamphlet on the Convention of, 534 and note,

543 and note;
C.’s criticism of, 548-550.

Clagget, Charles, 70 and note.

Clare, Lord, 638.

Clarke, Mrs., the notorious, 543 n.

Clarkson, Mrs., 592.

Clarkson, Thomas, 363, 398;

his History of the Abolition of the Slave Trade, 527 and note, 528-
530;
his character, 529, 530;
C.’s review of his book, 535, 536;
538 n., 547, 548;
on the second rupture between C. and Wordsworth, 599 n.

Clement, Mr., a bookseller, 548.

Clergyman, an earnest young, 691.

Clevedon, C.’s honeymoon at, 136.

Clock, a motto for a market, 553 and note, 554 n.

Coates, Matthew, 441 n.;

his belief in the impersonality of the deity, 444;
letter from C., 441.

Coates, Mrs. Matthew, 442, 443.

Cobham, 673 n.

Cole, Mrs., 271.

Coleorton, Memorials of, 369 n., 440.

Coleorton Farmhouse, C.’s visit to the Wordsworths at, 509-514.

Coleridge, Anne (sister—usually called “Nancy”), 8 and note, 21, 26.

Coleridge, Berkeley (son), birth of, 247 and note, 248, 249;
taken with smallpox, 259 n., 260 n.;
262, 267, 272;
death of, 247 n., 282-287, 289.

Coleridge, David Hartley (son—usually called “Hartley”), birth of,

169;
176, 205, 213, 220, 231, 245, 260-262, 267 n., 289, 296, 305,
318;
his talkativeness and boisterousness at the age of three, 321;
his theologico-astronomical hypothesis as to stars, 323;
a pompous remark by, 332;
illness, 342, 343;
early astronomical observations, 342, 343;
an extraordinary creature, 343, 344;
345 n., 355, 356 n., 359;
a poet in spite of his low forehead, 395;
408, 413, 416, 421;
at seven years, 443;
plans for his education, 461, 462;
468, 508;
visits the Wordsworths at Coleorton Farmhouse with his father,
509-514;
as a traveller, 509;
his character at ten years, 510, 512;
511;
 under his father’s sole care for four or five months, 511 n.;
spends five or six weeks with his father and the Wordsworths at
Basil Montagu’s house in London, 511 n.;
portraits of, 511 n.;
521;
his appearance, behavior, and mental acuteness at the age of
thirteen, 564;
at fifteen, 576, 577;
at Mr. Dawes’s school, 576 and note, 577;
583 n.;
friendly relations with his cousins, 675 and note;
C. asks Poole to invite him to Stowey, 675;
visits Stowey, 675 n.;
684, 721, 726;
letter of advice from S. T. C., 511.

Coleridge, Derwent (son of S. T. C. and father of the editor), birth

baptism of, 338 and note;
344, and 355, 359;
learns his letters, 393, 395;
408, 413, 416;
at three years, 443;
462, 468, 521;
at nine years, 564;
at eleven years, 576, 577;
at Mr. Dawes’s school, 576 and note, 577;
580, 605 n., 671 n.;
John Hookham Frere’s assistance in sending him to Cambridge,
675 and note;
707, 711.

Coleridge, Miss Edith, 670 n.

Coleridge, Edward (brother), 7, 53-55, 699 n.

Coleridge, Rev. Edward (nephew), 724 n.;

 letters from C., 724, 738, 744.

Coleridge, Frances Duke (niece), 726 and note, 740.

Coleridge, Francis Syndercombe (brother), 8, 9, 11, 12, 13;

his boyish quarrel with S. T. C., 13, 14;
becomes a midshipman, 17;
dies, 53 and note.

Coleridge, Frederick (nephew), 56.

Coleridge, Rev. George (brother), 7, 8;

his character and ability, 8;
12, 21 n., 25 n.;
his lines to Genius, Ibi Hæc Incondita Solus, 43 n.;
59;
his self-forgetting economy, 65;
extract from a letter from J. Plampin, 70 n.;
95, 97 n., 98 and note, 261;
visit from S. T. C. and his wife, 305 n., 306;
467, 498 n., 512;
disapproves of S. T. C.’s intended separation from his wife and
refuses to receive him and his family into his house, 523 and note;
699 n.;
approaching death of, 746-748;
S. T. C.’s relations with, 747, 748;
letters from S. T. C., 22, 23, 42, 53, 55, 59, 60, 62-70, 103, 239.

Coleridge, the Rev. George, To, a dedication, 223 and note.

Coleridge, Rev. George May (nephew), his friendly relations with

Hartley C., 675 and note;
letter from C., 746.

Coleridge, Hartley, Poems of, 511 n.

Coleridge, Henry Nelson (nephew and son-in-law), 3, 553 n., 570 n.,
579 n., 744-746;
sketch of his life, 756 n.;
letter from S. T. C., 756.

Coleridge, Mrs. Henry Nelson (Sara Coleridge), 9 n., 163 n.;

extract from a letter from Mrs. Wordsworth, 220 n.;
320 n., 327 n., 572 n.

Coleridge, James, the younger, (nephew), his narrow escape, 56.

Coleridge, Colonel James (brother), 7, 54, 56, 61, 306, 724 n., 726
n.;
letter from S. T. C., 61.

Coleridge, Mrs. James (sister-in-law), 740.

Coleridge, John (brother), 7.

Coleridge, John (grandfather), 4, 5.

Coleridge, Mrs. John (mother), 5 n., 7, 13-17, 21 n., 25, 56;

letter from S. T. C., 21.

Coleridge, Rev. John (father), 5 and note, 6, 7, 10-12, 15, 16;

dies, 17, 18;
his character, 18.

Coleridge, John Duke, Lord Chief-Justice (great-nephew), 572 n., 699

n., 745 n.

Coleridge, Sir John Taylor (nephew), his friendly relations with

Hartley C., 675 and note;
editor of The Quarterly Review, 736 and note, 737;
his judgment and knowledge of the world, 739;
delighted with Aids to Reflection, 739;
 740 n., 744, 745;
letter from S. T. C., 734.

Coleridge, Luke Herman (brother), 8, 21, 22.

Coleridge, Samuel Taylor, his autobiographical letters to Thomas

Poole, 3-18;
ancestry and parentage, 4-7;
birth, 6, 9 and note;
his brothers and sister, 7-9;
christened, 9;
infancy and childhood, 9-12;
learns to read, 10;
early taste in books, 11 and note, 12;
his dreaminess and indisposition to bodily activity in childhood, 12;
boyhood, 12-21;
has a dangerous fever, 12-13;
quarrels with his brother Frank, runs away, and is found and
brought back, 13-15;
his imagination developed early by the reading of fairy tales, 16;
a Christ’s Hospital Presentation procured for him by Judge Buller,
18;
visits his maternal uncle, Mr. John Bowdon, in London, 18, 19;
becomes a Blue-Coat boy, 19;
his life at Christ’s Hospital, 20-22;
enters Jesus College, Cambridge, 22, 23;
becomes acquainted with the Evans family, 23 and note, 24;
writes a Greek Ode, for which he obtains the Browne gold medal
for 1792, 43 and note;
is matriculated as pensioner, 44 and note;
his examination for the Craven Scholarship, 45 and note, 46;
his temperament, 47;
takes violin lessons, 49;
enlists in the army, 57 and note;
nurses a comrade who is ill of smallpox in the Henley workhouse,
58 and note;
 his enlistment disclosed to his family, 57 n., 58, 59;
remorse, 59-61, 64, 65;
arrangements resulting in his discharge, 61-70;
his religious beliefs at twenty-one, 68, 69;
returns to the university and is punished, 70, 71;
drops his gay acquaintances and settles down to hard work, 71;
makes a tour of North Wales with Mr. J. Hucks, 72-81;
falls in love with Miss Sarah Fricker, 81;
proposes to go to America with a colony of pantisocrats, 81, 88-
91, 101-103;
his interest in Miss Fricker cools and his old love for Mary Evans
revives, 89;
his indolence, 103, 104;
on his own poetry, 112;
considers going to Wales with Southey and others to found a
colony of pantisocrats, 121, 122;
his love for Mary Evans proves hopeless, 122-126;
in lodgings in Bristol after having left Cambridge without taking his
degree, 133-135;
marries Miss Sarah Fricker and spends the honeymoon in a
cottage at Clevedon, 136;
breaks with Southey, 136-151;
happiness in early married life, 139;
his tour to procure subscribers for the Watchman, 151 and note,
152-154;
poverty, 154, 155;
receives a communication from Mr. Thomas Poole that seven or
eight friends have undertaken to subscribe a certain sum to be paid
annually to him as the author of the monody on Chatterton, 158 n.;
discontinues the Watchman, 158;
takes Charles Lloyd into his home, 168-170;
birth of his first child, David Hartley, 169;
considers starting a day school at Derby, 170 and note;
has a severe attack of neuralgia for which he takes laudanum,
173-176;
early use of opium and beginning of the habit, 173 n., 174 n.;
 selects twenty-eight sonnets by himself, Southey, Lloyd, Lamb,
and others and has them privately printed, to be bound up with
Bowles’s sonnets, 177, 206 and note;
his description of himself in 1796, 180, 181;
his personal appearance as described by another, 180 n., 181 n.;
anxious to take a cottage at Nether Stowey and support himself
by gardening, 184-194;
makes arrangements to carry out this plan, 209;
his partial reconciliation with Southey, 210, 211;
in the cottage at Nether Stowey, 213;
his engagement as tutor to the children of Mrs. Evans of Darley
Hall breaks down, 215 n.;
his visit at Mrs. Evans’s house, 216;
daily life at Nether Stowey, 219, 220;
visits Wordsworth at Racedown, 220 and note, 221;
secures a house (Alfoxden) for Wordsworth near Stowey, 224;
visits him there, 227;
finishes his tragedy, Osorio, 231;
suspected of conspiracy with Wordsworth and Thelwall against the
government, 232 n.;
accepts an annuity of £150 for life from Josiah and Thomas
Wedgwood, 234 and note, 235 and note;
declines an offer of the Unitarian pastorate at Shrewsbury, 235
and note, 236;
writes Joseph Cottle in regard to a third edition of his poems, 239;
rupture with Lloyd, 238, 245 n., 246;
first recourse to opium to relieve distress of mind, 245 n.;
birth of a second child, Berkeley, 247;
temporary estrangement from Lamb caused by Lloyd, 249-253;
goes to Germany with William Wordsworth, Dorothy Wordsworth,
and John Chester, for the purpose of study and observation, 258-
262;
life en pension with Chester in the family of a German pastor at
Ratzeburg, after parting from the Wordsworths at Hamburg, 262-
278;
learning the German language, 262, 263, 267, 268;
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