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LAB 3_VDP

This document outlines the instructions for Lab Work 3 focused on the layout of CMOS analog circuits using Electric VLSI software. It includes guidelines for report submission, task contributions, and specific steps for creating NMOS and PMOS transistors, as well as conducting design rule checks and network compliance checks. Additionally, it addresses post-laboratory questions related to layout techniques and design considerations.

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Glenn Virrey
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2 views

LAB 3_VDP

This document outlines the instructions for Lab Work 3 focused on the layout of CMOS analog circuits using Electric VLSI software. It includes guidelines for report submission, task contributions, and specific steps for creating NMOS and PMOS transistors, as well as conducting design rule checks and network compliance checks. Additionally, it addresses post-laboratory questions related to layout techniques and design considerations.

Uploaded by

Glenn Virrey
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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LAB WORK 3

Layout of CMOS Analog Circuits (Part 1)


Prepared by:
Engr. Angelito A. Silverio, Ph.D.
Directions:

1. Submit a softcopy of your group report in IEEE conference paper format into the Laboratory
Work 3 Submission bin in Blackboard.
2. Submit this group report individually.
3. Include a section on your report mentioning the task partitions/ contributions by each group
member.
4. Include in your report snapshots of the schematics as well as the relevant plots which are
asked in each procedure.
5. Provide a section in the report which answers the post-laboratory questions.
6. Do not forget to include references whenever you cited some relevant literature.

Grading:
SO5.4 – Task Partitions (10pts)
SO6.1 – Data Completeness (10pts)
SO6.2 – Discussion of Results (10pts)
SO6.3 - Conclusion and Post-Lab Questions (10pts)

Electric VLSI is a Java-based open-source software that permits a “full custom” IC Design flow
involving schematic capture, layout, design rule check and network compliance check. It also
incorporates a circuit simulator for pre- and post-layout performance verification. Its interface is
shown in the following figure.
The interface consists of two windows namely of the Main window and the messages window.
The Main window is where schematic and layout may be done as well as the corresponding
design verifications. Meanwhile, the messages window shows interactively the activities being
done and more importantly if there are errors/ design rule violations in layout as well as if there
is a mismatch between layout and schematic.

On the left side of the main window, there are three tabs namely: Layers, Explorer and
Components. The Layers tab allows you to select which layers are to be viewed particularly in
layout. The Explorer tab allows you to see the corresponding libraries and cells as well as if there
are errors/ violations in layout and in NCC. Finally, the Components tab allows you to select and
add the active (e.g. transistors) or passive devices (e.g. resistors, capacitors) into your circuit.

To begin using Electric, you are to firstly create a “library” which serves as the collection of your
schematic and layout designs. Then, you are to create a “cell” either a schematic or a layout cell.
If you created a schematic cell, the components tab will be showing component symbols;
whereas, if you created a layout cell, the components tab will be showing layout components
such as the layers and the basic active or passive devices. Please ensure that the file names of
both schematic and layout are the same. The following figure shows the explorer tab once you
created the respective layout and schematic cells.

The next step would be is to build the circuits. In schematic view, the components tab will appear
like the following figure. Here, an NMOS transistor has been added. The numbers shown refer to
the transistor’s Width and Length. You can modify the width and length by double clicking the
component or by going to Edit → Properties → Object Properties while the component is
selected. Please take note that in Electric, you do not need to add the suffix. Any numbers you
place are automatically in microns (micrometer).
In the layout view, the component tab will appear like the following figure. The node properties
window can be opened by double clicking the MOS transistor or by selecting MOS transistor and
going to Edit → Properties → Object Properties. Please note that the layout is pattern coded
where the green region is for the diffusion (e.g. drain, source), while the red region is for
polysilicon which is representative of the gate. Remember that whenever a polysilicon crosses a
diffusion, an MOS transistor is formed.

The next step is to run DRC which may be accessed in Tools → DRC → Check Hierarchically. If
there are rule violations, the Message window will show this. The error may also be accessed
on the Explorer tab as shown in the following figure. Meanwhile, you may double click each
error and you will be directed to its location in the layout enclosed by a red dashed box.
Once the error has been fixed, the next step is to compare the layout and the schematic using
the NCC tool. This may be accessed from Tools → NCC →Schematic and Layout Views of Cell in
Current Window. If there is a mismatch between the layout and the schematic, an error will be
flagged like the one shown below. The mismatched parameters are pointed out. For this error,
the size of the MOS transistor from the schematic and layout are not the same. The
corresponding mismatch may also be located in the layout by clicking the particular error flagged.

Part 1. Basic NMOS and PMOS Layout

1. Using Electric VLSI, build the schematic and layout of an NMOS and PMOS transistor with
an aspect ratio of 6u/6u and 12u/6u, respectively. Do not forget the respective bulks of
the NMOS and PMOS transistors. Provide labels. Show a snapshot of both the schematic
and layout views.
2. Ensure that there are no layout Design Rule violations by running the DRC. Show a
snapshot of the Electric Messages Tab upon running the DRC.
3. Ensure that the layout and schematic are the same by running the Network Compliance
Check (NCC). Show a snapshot of the Electric Messages Tab upon running the DRC.
4. Repeat steps 1 to 3 this time by building a “long channel length” NMOS transistor having
an aspect ratio of 3U/30U.

Part 2. MOS Multiplier and the Interdigitated Transistors


1. Using Electric VLSI, build the schematic and layout of an NMOS and PMOS transistor
with an aspect ratio of 15u/3u m=4 and 30u/3u m=4, respectively. Show a snapshot
ofboth the schematic and layout views.
2. Ensure that there are no layout Design Rule violations by running the DRC. Show a
snapshot of the Electric Messages Tab upon running the DRC.
3. Ensure that the layout and schematic are the same by running the Network Compliance
Check (NCC). Show a snapshot of the Electric Messages Tab upon running the DRC.
4. Build the schematic and layout of a simple NMOS current mirror with both transistors
having an aspect ratio of 6u/6u m=2. Use the interdigitation pattern: ABBA, where A and
B represents the gate areas of transistors MA and MB, respectively.

Post Lab Questions


1. What is the benefit of using interdigitated pattern in the layout of wide MOS
transistors?
2. What does serpentine layout mean?
3. Comment on the best effective way to create the bulk for the MOS transistors.

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