Scribd
Upload
3 views6 pages

LAB_6_MICRO-ELE1_AID

The document outlines the methodology for designing CMOS analog circuits using the gm/id and V* design approaches, emphasizing the limitations of the square law model in advanced technologies. It provides detailed instructions for a laboratory report, including tasks for group contributions, schematic snapshots, and post-laboratory questions. Additionally, it describes the steps for using the V* methodology to achieve specific design objectives for common source amplifiers while minimizing power dissipation.

Uploaded by

Glenn Virrey
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
3 views6 pages

LAB_6_MICRO-ELE1_AID

The document outlines the methodology for designing CMOS analog circuits using the gm/id and V* design approaches, emphasizing the limitations of the square law model in advanced technologies. It provides detailed instructions for a laboratory report, including tasks for group contributions, schematic snapshots, and post-laboratory questions. Additionally, it describes the steps for using the V* methodology to achieve specific design objectives for common source amplifiers while minimizing power dissipation.

Uploaded by

Glenn Virrey
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 6

LAB WORK 6

Gm/ID and V* Design Methodology


Prepared by: Engr. Angelito A. Silverio, Ph.D.

Directions:

1. Submit a softcopy of your group report in IEEE conference paper format into the Laboratory Work
6Submission bin in Blackboard.
2. Submit this group report individually.
3. Include a section on your report mentioning the task partitions/ contributions by each group
member.
4. Include in your report snapshots of the schematics as well as the relevant plots which are asked in
each procedure.
5. Provide a section in the report which answers the post-laboratory questions.
6. Do not forget to include references whenever you cited some relevant literature.

Grading:
SO5.4 – Task Partitions (10pts)
SO6.1 – Data Completeness (10pts)
SO6.2 – Discussion of Results (10pts)
SO6.3 - Conclusion and Post-Lab Questions (10pts)

The use of the square law equations for designing CMOS analog circuits do not totally predict the resulting
performance especially in very advanced CMOS process technologies. Such technologies do not readily
follow the square law model since more physical parameters are included in the model to account for the
second order effects brought about by technology scaling (reduction in feature size or minimum length).
In the standard square law equation given by:

There are interdependencies between parameters such as: transconductance factor KP is affected by the
width, whereas the channel length modulation factor λ is affected by the length. To go about this, the so-
called key parameters (e.g. Kp, gamma, lambda, VTH), are obtained from a series of graphs containing
variable widths, lengths and bias currents. Furthermore, such key parameters vary from one technology
node to another.

On top of the inaccuracy of using the square law approximation to predict circuit performance, we usually
need to have a so-called “figure of merit” between two parameters that don’t come together (e.g.
bandwidth and power dissipation). For such cases of scaling and figure of merit, we can instead use the
so-called “graphical approach” in designing our circuits. This approach is accomplished by the gm/id or its
spin-off, the V* methodology.

Gm/id is also called the “transconductance efficiency factor”. It is a measure of how much
transconductance (gm) you can obtain based on how much current you invest. The gm/id term is fairly
constant with the technology node and sizes as shown in the following figure:
The gm is a parameter that determines both your DC gain as well as the so-called gain-bandwidth “GBW”
(a.k.a. gain-bandwidth product). For the following common source amplifier the gain expression as well
as the gain bandwidth are as shown:

However, if we want a higher DC gain and GBW, we need to use a larger bias current to achieve a higher
gm. This will be an issue if we want to design the circuit so that it does not reasonably dissipate power. To
achieve this, we need to operate the MOS transistor in saturation which gives the highest achievable
bandwidth. But we need to design it so that it does not dissipate a lot of current. Here we can consider
the V* method. V* is given by:

VOV is also known as overdrive voltage and is just another term for VDSAT. By re-arranging:

𝑔𝑚 2
=
𝐼𝐷 𝑉𝑂𝑉
We can denote VOV as V* (for most cases, but not always), hence,

2𝐼𝐷
𝑉∗ =
𝑔𝑚

The value of V* usually affects the operating condition of the MOSFET:


a) 160 mV – 180 mV (weak inversion) large signal swing, high current efficiency
b) 200 mV to 250 mV (moderate inversion)
c) >= 300 mV (strong inversion) (high fT, lower device parasitics)

B.E. Boser, “Analog Design Using gm/Id and ft Metrics”, UC Berkeley, 2011

For your design, you may utilize the following test benches for obtaining your ID vs V* plots. For a defined
current (Id), find the corresponding width to reach ID(target) at V* = 200 mV. This V* value allows you to
have a wide bandwidth with reasonable power dissipation. This is a design parameter used almost
exclusively in sizing MOS transistors to operate in saturation. You may increase the width to reach the
target drain current when the resulting current is still below your target current; otherwise, decrease the
width.
After obtaining your transistor width, you need to determine the input DC voltage across the gate-source
of M1 which will bias it to saturation. With your knowledge of the output DC level, you can get this voltage
via the following test bench and plot:

In this test-bench, element E1 is a voltage-controlled voltage source (a.k.a. voltage amplifier) with a high
voltage gain (10,000). This circuit configuration forces the output DC level to be equal to the target DC
level while finding for the proper gate-source bias voltage.

In summary, the following are the steps for using the V* methodology:

The following details the V* Design Methodology steps:


1. Determine gm from design objectives (dynamic range, bandwidth…)
2. Pick L
- Short Channel à high fT (high speed)
- Long Channel à high intrinsic gain
3. Determine ID using
2𝐼
𝑉∗ = 𝐷 = 200𝑚𝑉 (approximately equal to V OV)
𝑔𝑚

4. Obtain W, based from iteration so that V* = 200 mV at the calculated ID


(takes care of short channel effects!)
5. Find the input DC voltage (a.k.a. the input common mode voltage)
Part 1:

Using the provided test bench, replicate the current density vs gm/id plot for both NMOS and PMOS.
Take a snapshot of the resulting graphs. Use widths from 1u to 100u at steps of 0.5u.

Part 2:

For your lab, design the following common source amplifier circuits to achieve the following
specifications at minimum power dissipation. Use V* Methodology.

AV = -20 V/V, B ≥ 20 MHz (Bandwidth), VDD = 1.8 V, VOUT = 0.9 V

Show in your report the corresponding V* plots as well as the AC analysis for the gain and phase. Show
also pertinent calculations.

(a) Common Source Amplifier with Resistive Load

(b) Common Source Amplifier with PMOS Current Source Load


For sizing your PMOS current source M2, you may use the following test bench:

You can utilize the target current as with the common source amplifier with resistor load. This time with
the known current you may proceed immediately with finding the PMOS width vs V* of 200 mV. The
corresponding bias current for the PMOS current source may be obtained similarly as what is done for the
NMOS.

Use AC analysis to show that the target differential gain and bandwidth has been achieved.

Post Laboratory Questions

1. What is the benefit of using gm/id or V* method as compared to the traditional square law -
based hand calculation?
2. Where will high or low gm/id will be used?
3. For designing MOS amplifiers, how will you choose the gm/id value?

You might also like