School of Engineering and Sciences (SEAS)

Department of
Electronics and Communication Engineering

DIGITAL ELECTRONICS

LABORATORY MANUAL
 Course Name Digital Electronics lab
Course Code CSE 207L

LIST OF EXPERIMENTS

S. No. Name of the Experiment Page No

1 Realization of Basic Logic Gates 1-6

2 Design of Code Converters (Binary to Gray) & (Gray to Binary) 7-8

3 Design of a) Half-Adder / Subtractor b) Full-Adder / Subtractor 9-11

4 Design of Multiplexers / De Multiplexer 12-14

5 Design of Decoder and Encoder/ BCD 7SSD 15-16

6 Design of Magnitude Comparator (2-bit) 17

7 Design and Verification of Flip-Flops using IC 18-20

8 Design of Johnson and Ring Counter 21-22

9 Design of Synchronous Counter 23-24

10 Design of Decade counter 74LS90 25-26

Design of Universal Shift Register
(Serial to Parallel, Parallel to Serial, Serial to Serial and Parallel to
11 Parallel Converters) 27-29

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 DIGITAL ELECTRONICS

DO’S AND DON’TS

DO’S:-

1. Students should carry observation notes and records completed in all aspects.
2. Correct specifications of the equipment have to be mentioned in the circuit diagram
3. Students should be aware of the operation of equipment’s.
4. Students should take care of the laboratory equipment’s/ Instruments.
5. After completing the connections, students should get the circuits verified by the Lab
Instructor

6. The readings/waveforms must be shown to the concerned faculty for verification.

7. Students should ensure that all switches are in the OFF position to remove the
connections before leaving the laboratory
8. All patch cords and chairs should be placed properly in their respective positions.

DON’Ts:-

1. Come late to the lab.

2. Make or remove the connections with power ON.
3. Switch ON the power supply without verification by the instructor.
4. Switch OFF the machine with load.
5. Leave the lab without the permission of the concerned faculty.

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 IC PIN DIAGRAMS:

AND GATE (7408) OR GATE (7432)

NOT GATE (7404) Ex-OR GATE (7486)

NAND GATE (7400) NOR GATE (7402)

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EX NOR GATE (74266) 3 INPUT AND GATE (7411)

3 INPUT NAND GATE (7410) D FLIPFLOP (7474)

JK FLIP FLOP (7476)

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 1. REALIZATION OF BASIC LOGIC GATES
AIM: To study about logic gates and verify their truth tables.

APPARATUS REQUIRED:

SL No. COMPONENT SPECIFICATION QTY

1. AND GATE IC 7408 1
2. OR GATE IC 7432 1
3. NOT GATE IC 7404 1
4. NAND GATE 2 I/P IC 7400 1
5. NOR GATE IC 7402 1
6. X-OR GATE IC 7486 1
7. IC TRAINER KIT - 1
8. PATCH CORD - As per Required

THEORY: Circuit that takes the logical decision and the process are called logic gates. Each gate has
one or more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are
known as universal gates. Basic gates form these gates.
AND GATE: The AND gate performs a logical multiplication commonly known as AND function. The
output is high when both the inputs are high. The output is low level when any one of the inputs is low.

OR GATE: The OR gate performs a logical addition commonly known as OR function. The output is
high when any one of the inputs is high. The output is low level when both the inputs are low.

NOT GATE: The NOT gate is called an inverter. The output is high when the input is low. The output
is low when the input is high.

NANDGATE: The NAND gate is a contraction of AND-NOT. The output is high when both inputs
are low and any one of the input is low .The output is low level when both inputs are high.

NOR GATE: The NOR gate is a contraction of OR-NOT. The output is high when both inputs are
low. The output is low when one or both inputs are high.

X-ORGATE: The output is high when any one of the inputs is high. The output is low when both the
inputs are low and both the inputs are high.

PROCEDURE:

(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.

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OR GATE:

NOT GATE:

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X-OR GATE :
SYMBOL: PIN DIAGRAM:

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CONCLUSION:

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 2. DESIGN OF CODE CONVERTORS
(BINARY TO GRAY) & (GRAY TO BINARYCONVERSION)

AIM: To design code converters and verify their truth tables

APPARATUS:
1. IC - 7486
2. Electronic circuit designer
3. Connecting patch chords

CIRCUIT DIAGRAM:

BINARY TO GRAY:

GRAY TO BINARY:

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THEORY:
WHAT IS BINARY CODE: -
BINARY code is a way of representing the text or the data generated by the computers and
other devices. In binary coding the text or the data is represented in a stream of bits of 1's and
0's. that isweighted as 8,4,2,1. so for forming 7, you just need 111.similar computation
for other decimal
numbers.
WHAT ARE GRAY CODES: -
GRAY CODES are non-weighted codes, that is they can’t be provided a weight to calculate
their equivalent in decimal. Gray codes are often called reflected binary code; the reason is
clear if you compare the column of gray code with the binary code. gray Code is a symbolic
representation of discrete information. Codes are of different types. Gray Code is one of the
most important codes. It is a non-weighted code which belongs to a class of codes called
minimum change codes. In this codes while traversing from one step to another step only one
bit in the code group changes. In caseof Gray Code two adjacent code numbers differs from
each other by only one bit. The idea of it can be cleared from the table given below.

PROCEDURE: -

1. The circuit connections are made as shown in fig.

2. Pin (14) is connected to +Vcc and Pin (7) to ground.
3. In the case of binary to gray conversion, the inputs B0, B1, B2 and B3 are given at
respectivepins and outputs G0, G1, G2, G3 are taken for all the 16 combinations of the
input.
4. In the case of gray to binary conversion, the inputs G0, G1, G2 and G3 are given at
Respective Pins and outputs B0, B1, B2, and B3 are taken for all the 16 combinations of
inputs.
5. The values of the outputs are tabulated.

CONCLUSION:

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 3. DESIGN OF COMBINATIONAL LOGIC CIRCUITS

AIM: To design and construct a) Half-adder, Half- subtractor,

b) Full-adder, Full- subtractor.

APPARATUS:

1. IC’s - 7486, 7432, 7408, 7400

2. Electronic Circuit Designer
3. Connecting patch chords.

THEORY:
HALF ADDER:
A half adder has two inputs for the two bits to be added and two outputs one from the sum
‘ S’ and other from the carry ‘ c’ into the higher adder position. Above circuit is called as a carry
signal from the addition of the less significant bits sum from the X-OR Gate the carry out from the
AND gate.
FULL ADDER:
A full adder is a combinational circuit that forms the arithmetic sum of input; it consists of
three inputs and two outputs. A full adder is useful to add three bits at a time but a half adder
cannot do so. In full adder sum output will be taken from X-OR Gate, carry output will be taken
from OR Gate.
HALF SUBTRACTOR:
The half subtractor is constructed using X-OR and AND Gate. The half subtractor has two
input and two outputs. The outputs are difference and borrow. The difference can be applied using
X-OR Gate, borrow output can be implemented using an AND Gate and an inverter.
FULL SUBTRACTOR:
The full subtractor is a combination of X-OR, AND, OR, NOT Gates. In a full subtractor
the logic circuit should have three inputs and two outputs. The two half subtractor put together
gives a full subtractor. The first half subtractor will be C and A B. The output will be difference
output of full subtractor. The expression AB assembles the borrow outputof the half subtractor and
the second term is the inverted difference output of first X-OR.

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 CIRCUIT DIAGRAM:
Half adder:

Half Subtractor:

Full Adder:

FULL SUBTRACTOR:

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 PROCEDURE:

1. Verify the gates.

2. Make the connections as per the circuit diagram.
3. Switch on VCC and apply various combinations of input according to truth table.
4. Note down the output readings for half/full adder and half/full subtractor, Sum/difference and
thecarry/borrow bit for different combinations of inputs verify their truth tables.

CONCLUSION:

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 4. DESIGN OF MULTIPLEXER & DE MULTIPLEXER
AIM: To design Multiplexer and De multiplexer and verify their truth tables

APPARATUS: 1. IC 74153, IC 74139 etc

2. Electronic circuit designer kit
3. Connecting patch chords
THEORY:
Multiplexer means many to one. A multiplexer is a circuit with many inputs but only one output. By
using control signals (select lines) we can select any input to the output. Multiplexer is also called as data
selector because the output bit depends on the input data bit that is selected. The general idea about the
multiplexing the circuit has N input signals, M control signals and 1 output signal.8 X 1 Multiplexer has 8
input signals and one output signal, three data control or select lines. These data control lines are nothing
but 3-bit binary code on the data control signal inputs which will allow the data on the corresponding data
input to pass through to the data output.

CIRCUIT DIAGRAM:

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PROCEDURE: - (IC 74153)

1. The Pin [16] is connected to + Vcc.

2. Pin [8] is connected to ground.
3. The inputs are applied either to ‘A’ input or ‘B’ input.
4. If MUX ‘A’ has to be initialized, Ea is made low and if MUX ‘B’ has to be initialized, Eb is made
low.
5. Based on the selection lines one of the inputs will be selected at the output and thus verify the
truth table

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PROCEDURE: - (IC 74139)

1. The inputs are applied to either ‘a’ input or ‘b’ input

2. The demux is activated by making Ea low and Eb low.
3. Verify the truth table .

PROCEDURE:
1. Check all the components for their working.
2. Insert the appropriate IC into the IC base
3. Make connections as shown in the circuit diagram.
4. Verify the Truth Table and observe the outputs.

CONCLUSION:

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 5. DESIGNS OF DECODER AND ENCODER
AIM: To verify the operation of 8 to 3 line Encoder and 3 to 8 Decoder using IC 74138 and 74148.

APPARATUS:

Equipment : Digital IC Trainer Kit

Discrete Components : IC 74148, IC 74138, RESISTOR 100Ω, LEDS.

ENCODER:
A decoder is a multiple-input, multiple-output logic circuit that converts coded inputs into coded
outputs, where the input and output codes are different. Binary Decoder has n inputs and 2n outputs
also called asn-to-2n decoder.
DECODER:
Decoder is the combinational circuit which contains ‘n’ input lines to 2n output lines. The decoder is
used for converting the binary code into the octal code. The IC74138 is the 3 x 8 decoder which
contains three inputs and 8 outputs and also three enables out of them two are active low and one is
active high.
Decoders are used in the circuit where required to get more outputs than that of the inputs.

Circuit Diagram:

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PROCEDURE:

1.Connect as per the diagram given.

2.Apply Vcc to pin 16 and Gnd to pin 8 of the 74138.
3.Connect the inputs to pins 1,2,3.
4.Connect pin 4,5 to gnd and 6 to Vcc.
5.Similarly when E2 is HIGH all the outputs are high irrespective of the inputs.
6.When E3 is low all the inputs are high irrespective of E1 and E2 = high.
7.If E1 and E2 are low and E3 is high the inputs are low, the outputs 0o will be low with allthe other
outputs are low.
9. Change the inputs we get 1 and outputs as low and all the other outputs as high.
10. Note BCD output from the IC 74148 as the input to 74138.
11. Compare the truth table.
12. Note outputs of decoder truth table.

CONCLUSION:

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 6. DESIGN OF MAGNITUDE COMPARATOR

AIM: To verify the truth table of one bit and four bit comparators using logic Gates and IC 7485

APPARATUS:

Equipment : Digital IC Trainer Kit

Discrete Components : IC 7485

PROCEDURE:

1. Connect the circuit as shown in fig. Feed the 4-bit binary words A0, A1, A2, A3 and B0, B1, B2,
B3 from the logic input switches.
2. Pin 3 of IC 7485 should be at logic 1 to enable compare operation.
3. Observe the output A>B, A=B, and A<B on logic indicators. The outputs must be 1 or 0
respectively.
4. Repeat the steps 1 ,2 and 3 for various inputs A0, A1, A2, A3 and B0, B1, B2, B3 andobserve the
outputs at A>B , A=B and A<B .

CONCLUSION:

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7. VERIFICATION OF TRUTH TABLES OF FLIP FLOPS USING IC
AIM: To design and construct basic flip-flops R-S,J-K, D, T flip-flops using IC and Verify the truth
tables
APPARATUS:

1. IC’s-7400, 7474, 7476.

2. NI ELVIS II+
3. Connecting wires
4. Function Generator Probe

THEORY:
• RS FLIP-FLOP:
There are two inputs to the flip-flop defined as R and S. When I/Ps R=0 and S=0 then
O/P remains unchanged. When I/Ps R=0andS=1 the flip-flop is switches to the stable
state where O/P is 1i.e. SET. The I/P condition is R=1 and S=0 the flip-flop is switched
to the stable statewhere O/P is 0i.e. RESET. The I/P condition is R=1 and S=1 the flip-
flop is switched to the stable state where O/P is forbidden.

• JK FLIP-FLOP:
For purpose of counting, the JK flip-flop is the ideal element to use. The variable J and K
are called control I/Ps because they determine what the flip-flop does when a positive edge
arrives. When J and K are both0s, both AND gates are disabled and Q retain sits last value.

• D FLIP–FLOP:
This kind of flip-flop prevents the value of D from reaching the Q output until clock pulses
occur. When the clock is low, both AND gates are disabled D can change value without
affecting the value of Q. On the other hand, when the clock is high, both AND gates are
enabled. In this case, Q is forced to equal the value of D. When the clock a gain goes low, Q
retains or stores the last value of D.A D flip-flop is a b is table circuit whose D input is
transferred to the output after a clock pulse is received.

• T FLIP-FLOP:
The T or" toggle" flip flop changes its output on each clock edge, giving an output which
is half the frequency of the signal to the T input. It is useful for constructing binary counters,
frequencydividers, and general binary addition devices. It can be made from a J-K flip-flop
by tying both of its inputs high.

CIRCUIT DIAGRAM:

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 JK FLIP FLOP USING IC:
Truth table:

T FLIP FLOP USING IC:

Truth table:

DFLIP FLOP USING IC 7474:-

TRUTH TABLE:

CLK D Q ̅
𝑸
1 0 0 1
1 1 1 0

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PROCEDURE:

1. Connect the Flip-flop circuits as shown above.

2. Apply different combinations of inputs and observe the outputs.
3. Apply clock pulse by using function generator with
Frequency -100Hz,
Amplitude- 5V p-p,
DC offset -2.48V
Pulse -square

RESULT:

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8. DESIGN OF RING AND JOHNSON COUNTERS USING FLIP-FLOPS
AIM: To design Ring counter and Johnson counter and verify their truth tables

APPARATUS:
1. IC’s - 7404, 7402, 7400
2. Electronic circuit designer
3. Connecting patch chords
THEORY:
A ring counter is a circular shift register which is initiated such that only one of its flip-flops is
the state one while others are in their zero states.
A ring counter is a shift register (a cascade connection of flip-flops) with the output of the last
one connected to the input of the first, that is, in a ring. Typically, a pattern consisting of a single
bit is circulated so the state repeats every n clock cycles if n flip-flops are used.
A Johnson counter (or switch-tail ring counter, twisted ring counter, walking ring counter,or
Mobius counter) is a modified ring counter, where the output from the last stage is inverted and
fed back as input to the first stage. The register cycles through a sequence of bit-patterns, whose
length is equal to twice the length of the shift register, continuing indefinitely. These counters
find specialist applications, including those similar to the decade counter, digital-to- analog
conversion, etc. They can be implemented easily using D- or JK-type flip-flops.

CIRCUIT DIAGRAM:

RING COUNTER:

TRUTH TABLE:
CLK Q2 Q1 Q0
0 1 0 0
1 0 1 0
2 0 0 1

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 JOHNSON COUNTER:

TRUTH TABLE:

CLK Q2 Q1 Q0
0 0 0 0
1 1 0 0
2 1 1 0
3 1 1 1
4 0 1 1
5 0 0 1

PROCEDURE:
1. Connections are made as per the circuit diagram

2. Switch on the power supply.

3. Apply clock pulses and note the outputs after each clock pulse

CONCLUSION:

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 9. DESIGN OF SYNCHRONOUS COUNTER
AIM: To design and construct of 3-bit Synchronous counter.

APPARATUS:

1. IC -7408,7476
2. Electronic circuit designer
3. Connecting patch chords
4. Function generator probe.

THEORY:

A counter in which each flip-flop is triggered by the output goes to previous flip flop. As all the flip-
flops does not change state simultaneously in a synchronous counter, spike occur at the output. To
avoid this, strobe pulse is required. Because of the propagation delay the operating speed of
asynchronous counter is low. This problem can be solved by triggering all the flip-flops in synchronous
with the clock signal and such counters are called synchronous counters.

CIRCUIT DIAGRAM:

3-bit Synchronous Counter QA QB QC

Vcc

2 7 2
Q
PRE
PRE
PRE

15 9 11 7408 4 15
4 Q Q

7476 1 7476
1Hz
1 7476 6

Q
Q Q 16
16 14 14
CLR

CLR

12 10
CLR

Vcc 5 13 Vcc 5 13
3 GND 8 3

Vcc

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TRUTH TABLE:

PROCEDURE:

1. Function Generator settings:

Frequency: 1Hz, Amplitude: 5V (p-p), DC offset: 2V, Clock Pulse- square wave

2. Connections are made as per the circuit diagram.

3. Connect pin no.7 to ground and pin no.14 to Vcc of IC 7408.

4. Similarly Connect pin no.13 to ground and pin no.5 to Vcc of IC 7476 as per the circuit diagram.

5. Switch on the power supply.

6. Apply clock pulses and note the outputs after each clock pulse and note done the outputs.

CONCLUSION:

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 10. DECADE COUNTER 74LS90

AIM: To construct and verify the working of a single digit decade counter using IC 7490.

APPARATUS: 1) IC 7490 Decade counters kit

2) Connecting patch cards.

THEORY:
A decade counter is one that counts in decimal digits, rather than binary. A decade counter may have each
(that is, it may count in binary-coded decimal, as the 7490 integrated circuit did) or other binary
encodings. "A decade counter is a binary counter that is designed to count to 1010 (decimal 10). An
ordinary four-stage counter can be easily modified to a decade counter by adding a NAND gate as in the
schematic to the right. Notice that FF2 and FF4 provide the inputs to the NAND gate. The NAND gate
outputs are connected to the CLR input of each of the FFs." A decade counter is one that counts in
decimal digits, rather than binary. It counts from 0 to 9 and then resets to zero. The counter output can be
set to zero by pulsing the reset line low. The count then increments on each clock pulse until it reaches
1001 (decimal 9). When it increments to 1010 (decimal 10) both inputs of the NAND gate go high. The
result is that the NAND output goes low, and resets the counter to zero. D going low can be a CARRY
OUT signal, indicating that there has been a count of ten.

CIRCUIT DIAGRAM: MOD 6 COUNTERS:

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TRUTH TABLE:-

PROCEDURE:
1. Wire the circuit diagram shown in figure 1.
2. Connect the 1Hz clock to pin CPO.(14)
3. Connect the reset terminals (MR1 & MR2) to high and set terminals (MS1 &
MS2) to zero and observe the output.
4. Now connect set and reset inputs to zero and observe the outputs.
5. Record the counter states for each clock pulse.
6. Design mod 6 counter using IC 7490 as shown in fig 2.
7. Record the counter states for each clock pulse.
8. Now Construct decade counter using J – K F/F’s and record the counter states.

CONCLUSION:

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 11. DESIGN OF SHIFT REGISTER
AIM: To study shift register using IC 7495 in all its modes i.e. SIPO/SISO,PISO/PIPO.

APPARATUS:

1. IC’s - 7495
2. Electronic Circuit Designer
3. Connecting patch chords.

THEORY:

In digital circuits, a shift register is a cascade of flip flops, sharing the same clock, in which the output of
each flip-flop is connected to the "data" input of the next flip-flop in the chain, resulting in a circuit that
shifts by one position the "bit array" stored in it, "shifting in" the data present at its input and 'shifting out'
the last bit in the array, at each transition of the clock input.
More generally, a shift register may be multidimensional, such that its "data in" and stage outputs are
themselves bit arrays; this is implemented simply by running several shift registers of the same bit- length
in parallel.
Shift registers can have both parallel and serial inputs and outputs. These are often configured as "serial-
in, parallel-out" (SIPO) or as "parallel-in, serial-out" (PISO). There are also types that have both serial
and parallel input and types with serial and parallel output. There are also "bidirectional" shift registers
which allow shifting in both directions: L→R or R→L. The serial input and last output of a shift register
can also be connected to create a "circular shift register". One register is PIPO (parallel in parallel out),
which is very fast, within single clock pulse, it is giving output

CIRCUIT DIAGRAM:

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PISO:-

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PROCEDURE:

Serial In Parallel Out(SIPO):

1. Connections are made as per circuit diagram.

2. Apply the data at serial i/p
3. Apply one clock pulse at clock 1 (Right Shift) observe this data at QA.
4. Apply the next data at serial i/p.
5. Apply one clock pulse at clock 2, observe that the data on QA will shift to QB and the new data applied
will appear at QA.
6. Repeat steps 2 and 3 till all the 4 bits data are entered oneby one into the shift register.

Serial In Serial Out (SISO):

1. Connections are made as per circuit diagram.

2. Load the shift register with 4 bits of data one by one serially.
3. At the end of 4th clock pulse the first data ‘d0’ appears at QD.
4. Apply another clock pulse; the second data ‘d1’ appears at QD.
5. Apply another clock pulse; the third data appears at QD.
6. Application of next clock pulse will enable the 4th data ‘d3’ to appear at QD. Thus the dataapplied serially at the
input comes out serially at QD

Parallel In Serial out (PISO):

1. Connections are made as per circuit diagram.

2. Apply the desired 4 bit data at A, B, C and D.
3. Keeping the mode control M=1 apply one clock pulse. The data applied at A, B,C and D will appear at
QA, QB, QC and QD respectively.
4. Now mode control M=0. Apply clock pulses one by one and observe the Data comingout serially at QD.

Parallel In Parallel Out (PIPO):

1. Connections are made as per circuit diagram.

2. Apply the 4 bit data at A, B, C and D.
3. Apply one clock pulse at Clock 2 (Note: Mode control M=1).
4. The 4 bit data at A, B, C and D appears at QA, QB, QC and QD respectively.

CONCLUSION:

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