UNIT III SYNCHRONOUS SEQUENTIAL

CIRCUITS

Latches, Flip flops – SR, JK, T, D, Master/Slave FF, Triggering of FF, Analysis and
design of clocked sequential circuits – Design - Moore/Mealy models, state
minimization, state assignment,lock - out condition circuit implementation - Counters,
Ripple Counters, Ring Counters, Shift registers, Universal Shift Register. Model
Development: Designing of rolling display/real time clock

100
Sequential Circuits

 Combinational
◼ The outputs depend only on the current input values
◼ It uses only logic gates
 Sequential
◼ The outputs depend on the current and past input values
◼ It uses logic gates and storage elements
◼ Example
 Vending machine
◼ They are referred as finite state machines since they have
a finite number of states
Sequential Circuits
101
Block Diagram

 Memory elements can store binary information

◼ This information at any given time determines the
state of the circuit at that time

Sequential Circuits
102
Sequential Circuit Types

 Synchronous
◼ The circuit behavior is determined by the signals at
discrete instants of time
◼ The memory elements are affected only at discrete
instants of time
◼ A clock is used for synchronization
 Memory elements are affected only with the arrival of a
clock pulse
 If memory elements use clock pulses in their inputs, the
circuit is called
◼ Clocked sequential circuit
Sequential Circuits
103
Sequential Circuit Types

 ASynchronous
◼ The circuit behavior is determined by the signals at
any instant of time
◼ It is also affected by the order the inputs change

Sequential Circuits
104
Clock

 It emits a series of pulses with a precise pulse

width and precise interval between consecutive
pulses
 Timing interval between the corresponding edges
of two consecutive pulses is known as the clock
cycle time, or period

Sequential Circuits
105
Flip-Flops

 They are memory elements

 They can store binary information

Sequential Circuits
106
Flip-Flops

 Can keep a binary state until an input signal to

switch the state is received
 There are different types of flip-flops depending
on the number of inputs and how the inputs affect
the binary state

Sequential Circuits
107
Latches

 The most basic flip-flops

◼ They operate with signal levels
 The flip-flops are constructed from latches
 They are not useful for synchronous sequential
circuits
 They are useful for asynchronous sequential
circuits

Sequential Circuits
108
SR Latch with NOR

Sequential Circuits
109
SR Latch with NOR

S = set
R = reset
Q = 1, Q' = 0 = set state
Q = 0, Q' = 1 = reset state
S = 1, R = 1 = undefined,Q and Q' are set to 0
In normalconditions, avoid S = 1, R = 1

Sequential Circuits
110
SR Latch with NAND

Sequential Circuits
111
SR Latch with NAND

S = set
R = reset
Q = 0, Q' = 1 = set state
Q = 1, Q' = 0 = reset state
S = 0, R = 0 = undefined,Q and Q' are set to1
In normalconditions, avoid S = 0, R = 0

Sequential Circuits
112
SR Latch with Control Input

Sequential Circuits
113
D Latch

Sequential Circuits
114
Symbols for Latches

Sequential Circuits
115
Edge-Triggered J-K Flip-Flop

Q(t + 1) = JQ'+ K ' Q

Sequential Circuits
116
Excitation Table

Sequential Circuits
117
Edge-Triggered T Flip-Flop

T Q(t + 1)
0 Q(t )
Q(t + 1) = T  Q = TQ '+T ' Q
1 Q' (t )
Sequential Circuits
118
Excitation Table

Sequential Circuits
119
 Master-Slave J-K Flip-Flop

7-Oct-24
PJF - 120
Chapter 9: Sequential
Flip-Flop Problem

The change in the flip-flop output is determined by the

circuit frequency
S and/or R are permitted to change while C = 1
◼ Suppose that Q = 0 and S=1, R=0 -> S=0, R=0
 The master latch sets to 1
 A 1 is transferred to the slave
◼ Suppose that Q = 0 and S=1, R=0 -> S=0, R=0 -> S=0, R=1 -> S=0,
R=0
 The master latch sets and then resets
 A 0 is transferred to the slave

7-Oct-24
PJF - 121
Chapter 9: Sequential
Flip-Flop Solution
Use edge-triggering instead of master-slave
An edge-triggered flip-flop ignores the pulse while it is at a constant level and
triggers only during a transition of the clock signal
Edge-triggered flip-flops can be built directly at the electronic circuit level, or
A master-slave D flip-flop which also exhibits edge-triggered behavior can be
used.

7-Oct-24
PJF - 122
Chapter 9: Sequential
Edge-triggered Flip-Flops

 Attach level-triggered D to level-triggered SR, using

complemented clocks.
 D-Type Positive Edge-Triggered Flip-Flop:

7-Oct-24
PJF - 123
Chapter 9: Sequential
Introduction: Counters
▪ Counters are circuits that cycle through a
specified number of states.
▪ Two types of counters:
❖ synchronous (parallel) counters
❖ asynchronous (ripple) counters

▪ Ripple counters allow some flip-flop outputs

to be used as a source of clock for other flip-
flops.
▪ Synchronous counters apply the same clock to
all flip-flops.
Introduction: Counters
124
Design Procedure

 Derive a state diagram

 Reduce the number of states
 Assign binary values to the states
 Obtain binary coded state table
 Choose the type of flip-flop to be used
 Derive simplified flip-flop input equations and
output equations
 Draw the logic diagram

Sequential Circuits
125
Synchronous (Parallel) Counters
▪ Synchronous (parallel) counters: the flip-flops are
clocked at the same time by a common clock pulse.
▪ We can design these counters using the sequential logic
design process
▪ Example: 2-bit synchronous binary counter (using T
flip-flops, or JK flip-flops with identical J,K inputs).

Synchronous (Parallel) Counters

126
Synchronous (Parallel) Counters
Qn Qn+1 J K T
00 01 0 0
0 1
1 0
11 10
1 1

Present Next Flip-flop

state state inputs
A1 A0 A1+ A0+
0 0 0 1
0 1 1 0
1 0 1 1
1 1 0 0
127
Synchronous (Parallel) Counters

▪ Example: 2-bit synchronous binary counter (using T flip-

flops, or JK flip-flops with identical J,K inputs).

Present Next Flip-flop

state state inputs
A1 A0 A1+ A0+ TA1 TA0
0 0 0 1 0 1
0 1 1 0 1 1
1 0 1 1 0 1
1 1 0 0 1 1 1

A0 A1
J J
TA1 = A0 Q Q
TA0 = 1 C C
Q' Q'
K K

CLK

Synchronous (Parallel) Counters

128
Synchronous (Parallel) Counters

Present Next Flip-flop

state state inputs
A2 A1 A0 A 2+ A1+ A0+
0 0 0 0 0 1
0 0 1 0 1 0
0 1 0 0 1 1
0 1 1 1 0 0
1 0 0 1 0 1
1 0 1 1 1 0
1 1 0 1 1 1
1 1 1 0 0 0

129
Synchronous (Parallel) Counters

▪ Example: 3-bit synchronous binary counter (using T

flip-flops, or JK flip-flops with identical J, K inputs).

Present Next Flip-flop

state state inputs
A2 A1 A0 A2+ A1+ A0+ TA2 TA1 TA0
0 0 0 0 0 1 0 0 1
0 0 1 0 1 0 0 1 1
0 1 0 0 1 1 0 0 1
0 1 1 1 0 0 1 1 1
1 0 0 1 0 1 0 0 1
1 0 1 1 1 0 0 1 1
1 1 0 1 1 1 0 0 1
1 1 1 0 0 0 1 1 1
A1 A1 A1

1 1 1 1 1 1 1
A2 1 A2 1 1 A2 1 1 1 1

A0 A0 A0
TA2 = A1.A0 TA1 = A0 TA0 = 1

Synchronous (Parallel) Counters

130
Synchronous (Parallel) Counters

▪ Example: 3-bit synchronous binary counter

(cont’d).
TA2 = A1.A0 TA1 = A0 TA0 = 1

A2 A1 A0

Q Q Q

J K J K J K

CP
1

Synchronous (Parallel) Counters

131
Synchronous (Parallel) Counters

▪ Note that in a binary counter, the nth bit

(shown underlined) is always complemented
whenever
011…11 → 100…00
or 111…11 → 000…00
▪ Hence, Xn is complemented whenever
Xn-1Xn-2 ... X1X0 = 11…11.
▪ As a result, if T flip-flops are used, then
TXn = Xn-1 . Xn-2 . ... . X1 . X0
Synchronous (Parallel) Counters
132
Synchronous (Parallel) Counters

▪ Example: 4-bit synchronous binary counter.

TA3 = A2 . A1 . A0
TA2 = A1 . A0
TA1 = A0
TA0 = 1
A1.A0
1 A2.A1.A0

A0 A1 A2 A3
J J J J
Q Q Q Q
C C C C
Q' Q' Q' Q'
K K K K

CLK

Synchronous (Parallel) Counters

133
Synchronous Binary Counters:
J-K Flip Flop Design of a 4-bit Binary Up Counter

134
 Synchronous Binary Counters
J-K Flip Flop Design of a Binary Up Counter (cont.)

135
 Synchronous Binary Counters
J-K Flip Flop Design of a Binary Up Counter (cont.)

136
 Synchronous Binary Counters
J-K Flip Flop Design of a Binary Up Counter (cont.)

137
 Synchronous Binary Counters
J-K Flip Flop Design of a Binary Up Counter (cont.)
logic 1 JQ0 = 1
J Q0
KQ0 = 1
C
K

JQ1 = Q0
Q1 KQ1 = Q0
J
C
K

JQ2 = Q0 Q1
J Q2 KQ2 = Q0 Q1
C
K

JQ3 = Q0 Q1 Q2
J Q3 KQ3 = Q0 Q1 Q2
C
K
20
CLK
Synchronous (Parallel) Counters

▪ Example: Synchronous decade/BCD counter.

Clock pulse Q3 Q2 Q1 Q0
Initially 0 0 0 0 T0 = 1
1 0 0 0 1 T1 = Q3'.Q0
2 0 0 1 0 T2 = Q1.Q0
3 0 0 1 1
T3 = Q2.Q1.Q0 + Q3.Q0
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 (recycle) 0 0 0 0

Synchronous (Parallel) Counters

139
Synchronous (Parallel) Counters

▪ Example: Synchronous decade/BCD counter

(cont’d).
T0 = 1
T1 = Q3'.Q0
T2 = Q1.Q0
T3 = Q2.Q1.Q0 + Q3.Q0

Q0

1 T T Q1 T Q2 T Q3
Q Q Q Q
C C C C
Q' Q' Q' Q'

CLK

Synchronous (Parallel) Counters

140
Up/Down Synchronous Counters

▪ Up/down synchronous counter: a

bidirectional counter that is capable of
counting either up or down.
▪ An input (control) line Up/Down (or simply
Up) specifies the direction of counting.
❖ Up/Down = 1 → Count upward
❖ Up/Down = 0 → Count downward

Up/Down Synchronous Counters

141
Up/Down Synchronous Counters

▪ Example: A 3-bit up/down synchronous binary

counter.
Clock pulse Up Q2 Q1 Q0 Down
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1

TQ0 = 1 Up counter Down counter

TQ1 = (Q0.Up) + (Q0'.Up' ) TQ0 = 1 TQ0 = 1
TQ2 = ( Q0.Q1.Up ) + (Q0'. Q1'. Up' ) TQ1 = Q0 TQ1 = Q0’
TQ2 = Q0.Q1 TQ2 = Q0’.Q1’

Up/Down Synchronous Counters

142
Up/Down Synchronous Counters

▪ Example: A 3-bit up/down synchronous binary

counter (cont’d).
TQ0 = 1
TQ1 = (Q0.Up) + (Q0'.Up' )
TQ2 = ( Q0.Q1.Up ) + (Q0'. Q1'. Up' )

Q0 Q1

1 T T T Q2
Q Q Q
Up C C C
Q Q Q
' ' '

CLK

Up/Down Synchronous Counters

143
Designing Synchronous Counters

▪ Example: A 3-bit Gray

code counter (using JK 000
001
100
flip-flops).
101 011

111 010
110
Present Next Flip-flop
state state inputs
Q2 Q1 Q0 Q2 Q1+
+
Q0+ JQ2 KQ2 JQ1 KQ1 JQ0 KQ0
0 0 0 0 0 1 0 X 0 X 1 X
0 0 1 0 1 1 0 X 1 X X 0
0 1 0 1 1 0 1 X X 0 0 X
0 1 1 0 1 0 0 X X 0 X 1
1 0 0 0 0 0 X 1 0 X 0 X
1 0 1 1 0 0 X 0 0 X X 1
1 1 0 1 1 1 X 0 X 0 1 X
1 1 1 1 0 1 X 0 X 1 X 0

Designing Synchronous Counters

144
Designing Synchronous Counters

▪ 3-bit Gray code counter: flip-flop inputs.

Q1Q0 Q1Q0 Q1Q0
Q2 Q2 00 01 11 10 Q2 00 01 11 10
00 01 11 10
0 0 1 X X 0 1 X X
1
1 X X X X 1 X X 1 X X 1

JQ2 = Q1.Q0' JQ1 = Q2'.Q0 JQ0 = Q2.Q1 + Q2'.Q1'

= (Q2  Q1)'
Q1Q0 Q1Q0 Q1Q0
Q2 00 01 11 10 Q2 00 01 11 10 Q2 00 01 11 10
0 X X X X 0 X X 0 X 1 X
1 1 1 X X 1 1 X 1 X
KQ2 = Q1'.Q0' KQ1 = Q2.Q0 KQ0 = Q2.Q1' + Q2'.Q1
= Q2  Q1

Designing Synchronous Counters

145
Designing Synchronous Counters

▪ 3-bit Gray code counter: logic diagram.

JQ2 = Q1.Q0' JQ1 = Q2'.Q0 JQ0 = (Q2  Q1)'
KQ2 = Q1'.Q0' KQ1 = Q2.Q0 KQ0 = Q2  Q1

Q0 Q1 Q2
J Q J Q J Q

C C C
Q1' Q2'
K Q' K Q' K Q'

Q0'

CLK

Designing Synchronous Counters

146
Up/Down Synchronous Counters

▪ Up/down synchronous counter: a

bidirectional counter that is capable of
counting either up or down.
▪ An input (control) line Up/Down (or simply
Up) specifies the direction of counting.
❖ Up/Down = 1 → Count upward
❖ Up/Down = 0 → Count downward

Up/Down Synchronous Counters

147
Up/Down Synchronous Counters

▪ Example: A 3-bit up/down synchronous binary

counter.
Clock pulse Up Q2 Q1 Q0 Down
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1

TQ0 = 1 Up counter Down counter

TQ1 = (Q0.Up) + (Q0'.Up' ) TQ0 = 1 TQ0 = 1
TQ2 = ( Q0.Q1.Up ) + (Q0'. Q1'. Up' ) TQ1 = Q0 TQ1 = Q0’
TQ2 = Q0.Q1 TQ2 = Q0’.Q1’

Up/Down Synchronous Counters

148
Up/Down Synchronous Counters

▪ Example: A 3-bit up/down synchronous binary

counter (cont’d).
TQ0 = 1
TQ1 = (Q0.Up) + (Q0'.Up' )
TQ2 = ( Q0.Q1.Up ) + (Q0'. Q1'. Up' )

Q0 Q1

Q2
1 T Q T Q T Q
Up C C C
Q' Q' Q'

CLK

Up/Down Synchronous Counters

149
Asynchronous (Ripple) Counters
▪ Example: 2-bit ripple binary counter.
▪ Output of one flip-flop is connected to the clock input of
the next more-significant flip-flop.
HIGH

J Q0 J Q1

CLK C C
Q0
K K

FF0 FF1

CLK 1 2 3 4

Q0 Timing diagram
00 → 01 → 10 → 11 → 00 ...
Q0 0 1 0 1 0

Q1 0 0 1 1 0

Asynchronous (Ripple) Counters

150
Asynchronous (Ripple) Counters
▪ Example: 3-bit ripple binary counter.
HIGH

J Q0 J Q1 J Q2

CLK C C C
Q0 Q1
K K K

FF0 FF1 FF2

CLK 1 2 3 4 5 6 7 8

Q0 0 1 0 1 0 1 0 1 0

Q1 0 0 1 1 0 0 1 1 0

Q2 0 0 0 0 1 1 1 1 0

Recycles back to 0

Asynchronous (Ripple) Counters

151
Asynchronous (Ripple) Counters
▪ Propagation delays in an asynchronous (ripple-clocked)
binary counter.
▪ If the accumulated delay is greater than the clock pulse,
some counter states may be misrepresented!

CLK 1 2 3 4

Q0

Q1

Q2
tPHL (CLK to Q0) tPHL (CLK to Q0)
tPLH (Q0 to Q1) tPHL (Q0 to Q1)
tPLH
(CLK to Q0) tPLH (Q1 to Q2)

Asynchronous (Ripple) Counters

152
Asynchronous (Ripple) Counters
▪ Example: 4-bit ripple binary counter (negative-edge
triggered).
HIGH

Q0 Q1 Q2 Q3
J J J J

CLK C C C C
K K K K

FF0 FF1 FF2 FF3

CLK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Q0

Q1

Q2

Q3

Asynchronous (Ripple) Counters

153
 n
Asyn. Counters with MOD no. < 2
▪ States may be skipped resulting in a truncated sequence.
▪ Technique: force counter to recycle before going through
all of the states in the binary sequence.
▪ Example: Given the following circuit, determine the
counting sequence (and hence the modulus no.)

C B A
Q J Q J Q J

All J, K CLK CLK CLK

inputs are Q K Q K Q K
1 (HIGH). CLR CLR CLR

B
C

Asynchronous Counters with MOD number <

154
2^n
 n
Asyn. Counters with MOD no. < 2

▪ Example (cont’d):
C B A
Q J Q J Q J
All J, K CLK CLK CLK
inputs Q K Q K Q K
CLR CLR CLR
are 1
(HIGH). B
C

1 2 3 4 5 6 7 8 9 10 11 12
Clock MOD-6 counter
A produced by
clearing (a MOD-8
B
binary counter)
C when count of six
NAND 1 (110) occurs.
Output 0

Asynchronous Counters with MOD number <

155
2^n
 n
Asyn. Counters with MOD no. < 2
▪ Example (cont’d): Counting sequence of circuit (in CBA
order).
1 2 3 4 5 6 7 8 9 10 11 12
Clock
A
B 0 1 0 1 0 1 0 1
0 0 1 1 0 0 0 0
C
NAND 1 0 0 0 0 1 1 0 0
Output 0

111 000
Temporary 001
state
Counter is a MOD-6
110 010 counter.

101 011
100

Asynchronous Counters with MOD number <

156
2^n
 n
Asyn. Counters with MOD no. < 2
▪ Decade counters (or BCD counters) are counters with
10 states (modulus-10) in their sequence. They are
commonly used in daily life (e.g.: utility meters,
odometers, etc.).
▪ Design an asynchronous decade counter.
(A.C)'

HIGH
D C B A
J Q J Q J Q J Q

CLK C C C C

K K K K
CLR CLR CLR CLR

Asynchronous Counters with MOD number <

157
2^n
 n
Asyn. Counters with MOD no. < 2
▪ Asynchronous decade/BCD counter (cont’d).
HIGH
D C B A
J Q J Q J Q J Q (A.C)'

CLK C C C C
K K K K
CLR CLR CLR CLR

1 2 3 4 5 6 7 8 9 10 11
Clock
D 0 1 0 1 0 1 0 1 0 1 0
C 0 0 1 1 0 0 1 1 0 0 0
B 0 0 0 0 1 1 1 1 0 0 0
A 0 0 0 0 0 0 0 0 1 1 0
NAND
output

Asynchronous Counters with MOD number <

158
2^n
Asynchronous Down Counters
▪ So far we are dealing with up counters. Down counters,
on the other hand, count downward from a maximum
value to zero, and repeat.
▪ Example: A 3-bit binary (MOD-23) down counter.
1

Q0 Q1 Q2
J J J
Q Q Q
CLK C C C 3-bit binary
Q' Q' Q' up counter
K K K

Q0 Q1 Q2
J Q
J
Q
J
Q
3-bit binary
CLK C C C
down counter
Q' Q' Q'
K K K

Asynchronous Down Counters

159
Ring Counters

▪ One flip-flop (stage) for each state in the

sequence.
▪ The output of the last stage is connected to the
D input of the first stage.
▪ An n-bit ring counter cycles through n states.
▪ No decoding gates are required, as there is an
output that corresponds to every state the
counter is in.

Ring Counters
160
Ring Counters
▪ Example: A 6-bit (MOD-6) ring counter.
PRE
Q0 Q1 Q2 Q3 Q4 Q5
D Q D Q D Q D Q D Q D Q

CLR
CLK

Clock Q0 Q1 Q2 Q3 Q4 Q5 100000
0 1 0 0 0 0 0
000001 010000
1 0 1 0 0 0 0
2 0 0 1 0 0 0
3 0 0 0 1 0 0 000010 001000
4 0 0 0 0 1 0
5 0 0 0 0 0 1 000100

Ring Counters
161
Johnson Counters

▪ The complement of the output of the last stage is

connected back to the D input of the first stage.
▪ Also called the twisted-ring counter.
▪ Require fewer flip-flops than ring counters but
more flip-flops than binary counters.
▪ An n-bit Johnson counter cycles through 2n
states.
▪ Require more decoding circuitry than ring
counter but less than binary counters.

Johnson Counters
162
Johnson Counters
▪ Example: A 4-bit (MOD-8) Johnson counter.
Q0 Q1 Q2
D Q D Q D Q D Q

Q'
Q3'
CLR
CLK

Clock Q0 Q1 Q2 Q3 0000
0 0 0 0 0
0001 1000
1 1 0 0 0
2 1 1 0 0
3 1 1 1 0 0011 1100
4 1 1 1 1
5 0 1 1 1 0111 1110
6 0 0 1 1
7 0 0 0 1 1111

Johnson Counters
163
Shift Registers

▪ Another function of a register, besides

storage, is to provide for data movements.
▪ Each stage (flip-flop) in a shift register
represents one bit of storage, and the shifting
capability of a register permits the movement
of data from stage to stage within the register,
or into or out of the register upon application
of clock pulses.

Shift Registers
164
Shift Registers

▪ Basic data movement in shift registers (four

bits are used for illustration).
Data in Data out Data out Data in

(a) Serial in/shift right/serial out (b) Serial in/shift left/serial out

Data in Data in
Data in

Data out
Data out
(c) Parallel in/serial out (d) Serial in/parallel out
Data out
(e) Parallel in /
parallel out

(f) Rotate right (g) Rotate left

Shift Registers
165
Serial In/Serial Out Shift Registers

▪ Accepts data serially – one bit at a time – and

also produces output serially.

Serial data Q0 Q1 Q2 Q3 Serial data

input D Q D Q D Q D Q output
C C C C

CLK

Serial In/Serial Out Shift Registers

166
Serial In/Serial Out Shift Registers

▪ Application: Serial transfer of data from one

register to another.
SI SO SI SO
Shift register A Shift register B

Clock CP
Shift control

Clock

Shift Wordtime
control

CP
T1 T2 T3 T4

Serial In/Serial Out Shift Registers

167
Serial In/Serial Out Shift Registers

▪ Serial-transfer example.
Timing Pulse Shift register A Shift register B Serial output of B
Initial value 1 0 1 1 0 0 1 0 0
After T1 1 1 0 1 1 0 0 1 1
After T2 1 1 1 0 1 1 0 0 0
After T3 0 1 1 1 0 1 1 0 0
After T4 1 0 1 1 1 0 1 1 1

Serial In/Serial Out Shift Registers

168
Serial In/Parallel Out Shift Registers
▪ Accepts data serially.
▪ Outputs of all stages are available simultaneously.

Data input D Q D Q D Q D Q

C C C C

CLK

Q0 Q1 Q2 Q3

Data input D SRG 4

Logic symbol
CLK C

Q0 Q1 Q2 Q3

Serial In/Parallel Out Shift Registers

169
Parallel In/Serial Out Shift Registers

▪ Bits are entered simultaneously, but output is

serial.
Data input

D0 D1 D2 D3
SHIFT/LOAD

Serial
D Q D Q D Q D Q data
Q0 Q1 Q2 Q3 out
C C C C

SHIFT.Q0 + SHIFT'.D1
CLK

Parallel In/Serial Out Shift Registers

170
Parallel In/Serial Out Shift Registers

▪ Bits are entered simultaneously, but output is

serial.
Data in

D0 D1 D2 D3

SHIFT/LOAD SRG 4
Serial data out
CLK C

Logic symbol

Parallel In/Serial Out Shift Registers

171
Parallel In/Parallel Out Shift Registers

▪ Simultaneous input and output of all data bits.

Parallel data inputs

D0 D1 D2 D3

D Q D Q D Q D Q
C C C C

CLK

Q0 Q1 Q2 Q3

Parallel data outputs

Parallel In/Parallel Out Shift Registers

172
Bidirectional Shift Registers

▪ Data can be shifted either left or right, using a

control line RIGHT/LEFT (or simply RIGHT)
to indicate the direction.
RIGHT/LEFT

Serial
data in

RIGHT.Q0 +
RIGHT'.Q2 D Q D Q D Q D Q Q3
Q1 Q2
C C C C

Q0
CLK
Bidirectional Shift Registers
173
Bidirectional Shift Registers
▪ 4-bit bidirectional shift register with parallel load.
Parallel outputs

A4 A3 A2 A1

Q Q Q Q
Clear
D D D D

CLK

s1 4x1 4x1 4x1 4x1

s0 MUX MUX MUX MUX
3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0

Serial input
for shift- Serial input
right for shift-left
I4 I3 I2 I1

Parallel inputs
Bidirectional Shift Registers
174
Bidirectional Shift Registers

▪ 4-bit bidirectional shift register with parallel load.

Mode Control
s1 s0 Register Operation
0 0 No change
0 1 Shift right
1 0 Shift left
1 1 Parallel load

Bidirectional Shift Registers

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The Mealy Model
 The inputs dominate our design.
 An input determines the next state
 The outputs are determined during the transitions
 Mealy machines tend to have fewer states
The Moore Model
 The design is determined from the states themselves.
 Actions are performed on entry to a state
 In mixed-state machines, states with entry actions are called
Moore states
 The machine will enter a state, do the entry action and then wait
for inputs
 Moore machines tend to have more states
State Diagram
00/0, 01/1 10/0, 01/0

Mealy Machine
10/0
A B
00/1

00 10
10 01
Moore Machine A0/0 B/0
10
01 00
00

A1/1
01
State Equations

A state equation shows

the next state as a
function of the current
state and inputs

A(t + 1) = A(t ) x(t ) + B(t ) x(t )

B(t + 1) = A' (t ) x(t )
y(t ) = A(t ) + B(t )x' (t )

A(t + 1) = Ax + Bx
B(t + 1) = A' x
y = ( A + B) x'
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State Table

A(t + 1) = A(t ) x(t ) + B(t ) x(t )

B(t + 1) = A' (t ) x(t )
y(t ) = A(t ) + B(t )x' (t )

A(t + 1) = Ax + Bx
B(t + 1) = A' x
y = ( A + B) x'
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State Diagram

Sequential Circuits
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Analysis with D Flip-Flops

DA = A  x  y
A(t + 1) = A  x  y
Sequential Circuits
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Design Procedure

 Derive a state diagram

 Reduce the number of states
 Assign binary values to the states
 Obtain binary coded state table
 Choose the type of flip-flop to be used
 Derive simplified flip-flop input equations and
output equations
 Draw the logic diagram

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State Reduction

 Reduce the number of states but keep the input-

output requirements
 Reducing the number of states may reduce the
number of flip-flops
◼ If there are n flip-flops, there are 2^n states
 If you have two circuits that produce the same
output sequence for any given input sequence, the
two circuits are equivalent
◼ They may replace each other

Sequential Circuits
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State Reduction Example

Find the states for which the

next states and outputs are
the same

Sequential Circuits
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Example (Cont.)

In the next
state, g is
replaced with e

In the next
state, f is
replaced with d

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Example (Cont.)

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State Assignment

 You need to assign binary values for each state so

that they can be implemented
 You need to use enough number of bits to cover
all the states

Sequential Circuits
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State Assignments

Sequential Circuits
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Design Procedure

 Derive a state diagram

 Reduce the number of states
 Assign binary values to the states
 Obtain binary coded state table
 Choose the type of flip-flop to be used
 Derive simplified flip-flop input equations and
output equations
 Draw the logic diagram

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190
Example

 Design a circuit (with D flip-flops) that detects three

or more consecutive 1’s in a string of bits coming
through an input line

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191
Example (Cont.)

A(t + 1) = DA ( A, B, x) =  (3,5,7)
B(t + 1) = DB ( A, B, x) =  (1,5,7)
y( A, B, x) =  (6,7)
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Example (Cont.)

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Example (Cont.)

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194
Example

◆ Design a circuit (with JK flip-flops) that detects

three or more consecutive 1’s in a string of bits
coming through an input line

Sequential Circuits
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Example (Cont.)

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Example (Cont.)

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Example (Cont.)

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