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Lab Manual 10 (2)

The lab focuses on understanding and designing synchronous sequential circuits using Verilog, specifically latches and flip-flops. It explains the differences between latches and flip-flops, detailing the operation of SR and JK flip-flops. The tasks involve implementing these flip-flops in Verilog, writing test benches, and analyzing their timing waveforms and schematic diagrams.

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10 views

Lab Manual 10 (2)

The lab focuses on understanding and designing synchronous sequential circuits using Verilog, specifically latches and flip-flops. It explains the differences between latches and flip-flops, detailing the operation of SR and JK flip-flops. The tasks involve implementing these flip-flops in Verilog, writing test benches, and analyzing their timing waveforms and schematic diagrams.

Uploaded by

Mary
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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LAB # 10: Sequential Circuits (FLIP-FLOPS)

Lab Objectives:
The main objective of this lab is to understand how the synchronous sequential circuits works
and to design them using Verilog.

Sequential Circuits:
A Sequential circuit produces an output based on current input and previous input
variables. That means sequential circuits include memory elements that can store binary
information. That binary information defines the state of the sequential circuit at that time. A
latch capable of storing one bit of information.

Latch:
Latches are basic storage elements that operate with signal levels (Level-Triggered).
Latches are useful for the design of the asynchronous sequential circuit.
SR LATCH USING NAND GATE

SR LATCH USING NOR GATE

SR Flip Flop:
A Flip-Flop will have an extra clock signal, that means it is Edge-triggered, in contrast with
a latch. The main function of the flip-flop is to store the binary values.

JK FLIP FLOP:
A J-K flip-flop is nothing more than an S-R flip-flop with an added layer of feedback. This
feedback selectively enables one of the two set/reset inputs so that they cannot both carry an
active signal to the multivibrator circuit, thus eliminating the invalid condition.
Different ways of Modeling Clock input in Test bench (Xillinx):

FIRST:

Begin

clk = 1’b0;

end

always #10 clk = ~clk;

SECOND:

Begin

clk= 1’b0;

forever #10 clk = clk

end

THIRD:

Begin

clk= 1’b0;

repeat(50)

#10 clk = ~clk;

End

Tasks:
1. Implement SR flip flop using Verilog. Write Test bench and analyze the timing waveform
and Schematic Diagram
2. Implement JK flip flop in Verilog. Write Test bench and analyze the timing waveform
and Schematic Diagram.

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