VLSI PROJECT TITLES 2024-2025

PROJECT
PROJECT NAME DOMAIN APPLICATION
CODE
PANVLSI1 Statistical Analysis of 5T SRAM Cell for Low DESIGNING
Power and Less Area SRAM Based Cache Memory + Low Power.
Memory for IoT Applications.
PANVLSI2 Implementation of 32-Bit Complex Floating-Point SIMULATION
Multiplier Using Vedic Multiplier, Array Multiplier
High Speed + DSP
and Combined integer and floating-point Multiplier
(CIFM).
PANVLSI3 SIMULATION
Hardware Efficient 2-Parallel and 3-Parallel Even DSP +
Length FIR Filters Using FFA. Communication.
PANVLSI4 DESIGNING
6T-SRAM Design to Optimize Delay Using Finfet
Memory
Technology.
PANVLSI5 SIMULATION
Review on FIR Filters Using Different Adders
DSP + ALU
and Multipliers Based on Vedic Mathematics.
PANVLSI6 DESIGNING
Quantum-dot Cellular Automata: An Efficient
Low power + High speed
and Adroit Alternate to CMOS Technology
PANVLSI7 Design of an Area Efficient Quantum Dot DESIGNING
Cellular Automata Based Full Adder Cell Having QCA Application
Low Latency.
PANVLSI8 SIMULATION
Approximate Ripple Carry and Carry Lookahead
High speed Application
Adders – A Comparative Analysis.
PANVLSI9 SIMULATION
Efficient Squaring Circuit Design using Vedic
DSP Application
Mathematics Principles and Parallel Prefix Adders.
PANVLSI10 DESIGNING
Design of an Efficient Seven Input Majority
QCA Application
Voter Gate for Quantum Dot Cellular Automata.
PANVLSI11 Design and Implementation of FIR Filter using SIMULATION
High order compressor based multiplier and three DSP Application
input adder.
PANVLSI12 SIMULATION
Design and verification of vending machine using
Real time Application
Verilog and system Verilog.
PANVLSI13 DESIGNING
Performance evaluation of 6T, 7T, 8T, and 9T
Low power Application
SRAM cell topologiesat 22 nm technology Node.
PANVLSI14 Design and verification of UART serial SIMULATION
communication modulebased on Verilog and OFF chip Application
system Verilog.
PANVLSI15 SIMULATION
Design and verification of APB memory using
OFF chip Application
Verilog and system Verilog.
PANVLSI16 SIMULATION
Design and verification of SPI protocol using
OFF chip Application
Verilog and system Verilog.
PANVLSI17 SIMULATION
Design and verification of I2C protocol using
OFF chip Application
Verilog and system Verilog.
PANVLSI18 SIMULATION
Design and verification of Interrupt controller using
ON chip Application
Verilog and system Verilog.
PANVLSI19 Design and verification of Asynchronous FIFO SIMULATION
Synchronization
using Verilog and
Application
system Verilog.
PANVLSI20 Design and verification of car parking management SIMULATION
system using Real time Application
Verilog and system Verilog.
PANVLSI21 Design and verification of Traffic light controller SIMULATION
with IR sensor Real time Application
using Verilog and system Verilog.
PANVLSI22 Design and verification High Speed 32-bit Vedic SIMULATION
multiplier using High speed Application
Verilog and system Verilog.
PANVLSI23 Design and verification Asynchronous read and SIMULATION
Memory
write memory
Application
using Verilog and system Verilog.
PANVLSI24 Efficient and implementation of Reduced Precision SIMULATION
Deep learning
Redundancy
Application
(RPR)Multiply and Accumulate (MAC).
PANVLSI25 Design and implementation FIR filter using SIMULATION
Verilog and system DSP Application
Verilog.
PANVLSI26 Approximate multiplier design using Novel SIMULATION
Dual-stage DSP Application
4:2compressors.
PANVLSI27 Performance evaluation of Distributed Arithmetic SIMULATION
based High speed + DSP
MAC Structures for DSP Applications.
PANVLSI28 Design and Evaluation of a FIR Filter DESIGNING
Using Hybrid Adders and Vedic High speed +Filter
Multipliers - based on CMOS using Application

micro wind.
PANVLSI29 Performance Analysis of 32-Bit Vedic SIMULATION
Multipliers for High speed
Different Adder Configurations.
PANVLSI30 Ultra Low power SRAM Cell for High- DESIGNING
Speed Memory Application
Applications using 45 nm CMOS Technology.
PANVLSI31 Design and Implementation of Health Care SIMULATION/
Monitoring HARDWARE Real time Application
System Using FPGA.
PANVLSI32 Agricultural Intelligence: The Role of FPGA in SIMULATION /
VLSI HARDWARE Real time Application
Design for Sustainable Farming Solutions.
PANVLSI33 Efficient 3-parallel polyphase odd length FIR SIMULATION
filter using Brent Kung adder and Booth High speed + Filter
multiplier for VLSI Application
applications.
PANVLSI34 Efficient Low-Area Design of XOR-MUX Full SIMULATION
Adders for DWT Application
Discrete Wavelet Transform.
PANVLSI35 Design of a Live Traffic Light Based Control SIMULATION/
System HARDWARE Real time Application
using FPGA.
PANVLSI36 Design and Analysis of Fault-Tolerant 1:2 DESIGNING
Demultiplexer Using Quantum-
QCA Application
Dot Cellular Automata Nano-
Technology.
PANVLSI37 FPGA Technology in VLSI Design: The SIMULATION/
Backbone of HARDWARE Real time Application
Advanced Smart Home Integration.
PANVLSI38 Low-power and high-speed 13T SRAM cell DESIGNING
using Low power + High speed
FinFETS.
PANVLSI39 Design and Implementation of an FPGA-Based SIMULATION /
Smart HARDWARE Real time Application
Parking System Using VLSI.
PANVLSI40 A Novel Design of Flip-Flop Circuits using DESIGNING
Quantum Dot QCA Application
Cellular Automata (QCA).
PANVLSI41 6Transistor SRAM Cell designed using 45nm DESIGNING
FinFET High speed
Technology.
PANVLSI42 Design of an Area Efficient Quantum Dot DESIGNING
Cellular
QCA Application
Automata Based Full Adder Cell Having Low
Latency.
PANVLSI43 Design and Analysis of Fault-Tolerant 1:2 DESIGNING
Demultiplexer Using Quantum-
QCA Application
Dot Cellular Automata Nano-
Technology.
PANVLSI44 Design of Efficient 1-bit Comparator in DESIGNING
Quantum dot QCA Application
Cellular Automata Nano-computing.
PANVLSI45 Quantum-dot Cellular Automata: An Efficient and DESIGNING
Adroit QCA Application
Alternate to CMOS Technology.
PANVLSI46 Design and Analysis of Fault-Tolerant 1:2 DESIGNING
Demultiplexer Using Quantum-
QCA Application
Dot Cellular Automata Nano-
Technology
PANVLSI47 Implementation of Boolean and Arithmetic DESIGNING
Functions with 8T
SRAM Cell for In- Memory Application
Memory Computation.
PANVLSI48 Energy-Efficient Multiplier Design: Evaluating DESIGNING
4x4 High speed Application
Circuits with 5-T, 8-T, and 2-T Logic.
PANVLSI49 Ultra Low power SRAM Cell for High Speed DESIGNING
Applications Memory Application
using 45nm CMOS Technology.
PANVLSI50 DESIGNING
Advanced Transmission Gate Logic for Enhanced Low power
Energy Efficiency in CMOS Full Adders. +High speed Application
PANVLSI51 Optimized Booth Multiplier Design:
SIMULATION
Approximate High speed Application
Compression Techniques in Verilog HDL.
PANVLSI52
SIMULATION Area Efficient +
Vedic Multiplier Using Carry look ahead adder.
High speed Application
PANVLSI53
High-Speed Hybrid-Logic Full Adder Using DESIGNING Low power + Area efficient
High- Performance 10-T XOR -XNOR Cell. Application
PANVLSI54 Design and Simulation of 16x16 Vedic Multiplier
SIMULATION
using High speed
Kogge-Stone Adder.
PANVLSI55 Statistical Analysis of 5T SRAM Cell for
DESIGNING
Low Power and Less Area SRAM Based
Memory Application
Cache Memory for IoT
Applications.
PANVLSI56 Design and Realization of Three-Operand Binary
SIMULATION
Adder
High speed + DSP
Using Kogge-Stone Adder in VLSI
Application
architecture.
PANVLSI57 Design Of Efficient BCD Adder with Five Input
SIMULATION
Majority DSP Application
Generators.
PANVLSI58 Design and Implementation of Vending machine
SIMULATION
both Real Time Application
Coin and Card using Verilog.
PANVLSI59 Optimized PMOS-Biased High-Efficiency Sense
DESIGNING
Amplifier Low power Application
for Minimal Power Usage.
PANVLSI60 Innovative Design and Evaluation of Near-
DESIGNING Low power +
Threshold 9T SRAM Using a One-Sided Schmitt
Trigger. Memory Application
PANVLSI61 Design and Synthesis of ALU using Reversible
SIMULATION
Logic for High speed Application
MAC Applications.
PANVLSI62 Design and Analysis of Modified Pre-Charge
DESIGNING
Sensing Memory Application
Circuit for STT-MRAM.
PANVLSI63 Design and Analysis of Ultra-Low Power
DESIGNING
Adiabatic
High speed Application
Computational Subsystem Based on Symmetric
Stacking.
PANVLSI64 FPGA Implementation of Area Efficient 16-Bit
SIMULATION /
Vedic DSP Application
HARDWARE
Multiplier Using Higher Order Compressors.
PANVLSI65
Low power , high performance 4-bit Vedic DESIGNING Low power +
multiplier in 45nm. High speed Application
PANVLSI66 High-Speed Vedic Multiplier Implementation
DESIGNING
Using DSP Application
Memristive and Speculative Adders.
PANVLSI67 Performance Evaluation of Adder Architectures for
SIMULATION High Speed + DSP
Vedic
Application
Multiplier Implementation.
PANVLSI68
High Speed and Power Efficient Vedic Multiplier SIMULATION / Low power + High speed
using Adders with MUX. DESIGNING Application
PANVLSI69
SIMULATION /
IOT based weather monitoring system using FPGA. Real time Application
HARDWARE
PANVLSI70
SIMULATION/
Object recognition using tiny YOLO in FPGA. HARDWARE Real time Application

PANVLSI71
SIMULATION/
Smart car parking system using spartan FPGA . HARDWARE Real time Application

PANVLSI72
SIMULATION/
Smart street light system using Spartan FPGA. HARDWARE Real time Application

PANVLSI73 Create a 32-bit Vedic Multiplier and Compare it

SIMULATION Low power
Against Other Multipliers Using A Carry Look-
Ahead Adder. +High speed Application
PANVLSI74 A low-cost IOT system for environmental
SIMULATION/
pollution HARDWARE Real time Application
monitoring using spartan FPGA.
PANVLSI75
SIMULATION/
Alcohol detection using Spartan FPGA. HARDWARE Real time Application

PANVLSI76 Design and Analysis of 16-bit Vedic Multiplier

SIMULATION
using High speed
RCA and CSLA.
PANVLSI77 Forest environment monitoring system using
SIMULATION/
spartan HARDWARE Real time Application
FPGA.
PANVLSI78 High-Speed Wallace Tree Multiplier Design and
SIMULATION High speed +
Analysis with Parallel Prefix Adders for VLSI Circuit
Applications. Low power Application
PANVLSI79 Agricultural Intelligence: The Role of FPGA in
SIMULATION/
VLSI HARDWARE Real time Application
Design for Sustainable Farming Solutions.
PANVLSI80 Design of Majority Logic (ML) Based
SIMULATION
Approximate Full Low power Application
Adders
PANVLSI81 Design implementation of health care monitoring
SIMULATION/
system HARDWARE Real time Application
using FPGA.
PANVLSI82
SIMULATION
Implementation of an Optimized AXI using Verilog. Real time Application

PANVLSI83
A Fully Static Topologically-Compressed 21- DESIGNING Area efficient +
Transistor Flip Flop With Power Saving. Low power Application
PANVLSI84 A Partially Static High Frequency
DESIGNING
18T Hybrid Topological Flip- Low power + Area efficient
Flop Design for Low Power Application Application

.
PANVLSI85 FPGA Technology in VLSI Design: The
SIMULATION/
Backbone of HARDWARE Real time Application
Advanced Smart Home Integration.
PANVLSI86 Efficient FIR Filter Design using Booth
SIMULATION High speed + Filter
Multiplier for
Application
VLSI Applications.
PANVLSI87 Design and Implementation of an FPGA-Based
SIMULATION/
Smart HARDWARE Real time Application
Parking System Using VLSI.
PANVLSI88
SIMULATION/
IOT based home automation using FPGA . HARDWARE Real time Application

PANVLSI89 Design of a Live Traffic Light Based Control

SIMULATION/
System HARDWARE Real time Application
using Xilinx.
PANVLSI90 IOT based gas leakage monitoring and
SIMULATION/
controlling for HARDWARE Real time Application
industrial application using FPGA.
PANVLSI91 Bluetooth Technology Based Wireless Type
SIMULATION/
Home HARDWARE Real time Application
Automation System.
PANVLSI92
SIMULATION/
IOT based health monitoring using FPGA. HARDWARE Real time Application

PANVLSI93
SIMULATION/
IOT based humidity measurement using FPGA. HARDWARE Real time Application

PANVLSI94
SIMULATION/
IOT based smart irrigation system using FPGA. HARDWARE Real time Application

PANVLSI95
SIMULATION/
IOT based smart water management using FPGA. HARDWARE Real time Application

PANVLSI96
SIMULATION/
IOT based street light monitoring using FPGA. HARDWARE Real time Application

PANVLSI97
SIMULATION/
CNN based object recognition using FPGA. HARDWARE Real time Application

PANVLSI98 Design of High Speed 8-bit Vedic Multiplier using

SIMULATION
Brent High speed Application
Kung Adders.
PANVLSI99
SIMULATION/
FPGA based patient monitoring system. HARDWARE Real time Application

PANVLSI100
SIMULATION/
Robotic ARM controller using spartan FPGA. HARDWARE Real time Application
PANVLSI101
SIMULATION/
Intelligent parking system design using FPGA. HARDWARE Real time Application

PANVLSI102
SIMULATION/
IOT based smart irrigation system using FPGA. HARDWARE Real time Application

PANVLSI103
SIMULATION/
IOT based security system using FPGA. HARDWARE Real time Application

PANVLSI104 Modified High Speed 32-bit Vedic Multiplier

SIMULATION
Design and DSP Application
Implementation.
PANVLSI105
IOT based water level monitoring system using SIMULATION/
HARDWARE Real time Application
FPGA.
PANVLSI106
SIMULATION/
IOT based Fire detection system using FPGA. HARDWARE Real time

PANVLSI107 Dynamic Reconfiguration of Truncated

SIMULATION
Multipliers for High speed Application
Energy-Conscious Design.
PANVLSI108 Design and Verification of 8-bit Hamming
SIMULATION
Encoder and High speed Application
Decoder.
PANVLSI109 Design and Analysis of Approximate Redundant
SIMULATION High speed +DSP
Binar
Application
Multipliers.
PANVLSI110 Efficient Implementations of Reduced
SIMULATION
Precision
High speed Application
Redundancy (RPR) Multiply and Accumulate
(MAC).
PANVLSI111 Design and Implementation of Filter using three
SIMULATION Filter + High speed
operand
Application
adders and high order compressors.
PANVLSI112
Specialized Applications: Implementing 5:2 SIMULATION High speed + Area efficient
Compression in Approximate Multipliers. Application
PANVLSI113 Industrial Plant safety Gas leakage detection using
SIMULATION/
Spartan HARDWARE Real time Application
FPGA .
PANVLSI114 Smart gardening and smart agriculture using
SIMULATION/
spartan -6 HARDWARE Real time Application
FPGA.
PANVLSI115 Smart water tank monitoring system using
SIMULATION/
spartan – 6 HARDWARE Real time Application
FPGA.
PANVLSI116
Area – Delay Efficient Binary adder using majority SIMULATION Area efficient +
gate generator using Verilog . High speed Application
PANVLSI117 Design and implementation of brent kung adder using
SIMULATION
carry High speed Application
select adder.
PANVLSI118
SIMULATION
Estimative Parallel Prefix Calculators. High speed Application

PANVLSI119
High speed low power multipliers based on reversible SIMULATION High speed + low power
logic methods. Application
PANVLSI120 An Energy Efficient High-Performance
DESIGNING
CMOS Low Power Application
Transmission Gate Full Adder Circuit.
PANVLSI121
High speed low power multipliers based on reversible SIMULATION High speed + low power
logic methods. Application
PANVLSI122
Design and Implementation of 4-bit and 8-bit DESIGNING High speed + low power
KSA in CMOS Technology. Application
PANVLSI123 A Partially Static High Frequency 18T Hybrid
DESIGNING High speed + low
Topological Flip-Flop Design for Low Power
Application. power Application
PANVLSI124
Reversible Logic Based 1-bit Comparator using DESIGNING
QCA Application
QCA.
PANVLSI125 Efficient Design of Vedic Square Calculator
DESIGNING
Using QCA Application
Quantum Dot Cellular Automata QCA.
PANVLSI126 Design and Implementation of a Fully Automated
SIMULATION/
Traffic HARDWARE Real time Application
Light Control System for a Four-Way Intersection
Using Verilog.
PANVLSI127 Design and Implementation of a Vending Machine
SIMULATION
Using Real time Application
Verilog HDL.
PANVLSI128 Performance Analysis of 4-Bit Multiplier using
DESIGNING
45nm Low power Application
Technology.
PANVLSI129
A Reliable Low Standby Power 10T SRAM Cell DESIGNING Low power + Memory
with Expanded Static Noise Margins. Application
PANVLSI130
DESIGNING
An Improved Performance Ring Oscillator Design. Low power Application

PANVLSI131
Design of Wallace Tree Multiplier using SIMULATION
High speed Application
Compressors.
PANVLSI132 Design a Low Power 8-bit Reversible Parallel
SIMULATION
Binary High speed Application
Adder Subtractor.
PANVLSI133
SIMULATION High speed + FIR
Partial Reconfigurable FIR Filter Design.
Application
PANVLSI134
Design and Estimation of Delay, Power and Area SIMULATION High speed + low
for Parallel Prefix Adders. power Application
PANVLSI135 Low Power Compressor Based MAC Architecture
SIMULATION High speed + DSP
for DSP
Application
Applications.
PANVLSI136 A 32-BIT MAC Unit Design Using Vedic
SIMULATION High speed + DSP
Multiplier and
Application
Reversible Logic Gate.
PANVLSI137
A Low-Power and High-Accuracy Approximate SIMULATION High speed + Low power
Multiplier With Reconfigurable Truncation. Application
PANVLSI138 Design and Performance Analysis of Various 32-bit
SIMULATION
Hybrid Adders DSP Application
using Verilog.
PANVLSI139 Implementation of Bio-metric based voting machine
SIMULATION
using Real time Application
Verilog.
PANVLSI140 Vedic-Based Squaring Circuit Using Parallel
SIMULATION
Prefix High speed Application
Adders.
PANVLSI141
A Dynamic Partial Reconfigurable FIR Filter SIMULATION
Filter Application
Architecture.
PANVLSI142 Design and Analysis of Approximate 4-2
SIMULATION
Compressors for High High speed Application
Accuracy Multipliers.
PANVLSI143 Design and synthesis of ALU using reversible
SIMULATION
logic for High speed Application
MAC Applications.
PANVLSI144 Hybrid Low Radix Encoding based Approximate
SIMULATION High speed + DSP
Booth
Application
multiplier.
PANVLSI145 Design and implementation of ROBA multiplier on
SIMULATION
MAC High speed Application
unit.
PANVLSI146 Design and verification of 8-bit Hamming
SIMULATION
Encoder and High speed Application
Decoder.
PANVLSI147
Design of DRAM sense amplifier using 45nm DESIGNING
Low power Application
Technology.
PANVLSI148 RoBA Multiplier: A Rounding-Based Approximate
SIMULATION
Multiplier for
DSP Application
High-Speed yet Energy-Efficient Digital Signal
Processing.
PANVLSI149 Design and analysis of High-speed Wallace tree
SIMULATION High speed + DSP
multiplier using
Application
parallel prefix adders for VLSI circuit designs.
PANVLSI150
Design of current mode 8T SRAM compute-in- DESIGNING High speed + Memory
Memory Macro for Processing Neural network. Application