EE6312-HOMEWORK III

Describe your reasoning for your design and calculations. Provide the simulations set-ups you used for this problem set and provide the necessary simulation results (operating point, plots, ...) to document your ndings. Make sure you provide sucient information, but not too much information either. The grade will depend both on the quality of the results as well as the quality of the succinct, but insightful description of your reasoning and calculations.

Problem 1
In this exercise you will investigate the various current mirror congurations and trade-os. Consider the transistor M1 shown in Fig1. We wish to dix the current in M1 to Iref . Due to the unilaterality of a transistor, feedback is required. Lets start analyzing the circuit without a gate-drain diode connection. When the current I1 through the transistor does not match with the desired current, Iref , the drain node voltage is undened (VD ). Consider the case Iref > I1 , drain voltage of M1 increases and gate voltage of M1 should be increased or source voltage of M1 should be decreased to match the two currents. Due to non-inverting nature of feedback, a unity gain amplier can be used to realize the feedback for simplicity. This collapses to the well known diode current mirror.

Vdd

Iref VD +

I1 M1

Figure 1: Basic Idea of Current Mirror

Consider the basic current mirror conguration shown in Fig2. For a xed VDS voltage, calculate the actual current at the drain of M2 by considering gds of the device. What is the error of mirrored current I Iref ( I = oIref 100)? This is the reason why high output impedance ( g1 ) is preferred. I ds Calculate output impedance of the cascode current mirror conguration shown in Fig3 in terms of small signal parameters. According to your calculations, size the transistors properly to get 1%, 10% accuracy from the cascode current mirror for VGS Vth = 200 mV , Iref = 1 mA and RL = 1 k.

Vdd

Iref Io M1 M2 + VDS

Figure 2: Basic Current Mirror Conguration

Vdd

Vdd

Iref M2 VG4

RL M4

M1

VG3

M3

Figure 3: Cascode Current Mirror Conguration

Plot the error of mirrored current vs VDS for the current mirrors in Fig2 and Fig3 by sweeping VDS and observe when the error is largest. The compliance is the smallest voltage at the output of the current source. Calculate the compliance of the realized current source. What is the minimum voltage required at the gate of M4 to have all devices in saturation? Compare it against the voltage used in Fig3. Fig 4 is one of the ways to realize this voltage at the gate of M4. What should be the voltage drop on R1 and calculate the required R1 value. Size the transistors properly to get 1% accuracy from the cascode current mirror for VGS Vth = 200 mV , Iref = 1 mA and RL = 1 k. Indicate the regions of operation of the transistors in Fig4. Generally we avoid using R1 because the voltage drop on R1 required will change with PVT variations. R1 is replaced by transistor realization shown in Fig5. Size the transistors properly to get 1% accuracy from the cascode current mirror for VGS Vth = 200 mV , Iref = 1 mA and RL = 1 k. Indicate the regions of operation of the transistors in Fig5. For highly scaled technologies, self-biased current mirror conguration shown in Fig5 isnt preferred because of threshold voltage dependence on L. Another current mirror conguration is shown in Fig6. Calculate the VGS and VDS of M3. To obtain the required VGS , keep the widths of all the transistors comparable and length the same, and size them properly to get 1% accuracy from this current mirror for VGS Vth = 200 mV for M1 and M2, Iref = 1 mA and RL = 1 k. Assume Iref is really small. 2

Vdd

Vdd

Iref R1 M2 VG4

RL

M4

M1

VG3

M3

Figure 4: Self Biased Current Mirror Conguration 1

Vdd

Vdd

Iref X M6 X/3 M5 X M1 X M2 X

RL

M4 X M3

Figure 5: Self Biased Current Mirror Conguration 2

Additional credit: Find out the smallest the gate voltages of M1 and M2 for cascode conguration. To obtain these gate voltages, we use a current mirror conguration shown in Fig8. Calculate the V1 and V2 shown in Fig8. Replace the Bias block with an appropriate transistor realization. Size the transistors properly to get 1% accuracy from this current mirror for VGS Vth = 200 mV , Iref = 1 mA and RL = 1 k.

Vdd

Vdd
ref

Vdd

Iref- Iref

RL

M3 M1 M2

Figure 6: Current Mirror Conguration 3

Vdd Vdd

Vdd

ref

RL

Iref- ref

V2

Bias

V1

M4 M3

M2 M1

Figure 7: Current Mirror Conguration 4

Problem 2
In this exercise you will investigate the basic dierential pair conguration, large signal analysis and small signal analysis. All device sizes are indicated in the following table and VSB = 0 V . Begin your analysis by assuming that M1 and M2 are perfectly matched. Parameter vs. Value Parameter Value W/L(M 1) 5 m/0.25 m W/L(M 2) 5 m/0.25 m W/L(M 0) 10 m/0.25 m W/L(M 3) 10 m/0.25 m Calculate the dierential mode gain (Ad ) for Fig8, Fig9 and Fig10. Provide simulation result for dierential mode gain (V1 = 0.5 < 0 , V2 = 0.5 < 0 for AC analysis). Now analyze the large signal characteristic of basic dierential pair. Plot I1 and I2 vs. Vin curve (I-V transfer characteristic) by sweeping dierential input voltage from 0 to VDD for Itail = 20 A, RL = 30 K

Vdd

Vdd

RL I1 M1 I2 M2

RL

V1 + Vin V2

Itail

Figure 8: Basic Dierential Pair Conguration with Ideal Current Source

and RS = 20 K. Calculate the required value of input voltage to switch current through just one of the input transistors.

Vdd

Vdd

RL I1 M1 I2 M2

RL

V1 + Vin V2

RS

Figure 9: Basic Dierential Pair Conguration with RS

Calculate and simulate the common mode gain (Acm ) for the following cases shown in Fig8, Fig9 and Fig10 (V1 = 1 < 0 , V2 = 1 < 0 for AC analysis). Common mode rejection ratio is dened as the tendency of the devices to reject the input signals common Ad to both inputs of a dierential pair and is given by CM RR = 20 log | Acm |. Calculate the CMRR for transistor realization of current source shown in Fig10. 5

Vdd

Vdd

Vdd

Iref

RL I1 M1 I2 M2

RL

V1 + Vin V2 M3

Itail M0

Figure 10: Basic Dierential Pair Conguration with Current Source Transistor

How do you increase the CMRR? Provide the circuit to increase CMRR considering your previous design background.