CE222

Computer Organization and

Assembly Language

Salman Ashraf

Faculty of Computer Science and Engineering

 INTERRUPT INITIATED INPUT/OUTPUT
- An alternative to program controlled I/O, open communication only
when some data has to be passed -> interrupt.

- The I/O interface, instead of CPU, monitors the I/O device.

- When the interface finds that the I/O device is ready for data transfer, it
generates an interrupt request to the CPU.

- Upon detecting an interrupt, CPU stops momentarily the task it is doing,

branches to the service routine to process the data transfer, and then
returns to the task it was performing.

• IEN (Interrupt-enable flip-flop)

- Can be set and cleared by instructions.

- When cleared, the computer cannot be interrupted.
 FLOWCHART FOR INTERRUPT CYCLE
(Instruction cycle) = 0 = 1 (Interrupt cycle)
R

Fetch and decode Store return address

instructions in location 0

Execute =0
IEN
instructions =1 Branch to location 1
=1
FGI
=0
=1 IEN  0
FGO R0
=0
R1

- The interrupt cycle is hardware implementation of a branch, and save

return address operation.
- At the beginning of the next instruction cycle, the instruction that is
read from memory is in address 1.
- At memory address 1, the programmer must store a branch instruction
that sends the control to an interrupt service routine.
- The instruction that returns the control to the original program is
indirect BUN 0.
REGISTER TRANSFER OPERATIONS IN INTERRUPT CYCLE
Memory
Before interrupt After interrupt cycle
0 0 256
1 0 BUN 1120 PC = 1 0 BUN 1120

255 Main 255 Main

PC = 256 Program 256 Program

1120 1120
I/O I/O
Program Program

1 BUN 0 1 BUN 0

- The control function for initiating the interrupt:

T0T1T2 (IEN)(FGI + FGO): R  1
- The interrupt cycle:
RT0: AR  0, TR  PC
RT1: M[AR]  TR, PC  0
RT2: PC  PC + 1, IEN  0, R  0, SC  0
- The fetch and decode phases of the normal instruction cycle must
be modified ➔ replace T0, T1, T2 with R'T0, R'T1, R’T2
COMPLETE COMPUTER DESCRIPTION: FLOWCHART
Start
SC  0, IEN  0, R  0

(Instruction Cycle) = 0 = 1 (Interrupt Cycle)

R
R’T0 RT0
AR  PC AR  0, TR  PC
R’T1 RT1
IR  M[AR], PC  PC + 1 M[AR]  TR, PC  0
R’T2 RT2
D0,...,D7  Decode IR(12-14), PC  PC + 1, IEN  0,
AR  IR(0-11), I  IR(15) R  0, SC  0

(Register or I/O) = 1 = 0 (Memory-reference)

D7

(I/O) = 1 = 0 (Register) (indirect) = 1 = 0 (direct)

I I

D7IT3 D7I’T3 D7’IT3 D7’I’T3

Execute Execute AR  M[AR] Nothing
I/O RR
Instruction Instruction D7’T4
Execute MR
Instruction
COMPLETE COMPUTER DESCRIPTION: MICROOPERATIONS
Fetch RT0: AR  PC
RT1: IR  M[AR], PC  PC + 1
Decode RT2: D0, ..., D7  Decode IR(12-14),
AR  IR(0-11), I  IR(15)
Indirect D7IT3: AR  M[AR]
Interrupt
T0T1T2(IEN)(FGI + FGO): R 1
RT0: AR  0, TR  PC
RT1: M[AR]  TR, PC  0
RT2: PC  PC + 1, IEN  0, R  0, SC  0
Memory-reference
AND D0T4: DR  M[AR]
D0T5: AC  AC  DR, SC  0
ADD D1T4: DR  M[AR]
D1T5: AC  AC + DR, E  Cout, SC  0
LDA D2T4: DR  M[AR]
D2T5: AC  DR, SC  0
STA D3T4: M[AR]  AC, SC  0
BUN D4T4: PC  AR, SC  0
BSA D5T4: M[AR]  PC, AR  AR + 1
D5T5: PC  AR, SC  0
ISZ D6T4: DR  M[AR]
D6T5: DR  DR + 1
D6T6: M[AR]  DR, if (DR = 0) then (PC  PC + 1),
SC  0
COMPLETE COMPUTER DESCRIPTION: MICROOPERATIONS
Register-reference
D7IT3 = r (Common to all register-reference instructions)
IR(i) = Bi (i = 0, 1, 2, ..., 11)
r: SC  0
CLA rB11: AC  0
CLE rB10: E0
CMA rB9: AC  AC
CME rB8: E  E
CIR rB7: AC  shr AC, AC(15)  E, E  AC(0)
CIL rB6: AC  shl AC, AC(0)  E, E  AC(15)
INC rB5: AC  AC + 1
SPA rB4: if (AC(15) = 0) then (PC  PC + 1)
SNA rB3: if (AC(15) = 1) then (PC  PC + 1)
SZA rB2: if (AC = 0) then (PC  PC + 1)
SZE rB1: if (E = 0) then (PC  PC + 1)
HLT rB0: S0

Input/Output D7IT3 = p (Common to all input/output instructions)

IR(i) = Bi (i = 6, 7, 8, ..., 11)
p: SC  0
INP pB11: AC(0-7)  INPR, FGI  0
OUT pB10: OUTR  AC(0-7), FGO  0
SKI pB9: if (FGI = 1) then (PC  PC + 1)
SKO pB8: if (FGO = 1) then (PC  PC + 1)
ION pB7: IEN  1
IOF pB6: IEN  0
THE VON NEUMANN ARCHITECTURE

General-purpose (von Neumann) Architecture

 STEPS OF COMPUTER DESIGN

• Designing
• CPU (ALU, CU)
• Bus structure

• Selecting
• Memory and Registers

• Defining
• Instruction format
• Instruction set
 DESIGN OF BASIC COMPUTER
– ALU

– Processor Registers

– Common Bus System

– Control Unit

– Memory

– Instruction Format

– Instruction Set

– Addressing Modes

– Memory, Register & I/O Instructions

– Interrupts

– Complete Computer Description

– Control of Registers, Flags and Bus

 DESIGN OF BASIC COMPUTER

Hardware Components of Basic Computer:

Memory Unit: 4096 x 16

Registers: AR, PC, DR, AC, IR, TR, OUTR, INPR and SC

Flip-Flops: I, S, E, R, IEN, FGI and FGO

Decoders: 3x8 op-code decoder

4x16 timing decoder

Common Bus: 16 bits

ALU: Connected to AC

Control logic gates

CONTROL UNIT OF BASIC COMPUTER
Instruction Register (IR)
15 14 13 12 11 - 0 Other inputs

3x8
decoder
7 6 5 4 3 2 10
D0
I Combinational
D7 Control Control
signals
logic

T15

T0

15 14 .... 2 1 0
4x16
decoder

4-bit Increment (INR)

sequence Clear (CLR)
counter
(SC) Clock
 FETCH and DECODE
T0: AR  PC (S2S1S0 = 010, T0 = 1)
Fetch and Decode T1: IR  M[AR], PC  PC + 1 (S2S1S0 = 111, T1 = 1)
T2: D0, . . . , D7  Decode IR(12-14), AR  IR(0-11), I  IR(15)

T1 S2

T0 S1 Bus
S0
Memory 7
unit
Address
Read

AR 1

LD

PC 2

INR

IR 5

LD
Clock
Common bus
 COMBINATIONAL CONTROL LOGIC

Generates signals:
• to generate control functions.
• to activate the common bus, memory, ALU, registers and flip-flops.
Control of Registers
 CONTROL OF AR

The control inputs of the registers are LD, INR and CLR.

To derive the gate structure associated with control inputs of AR,

scan all the register transfer statements that change the content
of AR.
COMPLETE COMPUTER DESCRIPTION: MICROOPERATIONS
Fetch RT0: AR  PC
RT1: IR  M[AR], PC  PC + 1
Decode RT2: D0, ..., D7  Decode IR(12-14),
AR  IR(0-11), I  IR(15)
Indirect D7IT3: AR  M[AR]
Interrupt
T0T1T2(IEN)(FGI + FGO): R 1
RT0: AR  0, TR  PC
RT1: M[AR]  TR, PC  0
RT2: PC  PC + 1, IEN  0, R  0, SC  0
Memory-reference
AND D0T4: DR  M[AR]
D0T5: AC  AC  DR, SC  0
ADD D1T4: DR  M[AR]
D1T5: AC  AC + DR, E  Cout, SC  0
LDA D2T4: DR  M[AR]
D2T5: AC  DR, SC  0
STA D3T4: M[AR]  AC, SC  0
BUN D4T4: PC  AR, SC  0
BSA D5T4: M[AR]  PC, AR  AR + 1
D5T5: PC  AR, SC  0
ISZ D6T4: DR  M[AR]
D6T5: DR  DR + 1
D6T6: M[AR]  DR, if (DR = 0) then (PC  PC + 1),
SC  0
COMPLETE COMPUTER DESCRIPTION: MICROOPERATIONS
Register-reference
D7IT3 = r (Common to all register-reference instructions)
IR(i) = Bi (i = 0, 1, 2, ..., 11)
r: SC  0
CLA rB11: AC  0
CLE rB10: E0
CMA rB9: AC  AC
CME rB8: E  E
CIR rB7: AC  shr AC, AC(15)  E, E  AC(0)
CIL rB6: AC  shl AC, AC(0)  E, E  AC(15)
INC rB5: AC  AC + 1
SPA rB4: if (AC(15) = 0) then (PC  PC + 1)
SNA rB3: if (AC(15) = 1) then (PC  PC + 1)
SZA rB2: if (AC = 0) then (PC  PC + 1)
SZE rB1: if (E = 0) then (PC  PC + 1)
HLT rB0: S0

Input/Output D7IT3 = p (Common to all input/output instructions)

IR(i) = Bi (i = 6, 7, 8, ..., 11)
p: SC  0
INP pB11: AC(0-7)  INPR, FGI  0
OUT pB10: OUTR  AC(0-7), FGO  0
SKI pB9: if (FGI = 1) then (PC  PC + 1)
SKO pB8: if (FGO = 1) then (PC  PC + 1)
ION pB7: IEN  1
IOF pB6: IEN  0
 CONTROL OF AR

R’T0: AR  PC LD(AR)
R’T2: AR  IR(0-11) LD(AR)
D7’IT3: AR  M[AR] LD(AR)
RT0: AR  0 CLR(AR)
D5T4: AR  AR + 1 INR(AR)

LD(AR) = R'T0 + R'T2 + D7'IT3

INR(AR) = D5T4
CLR(AR) = RT0

12 12
From bus AR To bus
D7’
I
LD Clock
T3
T2 INR
CLR
R
T0
D5
T4
Control of AC
COMMON BUS SYSTEM
S2
S1 Bus
S0
Memory unit 7
4096 x 16
Address
Write Read

AR 1

LD INR CLR

PC 2

LD INR CLR

DR 3

LD INR CLR

E
ALU AC 4

LD INR CLR

INPR
IR 5

LD
TR 6

LD INR CLR
OUTR
Clock
LD
16-bit common bus
CIRCUITS ASSOCIATED WITH AC

16

16 Adder and 16 16
From DR Logic AC
Circuit To bus
8
From INPR

LD INR CLR Clock

Control
of AC
COMPLETE COMPUTER DESCRIPTION: MICROOPERATIONS
Fetch RT0: AR  PC
RT1: IR  M[AR], PC  PC + 1
Decode RT2: D0, ..., D7  Decode IR(12-14),
AR  IR(0-11), I  IR(15)
Indirect D7IT3: AR  M[AR]
Interrupt
T0T1T2(IEN)(FGI + FGO): R 1
RT0: AR  0, TR  PC
RT1: M[AR]  TR, PC  0
RT2: PC  PC + 1, IEN  0, R  0, SC  0
Memory-reference
AND D0T4: DR  M[AR]
D0T5: AC  AC  DR, SC  0
ADD D1T4: DR  M[AR]
D1T5: AC  AC + DR, E  Cout, SC  0
LDA D2T4: DR  M[AR]
D2T5: AC  DR, SC  0
STA D3T4: M[AR]  AC, SC  0
BUN D4T4: PC  AR, SC  0
BSA D5T4: M[AR]  PC, AR  AR + 1
D5T5: PC  AR, SC  0
ISZ D6T4: DR  M[AR]
D6T5: DR  DR + 1
D6T6: M[AR]  DR, if (DR = 0) then (PC  PC + 1),
SC  0
COMPLETE COMPUTER DESCRIPTION: MICROOPERATIONS
Register-reference
D7IT3 = r (Common to all register-reference instructions)
IR(i) = Bi (i = 0, 1, 2, ..., 11)
r: SC  0
CLA rB11: AC  0
CLE rB10: E0
CMA rB9: AC  AC
CME rB8: E  E
CIR rB7: AC  shr AC, AC(15)  E, E  AC(0)
CIL rB6: AC  shl AC, AC(0)  E, E  AC(15)
INC rB5: AC  AC + 1
SPA rB4: if (AC(15) = 0) then (PC  PC + 1)
SNA rB3: if (AC(15) = 1) then (PC  PC + 1)
SZA rB2: if (AC = 0) then (PC  PC + 1)
SZE rB1: if (E = 0) then (PC  PC + 1)
HLT rB0: S0

Input/Output D7IT3 = p (Common to all input/output instructions)

IR(i) = Bi (i = 6, 7, 8, ..., 11)
p: SC  0
INP pB11: AC(0-7)  INPR, FGI  0
OUT pB10: OUTR  AC(0-7), FGO  0
SKI pB9: if (FGI = 1) then (PC  PC + 1)
SKO pB8: if (FGO = 1) then (PC  PC + 1)
ION pB7: IEN  1
IOF pB6: IEN  0
 CONTROL OF AC

All statements that change the content of AC:

D0T5: AC  AC  DR AND with DR

D1T5: AC  AC + DR ADD with DR
D2T5: AC  DR Transfer from DR
pB11: AC(0-7)  INPR Transfer from INPR
rB9: AC  AC Complement
rB7: AC  shr AC, AC(15)  E Shift right
rB6: AC  shl AC, AC(0)  E Shift left
rB5: AC  AC + 1 Increment
rB11: AC  0 Clear
 CONTROL OF AC
Gate structures for controlling
LD, INR and CLR of AC:

From Adder 16 16
To bus
and Logic Circuit AC
D0 AND LD Clock
T5 INR
D1 ADD CLR

D2 DR
T5
p INPR
B11
r COM
B9
SHR
B7
SHL
B6
INC
B5
CLR
B11
Control of Flags
COMPLETE COMPUTER DESCRIPTION: MICROOPERATIONS
Fetch RT0: AR  PC
RT1: IR  M[AR], PC  PC + 1
Decode RT2: D0, ..., D7  Decode IR(12-14),
AR  IR(0-11), I  IR(15)
Indirect D7IT3: AR  M[AR]
Interrupt
T0T1T2(IEN)(FGI + FGO): R 1
RT0: AR  0, TR  PC
RT1: M[AR]  TR, PC  0
RT2: PC  PC + 1, IEN  0, R  0, SC  0
Memory-reference
AND D0T4: DR  M[AR]
D0T5: AC  AC  DR, SC  0
ADD D1T4: DR  M[AR]
D1T5: AC  AC + DR, E  Cout, SC  0
LDA D2T4: DR  M[AR]
D2T5: AC  DR, SC  0
STA D3T4: M[AR]  AC, SC  0
BUN D4T4: PC  AR, SC  0
BSA D5T4: M[AR]  PC, AR  AR + 1
D5T5: PC  AR, SC  0
ISZ D6T4: DR  M[AR]
D6T5: DR  DR + 1
D6T6: M[AR]  DR, if (DR = 0) then (PC  PC + 1),
SC  0
COMPLETE COMPUTER DESCRIPTION: MICROOPERATIONS
Register-reference
D7IT3 = r (Common to all register-reference instructions)
IR(i) = Bi (i = 0, 1, 2, ..., 11)
r: SC  0
CLA rB11: AC  0
CLE rB10: E0
CMA rB9: AC  AC
CME rB8: E  E
CIR rB7: AC  shr AC, AC(15)  E, E  AC(0)
CIL rB6: AC  shl AC, AC(0)  E, E  AC(15)
INC rB5: AC  AC + 1
SPA rB4: if (AC(15) = 0) then (PC  PC + 1)
SNA rB3: if (AC(15) = 1) then (PC  PC + 1)
SZA rB2: if (AC = 0) then (PC  PC + 1)
SZE rB1: if (E = 0) then (PC  PC + 1)
HLT rB0: S0

Input/Output D7IT3 = p (Common to all input/output instructions)

IR(i) = Bi (i = 6, 7, 8, ..., 11)
p: SC  0
INP pB11: AC(0-7)  INPR, FGI  0
OUT pB10: OUTR  AC(0-7), FGO  0
SKI pB9: if (FGI = 1) then (PC  PC + 1)
SKO pB8: if (FGO = 1) then (PC  PC + 1)
ION pB7: IEN  1
IOF pB6: IEN  0
 CONTROL OF IEN

IEN: Interrupt Enable Flag

pB7: IEN  1 (I/O Instruction)
pB6: IEN  0 (I/O Instruction)
RT2: IEN  0 (Interrupt)

p = D7IT3 (Input/Output Instruction)

D
7
p
I
J Q IEN
B7
T3

B6
K

R
T2
Control of Common Bus
COMMON BUS SYSTEM
S2
S1 Bus
S0
Memory unit 7
4096 x 16
Address
Write Read

AR 1

LD INR CLR

PC 2

LD INR CLR

DR 3

LD INR CLR

E
ALU AC 4

LD INR CLR

INPR
IR 5

LD
TR 6

LD INR CLR
OUTR
Clock
LD
16-bit common bus
COMPLETE COMPUTER DESCRIPTION: MICROOPERATIONS
Fetch RT0: AR  PC
RT1: IR  M[AR], PC  PC + 1
Decode RT2: D0, ..., D7  Decode IR(12-14),
AR  IR(0-11), I  IR(15)
Indirect D7IT3: AR  M[AR]
Interrupt
T0T1T2(IEN)(FGI + FGO): R 1
RT0: AR  0, TR  PC
RT1: M[AR]  TR, PC  0
RT2: PC  PC + 1, IEN  0, R  0, SC  0
Memory-reference
AND D0T4: DR  M[AR]
D0T5: AC  AC  DR, SC  0
ADD D1T4: DR  M[AR]
D1T5: AC  AC + DR, E  Cout, SC  0
LDA D2T4: DR  M[AR]
D2T5: AC  DR, SC  0
STA D3T4: M[AR]  AC, SC  0
BUN D4T4: PC  AR, SC  0
BSA D5T4: M[AR]  PC, AR  AR + 1
D5T5: PC  AR, SC  0
ISZ D6T4: DR  M[AR]
D6T5: DR  DR + 1
D6T6: M[AR]  DR, if (DR = 0) then (PC  PC + 1),
SC  0
COMPLETE COMPUTER DESCRIPTION: MICROOPERATIONS
Register-reference
D7IT3 = r (Common to all register-reference instructions)
IR(i) = Bi (i = 0, 1, 2, ..., 11)
r: SC  0
CLA rB11: AC  0
CLE rB10: E0
CMA rB9: AC  AC
CME rB8: E  E
CIR rB7: AC  shr AC, AC(15)  E, E  AC(0)
CIL rB6: AC  shl AC, AC(0)  E, E  AC(15)
INC rB5: AC  AC + 1
SPA rB4: if (AC(15) = 0) then (PC  PC + 1)
SNA rB3: if (AC(15) = 1) then (PC  PC + 1)
SZA rB2: if (AC = 0) then (PC  PC + 1)
SZE rB1: if (E = 0) then (PC  PC + 1)
HLT rB0: S0

Input/Output D7IT3 = p (Common to all input/output instructions)

IR(i) = Bi (i = 6, 7, 8, ..., 11)
p: SC  0
INP pB11: AC(0-7)  INPR, FGI  0
OUT pB10: OUTR  AC(0-7), FGO  0
SKI pB9: if (FGI = 1) then (PC  PC + 1)
SKO pB8: if (FGO = 1) then (PC  PC + 1)
ION pB7: IEN  1
IOF pB6: IEN  0
 CONTROL OF COMMON BUS

Selected
S2 S1 S0 Register

0 0 0 none
0 0 1 AR
0 1 0 PC
0 1 1 DR
1 0 0 AC
1 0 1 IR
1 1 0 TR
1 1 1 Memory

For selecting AR as source register:

D4T4: PC  AR
D5T5: PC  AR

S0 = D4T4 + D5T5
THE VON NEUMANN ARCHITECTURE

General-purpose (von Neumann) Architecture