CE222

Computer Organization and

Assembly Language

Salman Ashraf

Faculty of Computer Science and Engineering

 TYPES OF MICROOPERATIONS

• Computer system microoperations are of four types:

- Register transfer microoperations

- Arithmetic microoperations
- Logic microoperations
- Shift microoperations
 REGISTER TRANSFER

• Copying the contents (information transfer) from one register

to another is a register transfer.

• Symbolically, a register transfer is indicated by means of a

replacement operator, as

R2  R1

– In this case the contents of register R1 are copied (loaded) into

register R2
– A simultaneous transfer of all bits from the source R1 to the
destination register R2
– Note that this is a non-destructive; i.e. the contents of R1 are not
altered by copying (loading) them to R2
 REGISTER TRANSFER

• A register transfer such as

R2  R1

Implies that the digital system has

– the data lines from the source register (R1) to the destination
register (R2)
– Parallel load capability at destination register (R2)
– Control lines to perform the action
 CLOCK
• Clock: In digital circuit design, clock means a signal
that oscillates between 0 and 1 in a regular fashion.
– All computers are constructed using a clock running at constant
rate.
– Ticks of the clock act as synchronizing events that keep other
components in step with each other.

• Positive clock edges: Transitions of the clock from 0 to 1

• Negative clock edges: Transitions from 1 to 0

Positive edge Triggering

 CLOCK

• Clock Pulse: The region between a positive and negative

clock edge.

• Microoperation: An elementary operation performed on

one or more registers during a single clock pulse.
e.g. R2  R1
R2 Clock
n pulse
R1

• Clock pulse is used to synchronize microoperations.

 CLOCK

• Clock cycle: The time interval between one positive or

negative edge and the next positive or negative edge
respectively.
– Or the amount of time between two pulses.

Features of a clock

• Clock cycles are also known as clock periods, ticks,

clock ticks, or cycles.
 CONTROL FUNCTIONS
• Often actions need to occur only if a certain condition is true.
This is similar to an “if” statement in a programming language

• In digital systems, this is often done via a control signal

– If the signal is 1, the action takes place

• In RTL, this is represented by means of a control function :

P: R2  R1

Which means “if P = 1, then load the contents of register R1 into

register R2”, i.e., if (P = 1) then (R2  R1)

• A control function is a Boolean variable terminated with a

colon.
HARDWARE IMPLEMENTATION OF CONTROLLED TRANSFERS

Every statement written in RTL implies a hardware construction for

Implementing the transfer.
Example: Implementation of controlled transfer P: R2  R1

Block diagram Control P Load

R2 Clock
Circuit
n
R1

Timing diagram t t+1

Clock

Load
Transfer occurs here

• Registers are assumed to use positive-edge-triggered flip-flops

• P may go back to 0 at time t+1, otherwise the transfer will occurs at every rising
clock edge while P remains active
 CONNECTING REGISTRS FOR REGISTER TRANSFER
• A typical digital computer has many registers, and paths must be
provided to transfer information from one register to another.

• It is impractical to have data and control lines to directly allow each

register to be loaded with the contents of every possible other
registers.

• To completely connect n registers → n(n – 1) minimum lines

– This is not a realistic approach to use in a large digital system

• A more efficient scheme for transferring information between registers

in a multiple-register configuration is to:
– Have one centralized set of circuits for data transfer, i.e., a common bus system
– Have control circuits to select which register is the source, and which is the
destination
THE VON NEUMANN ARCHITECTURE

General-purpose (von Neumann) Architecture

 STRUCTURE - THE CPU
Structural Components of CPU

Computer Arithmetic
Registers and
I/O Login Unit
System CPU
Bus
Internal CPU
Memory Interconnection

Control
Unit
 BUS AND BUS TRANSFER

• Bus is a shared path (a set of common lines, one for each bit
of a register) over which information is transferred (one at a
time), from any of several sources to any of several
destinations.

From a register to bus: BUS  R

A B C D

Bus lines
Constructing A Bus System using
Multiplexers
 RECALL MULTIPLEXER

• A combinational circuit with 2n input data lines, a single output line

and n input selection lines.

4-to-1 Multiplexer

I0
Function Table
I1 Select Output
Y S1 S0 Y
I2
0 0 I0
I3 0 1 I1
1 0 I2
1 1 I3
S0
S1
 BUS SYSTEM FOR FOUR REGISTERS
Register A Register B Register C Register D

0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3

B0 C 0 D 0 B1 C 1 D 1 B2 C 2 D 2 B3 C 3 D 3

0 0 0 0
4x1 4x1 4x1 4x1
MUX−0 MUX−1 MUX−2 MUX−3

S0
Register
S1 S1 S0 selected
0 0 A
0 1 B
4-line bus 1 0 C
1 1 D

In general, a bus system multiplexes k registers, of n bits each, to produce n-line bus using
n multiplexers. The size of each multiplexer must be k x 1.
Constructing A Bus System using
Decoders and Three-State Gates
 RECALL DECODERS

• Decoder is a combinational circuit that converts n coded inputs to

2n unique outputs.

2-to-4 Decoder

D0

E S1 S0 D0 D1 D2 D3
S0 D1
1 0 0 1 0 0 0
1 0 1 0 1 0 0
1 1 0 0 0 1 0 D2
1 1 1 0 0 0 1
0 d d 0 0 0 0 D3
S1
E
 THREE-STATE GATE

• A three-state gate is a digital circuit that exhibits three states. Two of

the states are signals equivalent to logic 1 and 0 as in a conventional
gate. The third state is a high-impedance state.

Output Y if C=1, output is enabled, i.e., Y = A

Normal input A
if C=0, output is disabled (high-impedance),
Control input C regardless of the value of A

The High impedance state behaves like an open circuit, which means
that the output is disconnected.
 BUS LINE WITH THREE-STATE GATES
Output Y if C=1, output is enabled, i.e., Y = A
Normal input A
if C=0, output is disabled (High-impedance),
Control input C regardless of the value of A
0
Register D Register C Register B Register A

1
2
3
Bus line for bit 0
A0
0
0 E S1 S0 D0 D1 D2 D3
1
1
B0
2 C0 1 0 0 1 0 0 0
2
3
3 D0 1 0 1 0 1 0 0
1 1 0 0 0 1 0
0
S0 0 1 1 1 0 0 0 1
1 1
2
S1 2 0 d d 0 0 0 0
3 E 3
2x4
0 decoder
1
2
3

• Each group of four gates receives one bit from the four registers.
• Each output produces one of the lines for the common bus for a total of 4 lines.
• Only one decoder is necessary to select between the four registers.
• To construct a common bus for k registers of n bits each using three-state gates,
we need n circuits with k gates in each.
 BUS TRANSFER IN RTL

• Depending on whether the bus is to be mentioned

explicitly or not, register transfer can be indicated as
either
R2  R1
or
BUS  R1, R2  BUS

• In the former case the bus is implicit, but in the latter, it is

explicitly indicated.
 MEMORY (RAM)
• Memory (RAM) can be thought of as a sequential circuit containing
some number of registers
• These registers hold the words of memory
• Each of the r registers is indicated by an address
• These addresses range from 0 to r-1
• Each register (word) can hold n bits of data
• Assume the RAM contains r = 2k words. It needs the following:
– n data input lines
– n data output lines
data input lines
– k address lines
– Control lines (Read, Write) n

address lines
k RAM
Read
unit
Write
n
data output lines

• A typical system bus consists of data, address, and control lines.

 MEMORY TRANSFER
• Collectively, the memory is viewed at the register level as a
device, M.

• A particular memory word is selected by the memory address during

Read or Write.
– This will be done by enclosing the address in square brackets following the letter M.

• Memory is usually accessed in computer systems by putting the

desired address in a special register, the Memory Address
Register (MAR or AR).

M
Memory Read
AR
unit Write

Data out Data in

 MEMORY READ AND WRITE

• To read a value from a location in memory and load it into a

register, the register transfer language notation looks like
this:
R1  M[AR]

• To write a value from a register to a location in memory

can be stated symbolically in register transfer language
as:
M[AR]  R1
 TYPES OF MICROOPERATIONS

• Computer system microoperations are of four types:

- Register transfer microoperations

- Arithmetic microoperations
- Logic microoperations
- Shift microoperations
 ARITHMETIC MICROOPERATIONS

• The basic arithmetic microoperations are:

– Increment
– Decrement
– Addition
– Subtraction

Typical Arithmetic Microoperations

R1  R1 + 1 Increment
R1  R1 - 1 Decrement
R3  R1 + R2 Contents of R1 plus R2 transferred to R3
R3  R1 - R2 Contents of R1 minus R2 transferred to R3
R3  R1 + R2’+1 Subtraction (R1 – R2)
R1  R1’ + 1 2's complement the contents of R1 (negate)
Designing Binary Incrementer
 RECALL HALF ADDER
• A digital circuit that performs the arithmetic addition of two bits is
called a half-adder.

y y
x y c s
0 0 0 0 0 0 0 1
0
1
1
0
0
0
1
1
x 01 x 1 0
1 1 1 0 c = xy s = xy’ + x’y
=x  y

x
y c

s
 BINARY INCREMENTER
Increment: S  A + 1

A3 A2 A1 A0 1

x y x y x y x y
HA HA HA HA
C S C S C S C S

C4 S3 S2 S1 S0

4-bit Binary Incrementer

• The circuit receives four bits from A0 through A3, adds one to it, and
generates the incremented output in S0 through S3 (S  A + 1).
• The output carry C4 will be 1 only after incrementing binary 1111.
• The circuit can be extended to an n-bit binary incrementer by extending
the diagram to include n half-adders.
Designing Binary Adder
 RECALL FULL ADDER
• A digital circuit that forms the arithmetic sum of three bits (two
significant bits and a previous carry) is called a full-adder.

x y cn-1 cn s y y
0 0 0 0 0 0 0 0 1
0 0 1 0 1 0 1 cn-1 1 0 cn-1
0 1 0 0 1 1 1 0 1
x x
0 1 1 1 0
1 0 0 0 1 0 1 1 0
cn s
1 0 1 1 0
1 1 0 1 0 cn = xy + xcn-1+ ycn-1
1 1 1 1 1 = xy + (x  y)cn-1

s = x’y’cn-1+x’yc’n-1+xy’c’n-1+xycn-1
x = x  y  cn-1 = (x  y)  cn-1
y S
cn-1
cn
 BINARY ADDER
Addition: S  A + B

• A digital circuit that generates the arithmetic sum of two binary numbers of
any length is called a binary adder.

• A binary adder is constructed with full-adder circuits connected in cascade,

with the output carry from one full-adder connected to the input carry of the
next full-adder.

B3 A3 B2 A2 B1 A1 B0 A0

FA C3 FA C2 FA C1 FA C0

C4 S3 S2 S1 S0
4-bit Adder

• The S outputs of the full-adders generate the required sum bits (S  A + B).
• An n-bit binary adder requires n full-adders.
 BINARY SUBTRACTOR
Subtraction
R3  R1 - R2
or
R3  R1 + R2’+1

• R2’ is the 1' s complement of R2.

• Adding 1 to R2’ produces the 2' s complement of R2.
• Adding the contents of R1 to the 2' s complement of R2 is equivalent to R1 - R2.

• Example: 1111 – 1101 = 0010

Modify 4-bit Adder

 BINARY ADDER-SUBTRACTOR
I B X-OR
0 0 0
0 1 1
1 0 1
1 1 0

B3 A3 B2 A2 B1 A1 B0 A0

I
M

C3 C2 C1 C0
FA FA FA FA

C4 S3 S2 S1 S0

4-bit Adder-Subtractor

When I=0, B + 0 = B and carry (I) = 0 → A + B (adder)

When I=1, B + 1 = B’ and carry (I) = 1 → A + B’+1 (subtrator)

 ARITHMETIC MICROOPERATIONS

• The basic arithmetic microoperations are:

– Increment
– Decrement
– Addition
– Subtraction

R1  R1 + 1 Increment
R1  R1 - 1 Decrement
R3  R1 + R2 Contents of R1 plus R2 transferred to R3
R3  R1 + R2’+1 Subtraction (R1 – R2)

All arithmetic microoperations listed above, and a few more, can be

implemented using a single composite arithmetic circuit as shown.
 ARITHMETIC CIRCUIT
Cin
S1
S0
A0 X0 C0
S1 FA D0
S0
0 4x1 Y0 C1
B0 1 MUX
2
3
A1 X1 C1
S1 FA D1
S0
0 4x1 Y1 C2
B1 1 MUX
2
3
A2 X2 C2
S1 FA D2
S0
0 4x1 Y2 C3
B2 1 MUX
2
3
A3 X3 C3
S1 FA D3
S0
B3 0 4x1 Y3 C4
1 MUX
2
3 Cout
0 1

4-bit Composite Arithmetic Circuit

By controlling the data inputs to the full adders, it is possible to obtain eight
arithmetic microoperations.
 ARITHMETIC CIRCUIT FUNCTION TABLE

FA FA
Selection Input Output Microoperation
S1 S0 Cin Y D=A+Y+Cin
0 0 0 B D=A+B Add
0 0 1 B D=A+B+1 Add with carry
0 1 0 B’ D = A + B’ Subtract with borrow
0 1 1 B’ D = A + B’+ 1 Subtract
1 0 0 0 D=A Transfer A
1 0 1 0 D=A+1 Increment A
1 1 0 1 D=A-1 Decrement A (A+ all 1’s = A-1)
1 1 1 1 D=A Transfer A (A-1 + 1 = A)

The microoperation D = A is generated twice, so there are only seven distinct

microoperations in the composite arithmetic circuit.