MOD - 1 : 8086 Architecture

Q1) - Explain architecture of 8086?

Architecture of 8086

The 8086 CPU is divided into two independent functional parts:

a. Bus Interface Unit (B.I.U)

b. Execution Unit (E.U)

1. B.I.U:
a. The BIU sends an address, fetches instructions from memory, reads data
from memory and writes data to memory.
b. In other words, B.I.U handles transfer of data and address on buses for
execution unit
c. It consists of following parts:
1. Queue:

To speed up execution of the program, BIU fetches 6 instruction bytes

ahead of time from memory and stores them in E.U in the queue.

2. Segment registers:

These are 16-bit registers used to manage memory segments.

 B.I.U contains following segment registers:

1. Code Segment (CS): This register points to the part of memory

where the program's code (instructions) is stored.
2. Stack Segment (SS): This register manages memory for the
stack, which is used to store temporary data and addresses
during program execution.
3. Data Segment (DS): This register points to the memory area
where the program's data is stored. The program uses this
segment to read and write data.
4. Extra Segment (ES): This is an additional data segment, often
used for operations involving string data, like copying a string
to a different location in memory.

3. Instruction Pointer (IP):

This register works with the Code Segment (CS) register to keep track
of where the next instruction in the program is located.

The IP holds a 16-bit address that tells the CPU where to find the next
byte of code to execute within the code segment.

2. Execution Unit (EU):

a. Execution unit tells BIU from where to fetch the data and then decode and execute
those instructions.
b. Its function is to control operations on data using the instruction decoder & ALU.
c. It consist of following functional parts:
i. ALU

It handles all arithmetic and logical operations, like +, −, ×, /, OR, AND, NOT
operations.

ii. Flag Register

It is a 16-bit register that behaves like a flip-flop, i.e. it changes its status
according to the result stored in the accumulator. It has 9 flags and they are
divided into 2 groups −

iii. Conditional Flags:

1. It represents the result of the last arithmetic or logical instruction
executed.
2. It includes Carry flag, Auxiliary, Parity, zero, Sign, Overflow flags.
iv. Control Flags
1. Control flags control the operations of the execution unit.
2. Following is the list of control flags −Trap flag, Interrupt flag, Direction
flag
v. General purpose register
 There are 8 general purpose registers, i.e., AH, AL, BH, BL, CH, CL, DH, and
DL. These registers can be used individually to store 8-bit data and can be
used in pairs to store 16-bit data which is represented as AX, BX, CX, and DX
respectively.

vi. Stack pointer register

It is a 16-bit register, which holds the address from the start of the segment to
the memory location, where a word was most recently stored on the stack.

Q2) - Flag register of 8086

The flag register is a special purpose register that behaves like a flip-flop, i.e. it changes its
status according to the result stored in the accumulator.

8086 has 16-bit flag register, and there are 9 valid flag bits. The format of flag register is like
below.

Q3) - Explain the programming model of 8086?

The programming model of the 8086 microprocessor consists of various registers that are
crucial for data manipulation and program execution. These registers are categorized into
four main groups, each serving specific functions:

1. General Purpose Registers:

a. AX (Accumulator): Used for arithmetic operations and data transfers.
b. BX (Base Register): Primarily used for addressing purposes.
c. CX (Counter Register): Utilized in loop and string operations.
d. DX (Data Register): Used in I/O operations and extended arithmetic
operations.

Each of these 16-bit registers can also be accessed as two 8-bit registers, e.g., AX
can be split into AH (high byte) and AL (low byte).
 2. Segment Registers:
a. ES (Extra Segment): An additional data segment register.
b. CS (Code Segment): Points to the segment containing the code.
c. DS (Data Segment): Points to the segment containing data.
d. SS (Stack Segment): Points to the segment containing the stack.

These registers define the locations of code, data, and stack segments, facilitating
the segmented memory architecture of the 8086.

3. Segment Offset Pointers:

a. SP (Stack Pointer): Points to the current position within the stack.
b. BP (Base Pointer): Used for accessing data on the stack.
c. SI (Source Index): Used in string operations as the source pointer.
d. DI (Destination Index): Used in string operations as the destination pointer.
e. IP (Instruction Pointer): Points to the next instruction to be executed.

These pointers are critical for memory addressing and execution control.

4. Flag Register
a. The Flag Register contains status flags that reflect the outcomes of
operations. Key flags include Zero, Carry, Sign, and Overflow flags.
b. This register provides information about the state of the processor and the
outcome of operations, which is essential for decision-making in programs.

In summary, the programming model of the 8086 microprocessor is designed to facilitate

efficient data handling and control flow within the processor, making it a versatile and
powerful architecture for its time.

Q4) - Explain the interrupt structure of 8086

1. An interrupt is a condition that halts the microprocessor temporarily to work on a

different task and then returns to its previous task.
2. It is an event or signal that requests the CPU’s attention.
3. This halt allows peripheral devices to access the microprocessor.
4. Whenever an interrupt occurs, the processor completes the current instruction and
starts the implementation of an Interrupt Service Routine (ISR) or Interrupt Handler.
5. ISR is a program that tells the processor what to do when the interrupt occurs. After
the ISR execution, control returns to the main routine where it was interrupted.
6. The different types of interrupts present in the 8086 microprocessor are given by:
a. Hardware Interrupts – Hardware interrupts are those interrupts that are
caused by any peripheral device by sending a signal through a specified pin
to the microprocessor. There are two hardware interrupts in the 8086
microprocessor. They are:
i. NMI (Non-Maskable Interrupt): It is a single pin non-maskable
hardware interrupt that cannot be disabled. It is the highest priority
interrupt in the 8086 microprocessor.
ii. INTR (Interrupt Request): It provides a single interrupt request and is
activated by the I/O port. This interrupt can be masked or delayed. It is
a level-triggered interrupt.
 b. Software Interrupts – These are instructions inserted within the program to
generate interrupts. There are 256 software interrupts in the 8086
microprocessor. The instructions are of the format INT type, where the type
ranges from 00 to FF.

Q5) - Draw and Explain interrupt vector table (IVT) and explain/differentiate btw hardware
and software interrupts.

1. The Interrupt Vector Table (IVT) in the 8086 microprocessor is a critical structure
located at the beginning of the memory address space, ranging from 0000H to
03FFH.
2. It consists of 256 entries, each occupying 4 bytes, totaling 1 KB in size.
3. Each entry in the IVT stores the segment (CS) and offset (IP) addresses of the
corresponding Interrupt Service Routine (ISR).
4. Key points about the IVT:
a. Address Range: 0000H to 03FFH.
b. Entry Size: Each entry is 4 bytes (32 bits).
c. Total Entries: 256 interrupt pointers.
d. Structure: Each pointer comprises a CS pair that points to the ISR.
e. Dedicated Pointers:
i. Type 0 (0000H): Divide Error.
ii. Type 1 (0004H): Single Step.
iii. Type 2 (0008H): Non-Maskable Interrupt (NMI).
iv. Type 3 (000CH): Breakpoint.
v. Type 4 (0010H): Overflow.
f. Reserved Pointers: Certain pointers, like Types 5 through 31, are reserved for
future or specific use.
 g. Available Pointers: Pointers from Type 32 to Type 255 are available for
user-defined interrupts.
h. Function: The IVT allows the CPU to quickly locate and execute the
appropriate ISR when an interrupt occurs, ensuring efficient interrupt
handling.
5. This organization facilitates the handling of both hardware and software interrupts by
providing a direct and structured approach to accessing interrupt service routines.

Q6) - Explain memory segmentation

1. Memory segmentation in the 8086 microprocessor efficiently manages its 1MB

memory space using 16-bit segment registers combined with 16-bit offsets to form
20-bit physical addresses.
2. The four main segment registers are Code Segment (CS) for instructions, Stack
Segment (SS) for temporary data, Data Segment (DS) for program data, and Extra
Segment (ES) for additional data storage, such as strings.
3. The formula for calculating the physical address is:

Physical Address = (Segment Address * 10H) + Offset Address.

4. For example, with a segment address of 1000H and an offset of 2345H, the physical
address would be 12345H.
5. This system allows the use of efficient, byte-compatible 16-bit addresses while still
accessing a larger 1MB memory space.
 6. Segmentation prevents data overriding by keeping each type of data within its
designated segment, ensuring that program instructions, stack data, and other data
do not interfere with each other.
7. This organized approach is crucial for managing the larger memory space of the
8086 compared to the 8085, which only had a 16-bit address bus for its 64KB
memory.
8. Segmentation not only makes memory management more efficient but also simplifies
it for programmers, as they work with segment and offset addresses rather than the
full 20-bit physical addresses.

Below is the one way of positioning four segments within the memory space of an
8086.

Q7) - What is advantage of memory banking in 8086 mp? justify with example

Memory banking in 8086 MP extends memory beyond the 1 MB limitation, facilitating

dynamic allocation of memory resources and concurrent access to multiple memory banks.

This architecture offers several advantages which includes:

a. Increased Memory Capacity: Memory banking allows multiple memory banks to be

accessed by the processor, effectively extending the available memory beyond the 1
MB limit of the 8086 architecture. Each memory bank can be independently
addressed, providing a larger combined address space.
b. Flexibility in Memory Management: Memory banking allows for dynamic allocation of
memory resources, enabling efficient memory management and resource utilization
in microprocessors.
c. Support for Large Data Structures: Memory banking facilitates the handling of large
data structures that may exceed the capacity of a single memory bank. By spreading
 the data across multiple banks, the system can accommodate larger datasets without
running into memory constraints.
d. Improved Performance: Memory banking can enhance system performance by
allowing concurrent access to multiple memory banks. In multiprocessing (MP)
systems, multiple processors can access different memory banks simultaneously,
reducing contention for memory resources and improving overall system throughput.

Example:
Let's consider a scenario where a 8086 MP system needs to address more than 1
MB of memory for a multimedia application. Without memory banking, the system
would be limited to the 1 MB address space provided by the 8086 architecture, which
might not be sufficient for storing large multimedia files or handling complex video
processing tasks.

By implementing memory banking, the system can divide the extended memory into
multiple banks, each containing a portion of the multimedia data. For example, one
bank could store video frames, another bank could store audio samples, and
additional banks could be allocated for buffers and intermediate processing stages.

During multimedia playback or processing, the processors in the MP system can

access different memory banks simultaneously, fetching data in parallel and
improving overall performance.

Q8) - Difference btw minimum mode and maximum mode

Q9) - IMP MAM Draw & explain the Read or write operation timing diagram of 8086 in
maximum mode
Read Cycle

a. Address Latch Enable (ALE): The address is placed on the address bus (AD0-AD19)
and latched by the external latches at the beginning of T1.
b. Status Signals (SO, S1, S2): In T2, the status signals (SO=1, S1=0, S2=1) are
asserted to indicate a memory read operation.
c. Data Transceiver (DT/R): The DT/R signal goes high in T2 indicating that the data will
be read from the memory onto the data bus.
d. Memory Read Command (MRDC): The MRDC signal is asserted in T3 to initiate the
memory read operation.
e. Data Enable (DEN): The DEN signal goes high in T4 to enable the data transceivers
onto the data bus.
f. Data Read (D0-D15): The data read from memory is placed on the data bus
(D0-D15) in T4 and can be retrieved by the processor.

Unlike a write cycle, the DT/R signal is high during a read cycle to indicate the direction of
the data flow.

Write cycle
 a. Address Latch Enable (ALE): The address is placed on the address bus (AD0-AD19)
and latched by the external latches at the beginning of T1.
b. Status Signals (SO, S1, S2): In T2, the status signals (SO=0, S1=1, S2=1) are
asserted to indicate a memory write operation.
c. Data Transceiver (DT/R): The DT/R signal goes low in T2 indicating that the data will
be placed on the data bus from the processor.
d. Memory Write Control (MWTC): The MWTC signal is asserted in T3 to initiate the
memory write operation.
e. Data Enable (DEN): The DEN signal goes high in T4 to enable the data transceivers
onto the data bus.
f. Data Write (D0-D15): The actual data to be written is placed on the data bus
(D0-D15) in T4.

Q10) - IMP Draw & explain the Read or write operation timing diagram of 8086 in minimum
mode

1. Address Latch Enable (ALE): A pulse is generated on the Address Latch Enable
(ALE) line at the beginning of T1. This pulse instructs external latches to capture the
valid address from the address bus (AD0-AD19).
2. Memory/IO (M/IO): The M/IO signal remains low during T1 to T4 indicating a memory
operation is in progress.
3. Data Transfer/Receive (DT/R): The DT/R signal goes low in T2 signifying the
processor is ready to receive data.
4. Data Enable (DEN): The DEN signal goes low in T2 as well to enable the data
transceivers onto the data bus.
5. Read (RD): The Read (RD) signal is asserted low in T2 to initiate the memory read
operation.
 6. Data Available (READY): The memory or I/O device asserts the READY signal high
in T3 to indicate the data is valid and ready to be placed on the data bus.
7. Data Read (D0-D15): The data from memory is placed on the data bus (D0-D15) in
T3 and can be retrieved by the processor.

In essence, the 8086 microprocessor in minimum mode initiates a read cycle by placing the
address on the bus and asserting the ALE signal. It then waits for the memory to indicate it
has the data ready (READY signal) before reading it from the data bus.

Write cycle

1. Address Latch Enable (ALE): A pulse is generated on the Address Latch

Enable (ALE) line at the beginning of T1. This pulse instructs external latches
to capture the valid address from the address bus (AD0-AD19).
2. Memory/IO (M/IO): The M/IO signal remains low during T1 to T4 indicating a
memory operation is in progress.
3. Data Transfer/Receive (DT/R): The DT/R signal goes high in T2 signifying the
processor is ready to send data to the memory.
4. Data Enable (DEN): The DEN signal goes low in T2 as well to enable the data
transceivers onto the data bus.
5. Write (WR): The Write (WR) signal is asserted low in T2 to initiate the
memory write operation and place the data to be written on the data bus
(D0-D15).
6. Data Available (READY): The memory or I/O device might assert the READY
signal high in T3 or T4 to indicate it's ready to receive the data. However, the
8086 in minimum mode ignores the READY signal during a write cycle and
proceeds with the data transfer regardless.

In essence, the 8086 microprocessor in minimum mode initiates a write cycle by

placing the address and data on the bus and asserting the ALE and WR signals. It
 does not wait for an acknowledgement from the memory device (unlike maximum
mode) before completing the write operation.

Q11) - IMP Addressing modes of 8086

1. Addressing modes in the microprocessor define how operands are accessed for
instructions.
2. Addressing modes of 8086 are as follow:

a. Register Addressing Mode:

i. In this mode, both the operands are registers
ii. For instance, MOV AX, BX copies the contents of the BX register to the AX
register.
iii. This mode offers faster access to data stored in registers, enhancing the
processor's efficiency.
iv. Registers can be either 8 or 16 bits in size, providing flexibility in data
manipulation.

b. Immediate Addressing Mode:

i. In this mode the operand is directly specified within the instruction itself.
ii. For example, MOV CL, 02H loads the immediate value 02H into the CL
register. Immediate addressing allows for quick data initialization and constant
manipulation without the need for additional memory accesses.

c. Memory Addressing Mode:

i. In this mode, operands are accessed from memory locations.
ii. The processor generates a 20-bit effective address using segment registers
and various addressing components like base registers, index registers, and
displacements.
iii. Different memory addressing modes include:
1. Direct Memory Addressing Mode: The effective address is directly
provided in the instruction. For instance, MOV [1023], AL copies the
contents of the AL register to the memory location with the effective
address 1023.
2. Register Indirect Addressing Mode: The effective address is specified
by a base or index register. For example, MOV AL, [SI] copies the
contents of the memory location pointed to by the SI register to the AL
register.
3. Register Relative Addressing Mode: The effective address is
determined by adding an 8-bit displacement to a base or index
 register. For example, MOV [BX + 10], AL copies the contents of the
AL register to the memory location calculated as BX + 10.
4. Based Indexed Addressing Mode: The effective address is a
combination of a base register and an index register. For example,
MOV [BX + SI], AL copies the contents of the AL register to the
memory location calculated as BX + SI.
5. Relative Based Indexed Addressing Mode: Similar to based indexed
addressing, but with an additional 8-bit displacement. For example,
MOV [BX + SI + 04], AL copies the contents of the AL register to the
memory location calculated as BX + SI + 04.

d. String Addressing Mode:

i. Used in string instructions where pointers SI and DI, along with segment
registers DS and ES, access source and destination memory locations.
ii. Pointers are automatically incremented or decremented based on the
direction flag's value.

e. Implied Addressing Mode:

i. In this mode, the operand is not explicitly specified in the instruction. Instead,
it is inherent in the operation itself.
ii. For example, XLATB (Translate Byte) instruction implicitly uses the contents
of the AL register as an index to perform a lookup in a translation table.

f. Implied Addressing Mode:

i. In this mode, the operand is not explicitly specified in the instruction. Instead,
it is inherent in the operation itself.
ii. For example, XLATB (Translate Byte) instruction implicitly uses the contents
of the AL register as an index to perform a lookup in a translation table.

OR
 1. MOV AX, [BX+SI] (Based Indexed Addressing): Effective address is calculated by
adding BX and SI registers; operand accessed and stored in AX.

2. AND CL, [2000] (Direct Addressing): Operand accessed directly from memory
address 2000h and ANDed with CL register.

3. IN AL, DX (I/O Addressing): Reads input from port specified in DX and stores in AL
register.

4. JMP [BX+2] (Based Indexed Addressing with Displacement): Jump to instruction

calculated by adding 2 to contents of BX register.

5. ADD AX, [BX+SI+5] (Based Indexed Addressing with Displacement): Adds value at
memory location obtained by adding BX, SI, and 5 to AX register.

Q12) - Explain following instructions?

1. XLAT (Translate): IMP

XLAT stands for Translate.

This instruction is used for table lookups.
It takes the value in the AL register as an offset into a table in memory pointed to by
BX, and replaces AL with the byte at the effective address (BX + AL).

Example
MOV BX, OFFSET table
MOV AL, 2
XLAT ; AL = table[2]

Here we set AL to the value at index 2 of the table.

2. DAA (Decimal Adjust Accumulator): IMP

DAA stands for Decimal Adjust Accumulator.

This instruction adjusts the contents of the AL register after an addition operation to
ensure a correct BCD (Binary-Coded Decimal) result. It is used when adding BCD
numbers to ensure the result is also in BCD format.

Example
MOV AL, 90 ; AL = 90 (BCD)
ADD AL, 25 ; AL = BCD addition
DAA ; AL = 15 (BCD corrected)

Here we adjusts AL from 0xB5 to 0x15 after BCD addition.

3. AAA (ASCII Adjust for Addition): IMP
AAA stands for ASCII Adjust for Addition.
This instruction adjusts the result of adding two ASCII values in the AL register to
produce a correct unpacked BCD result. It is used in ASCII arithmetic operations.

MOV AL, 39h ; AL = '9'

ADD AL, 02h ; AL = '9' + 2
AAA ; AL = 01h (carry) and AH = 1

Here we adjust AL to 1 and set AH to 1 after ASCII addition.

4. STOSB (Store String Byte): IMP

STOSB stands for Store String Byte.
This instruction stores the byte in the AL register at the memory location pointed to
by DI (ES).
It then increments or decrements DI based on the direction flag (DF)

Example
MOV AL, 5
MOV DI, 1000h
STOSB ; [1000h] = 5, DI = 1001h or 0FFFh

This example stores 5 at memory location 1000h and updates DI.

5. LAHF (Load AH from Flags): IMP

LAHF stands for Load AH from Flags.
This instruction loads the AH register with the low byte of the EFLAGS register, which
contains the status flags (such as carry, zero, sign, and others)

Example
ADD AL, 1 ; Affect flags
LAHF ; Load flags into AH

This example loads the status flags into the AH register.

6. LODS (Load String):

LODS stands for Load String.
This instruction loads a byte or word from the address pointed to by SI (DS) into AL
or AX, respectively.
It then increments or decrements SI based on the direction flag (DF).

Example
MOV SI, 2000h
LODSB ; AL = [2000h], SI = 2001h or 1FFFh
 This example loads the byte at memory location 2000h into AL and updates SI.

7. SCAS (Scan String):

SCAS stands for Scan String.
This instruction compares AL or AX with the byte or word at the address pointed to
by DI (ES) and increments or decrements DI based on the direction flag (DF).
It also sets flags based on the comparison result.
Example
MOV DI, 3000h
MOV AL, 5
SCASB ; Compare AL with [3000h], DI = 3001h or 2FFFh

This example compares AL with the byte at memory location 3000h and updates DI.

Q13) - Explain Assembler Directives?

1. The assembler directives are special instructions used to indicate to the assembler
how a program is to be assembled and executed in a proper way.
2. These are also called as pseudo-operations which are not executable by the
processor.
3. Some commonly used assembler directives are listed below:
a. ASSUME:
i. The 8086 processor has four physical segments: DS (Data Segment),
CS (Code Segment), SS (Stack Segment), and ES (Extra Segment). It
also supports several logical segments.
ii. The ASSUME directive assigns a logical segment to a physical
segment.
iii. Example
ASSUME CS:CODE
It refers the logical segment as code

b. ALIGN:
i. This directive aligns the next variable or instruction to a specified
boundary.

ii. Example
ALIGN 4
This will force the assembler to align the next segment at an address
that is divisible by 4.

c. ORG:(originate):
This directive is used to set the starting offset address for the data or code.
Example: ORG 100H
This example sets the starting offset address to 100H.
 d. EVEN:
This directive aligns the next instruction or variable to an even byte boundary.

e. PAGE:
This directive helps control the format of the listing of an assembled program.
Syntax: PAGE [LENGTH], [WIDTH]

f. .CODE:
This directive indicates the start of the code segment.
It is Shortcut for defining the code segment.

g. .DATA:
This directive indicates the start of the data segment.
Shortcut for defining the data segment.

These directives help organize code, manage memory, define constants, and control the
assembly process, making the assembly language program more structured and easier to
understand.

======================================================================

8255 Programmable Peripheral Interface (PPI)

1. What it is: The 8255 is a programmable device used to interface the
microprocessor with external peripherals like keyboards, displays, and other
I/O devices.
2. Usage: It provides 24 I/O pins divided into three 8-bit ports (Port A, Port B,
and Port C), which can be configured as input or output as needed.
3. Example: If you want to connect a keyboard to the 8086, the 8255 can be
used to read the input from the keyboard and send it to the 8086 for
processing.

8257 Direct Memory Access (DMA) Controller

1. What it is: The 8257 is a DMA controller that allows peripheral devices to
directly transfer data to and from the memory without involving the CPU.
2. Usage: It helps in high-speed data transfer operations, reducing the CPU's
load and allowing it to perform other tasks while the data transfer is
happening.
3. Example: When transferring data from a hard drive to memory, the 8257 can
manage the data transfer directly, freeing up the 8086 to execute other
instructions simultaneously.

8259 Programmable Interrupt Controller (PIC)

1. What it is: The 8259 is an interrupt controller that manages interrupt signals
from various peripheral devices to the CPU.
 2. Usage: It prioritizes multiple interrupt requests and sends them to the CPU in
an orderly manner, ensuring that more critical tasks are attended to first.
3. Example: If both a keyboard and a mouse send interrupt signals to the 8086,
the 8259 decides which interrupt to handle first based on priority levels, and
sends the appropriate signal to the 8086 for processing.

How they work with the 8086:

● 8255: The 8086 communicates with external devices through the 8255 by
reading from or writing to its ports.
● 8257: The 8086 can set up the 8257 to handle data transfers between
memory and peripherals, reducing its own workload.
● 8259: The 8086 uses the 8259 to manage multiple interrupts, ensuring that it
handles high-priority tasks first.

In summary, these chips help the 8086 efficiently manage input/output operations, data
transfers, and interrupt handling, improving overall system performance and responsiveness.

======================================================================

Q14) - IMP Draw block diagram and Explain DMA controller 8257

1. The DMA controller, specifically the 8257, is a dedicated microprocessor designed to

manage data transfers between peripheral devices and memory in a computer
system.
2. Unlike the CPU, which executes instructions sequentially, the DMA controller
operates independently, allowing for simultaneous data transfers without CPU
intervention.
3. Functionally, the 8257 serves as an intermediary between peripheral devices, such
as hard drives or network cards, and the system memory. When a peripheral device
needs to transfer data to or from memory, it sends a request signal, known as DMA
request (DREQ), to the DMA controller.
4. Upon receiving a DMA request, the DMA controller temporarily pauses the CPU by
asserting a hold request. Once the CPU acknowledges the hold request by sending a
hold acknowledge (HLDA) signal, the DMA controller gains control of the system bus.
5. The DMA controller then accesses the memory directly, using the address and count
registers to determine the memory location and the amount of data to transfer.
 6. It reads or writes data between the peripheral device and memory without involving
the CPU, significantly reducing CPU overhead.
7. The 8257 supports four channels, allowing it to handle multiple data transfer requests
simultaneously.
8. Each channel can operate independently, with its own set of control registers and
modes of operation.
9. Overall, the DMA controller improves system performance by offloading data transfer
tasks from the CPU, allowing it to focus on executing instructions and tasks that
require computational processing power.
10. This results in faster data transfers and increased system efficiency, particularly in
systems with high data throughput requirements, such as multimedia processing or
data storage applications.

Q15) - IMP MAM Explain ICW and OCW (initial/operational command word) of 8259 PIC

1. The 8259 Programmable Interrupt Controller (PIC) is a crucial component in

computer systems for managing interrupt requests from various peripheral devices.
2. Its operation is controlled through a series of command words known as the Initial
Command Words (ICW) and Operational Command Words (OCW).
3. Initial Command Words(ICW):
a. The Initial Command Words (ICW) configure the 8259 PIC's operation mode
and cascading setup.
b. ICW1 indicates if ICW4 will be sent, sets the interrupt triggering mode, and
specifies the PIC's reaction to an EOI signal.
For instance, ICW1 = 0001 0001 initializes the PIC to edge-triggered mode
and preps for ICW4.
c. ICW2 sets the interrupt vector offset and determines the starting interrupt
vector number.
For example, ICW2 = 0010 0000 starts at vector number 32.
d. ICW3 identifies the slave PIC in cascaded setups and designates the IRQ line
for connection.
For instance, ICW3 = 0000 0100 assigns IRQ2 to the slave PIC.
e. ICW4 configures extra options like the microprocessor mode and automatic
EOI.
For instance, ICW4 = 0000 0010 sets the PIC to 8086/8088 mode and
enables automatic EOI.

4. Operational Command Words (OCW):

a. The Operational Command Words (OCW) are used for real-time control of
interrupt handling.
b. OCW1 masks or unmasks individual IRQs, allowing CPU control over
interrupt lines.
For example, OCW1 = 0000 0101 masks IRQ0 and IRQ2.
c. OCW2 manages interrupt processing modes and the EOI command, aiding in
interrupt acknowledgment and priority rotation.
For example, OCW2 = 0010 0000 sends an EOI command and configures
Automatic Rotation.
 d. OCW3 handles special functions like accessing interrupt request and
in-service registers.
For instance, OCW3 = 0000 0001 reads the ISR register.

In conclusion, ICW and OCW together facilitate the initialization and ongoing
operation of the 8259 PIC, ensuring effective interrupt management within the
system.

Q16) - 8255

The 8255 is a general purpose programmable IO device. It is designed to interface the CPU
with some external devices like ADC, DAC, keyboard etc. We can program the device
according to the given condition.

There are three 8-bit bi-directional IO ports. The Port-A, Port-B, and Port-C. These ports are
assigned as input or output port.

The block diagram of 8255 is like this:

The 8255 Programmable Peripheral Interface (PPI) operates in three primary modes
to interface with peripheral devices. These modes allow for flexible data transfer and
control operations:

A. Mode 0 (Basic Input/Output Mode):

a. Mode 0 is the simplest mode where each of the three ports (A, B, and
C) can be independently configured as either input or output ports.
b. There is no handshaking or interrupt capability in this mode, making it
ideal for straightforward data transfer between the microprocessor and
peripheral devices.
 c. For instance, you might use Port A to read sensor data (input) while
Port B drives LEDs (output).

B. Mode 1 (Strobed Input/Output Mode):

a. Mode 1 supports input or output operations with handshaking,
allowing synchronization between the data transfer processes.
b. Ports A and B can be configured to use part of Port C for control and
status signals, which ensures data integrity through synchronized
handshaking.
c. This mode is useful when reliable data transfer is needed, such as
reading data from a keyboard (input) or sending data to a printer
(output).

C. Mode 2 (Bidirectional Bus Mode):

a. Mode 2 is specific to Port A and enables it to operate as a bidirectional
data bus, allowing both data input and output.
b. Handshaking signals, provided by Port C, manage the bidirectional
data flow, ensuring proper synchronization.
c. This mode is suitable for complex applications where Port A needs to
alternate between sending and receiving data, such as communication
with another microprocessor or a bidirectional peripheral device.

=====================================================================

80386

Q1) - Explain the register organization of 80386

The 80386 microprocessor has several important registers that play key roles in its
operation. These registers can be categorized into the following types:

1. Data Registers
a. The 80386 has eight 32-bit general-purpose data registers named EAX, EBX,
ECX, EDX, ESI, EDI, EBP, and ESP.
b. These registers are used for general arithmetic and data manipulation
operations.
2. Pointer and Index Registers
a. EIP (Instruction Pointer): This 32-bit register holds the offset address of the
next instruction to be executed.
 b. ESP (Stack Pointer): It points to the top of the stack.
c. EBP (Base Pointer): It is used to reference parameters and local variables on
the stack.
3. Segment Registers
a. CS (Code Segment): Points to the segment where the instruction resides.
b. DS (Data Segment): Points to the segment where data is located.
c. SS (Stack Segment): Points to the segment of the stack.
d. ES (Extra Segment): An additional segment register for data.
4. Control Registers
a. CR0, CR2, CR3: These are control registers used for controlling and
managing the operation of the processor.
5. Status Registers
a. EFLAGS: This register contains status flags that indicate the result of
arithmetic and logical operations.
6. Debug Registers
a. DR0-DR7: These registers are used for debugging purposes.

Q2) - MAM Explain EFLAG Register of 80386

1. The EFLAGS register in the 80386 microprocessor is an extended version of the

FLAGS register found in earlier x86 processors.
2. It is a 32-bit register used to indicate the status of the processor and to control its
operation.

3. Among these 32 bits, D31 to D18, D15, D5 and D3 are reserved by Intel and D1 is
always 1.
4. Flags are imp because they are the conditions for conditional branching instructions.
5. These flags can be grouped into status flags, control flags, and system flags.
A. Status Flags
a. Carry Flag (CF): This flag is set if carry is produced by the most significant bit
during the execution of an arithmetic operation. In subtraction carry serves as
a borrow flag.
b. Parity Flag (PF): This flag is set to 1, if the result stored in the accumulator
contains even parity i.e. even number of 1’s. If accumulator contains odd
number of 1’s the flag is 0
c. Auxiliary Carry Flag (AF): In an arithmetic operation when carry is generated
from bit D3 to D4, the auxiliary carry flag is set to 1. This flag is only available
internally and used for BCD operations and not available for programmers.
d. Zero Flag (ZF): After performing arithmetic or logic operation, if the result is
zero, then zero flag is set to 1, else it is reset.
e. Sign Flag (SF):After execution of arithmetic and logic operation if the most
significant bit of the result is 1, then the sign flag is set to 1 otherwise 0. Ig
MSB is 1, the number will be negative and if it is 0, the number will be positive
f. Overflow Flag (OF): This flag will be set (1) if the result of a signed operation
is too large to fit in the number of bits available to represent it, otherwise reset
(0).

B. Control Flags
a. Direction Flag (DF): This flag is utilized in string instructions to determine the
direction of data access; when set (1), string data is accessed from higher
memory locations towards lower memory locations, and when reset (0), data
is accessed from lower memory locations towards higher memory locations.
b. Interrupt Enable Flag (IF): This flag governs the enabling or disabling of
maskable interrupts; when set, interrupts are enabled, permitting the
processor to respond to external interrupt requests, and when cleared,
interrupts are disabled.
c. Trap Flag (TF): Used for debugging purposes, this flag activates single-step
mode; when set, it triggers a trap after the execution of each instruction,
facilitating debugging by allowing step-by-step execution of code.

C. System Flags
a. I/O Privilege Level (IOPL): This flag register determines the privilege level
required for executing input/output (I/O) instructions. It consists of two bits
(Bits 12 and 13), allowing for four privilege levels ranging from 0 to 3, with 0
being the highest privilege level and 3 the lowest.
b. RF (Resume Flag) This is the first bit in the extended EFLAGS register. It is
used with the debug register breakpoints. At the starting of each instruction
cycle, the status of RF is always checked. If RF = 1, any debug fault will be
ignored while executing any instruction. This flag is automatically reset after
execution of instructions except IRET and POPE.
c. VM (Virtual Mode Flag) When this flag is set, the 80386 enters in the virtual
8086 mode within the protected mode. If VF is set, 80386 operates in
 protected mode. When this flag is cleared or reset, the 80386 operates in real
address mode.

Q3) - Short note on control register of 80386DX

q4) - Virtual mode, protected mode, Real mode short note and Difference btw in 80386

Real Mode:

1. Real mode is the initial operating state of the 80386 processor

2. In this mode, the processor operates using a segmented memory model, where
memory addresses are formed by combining a 16-bit segment selector with a 16-bit
offset.
3. Programs running in real mode have direct access to hardware resources and can
communicate directly with peripherals without any restrictions.
4. It's like using a basic tool without any safety measures or advanced functionalities.

Protected Mode:

1. Protected mode represents a significant advancement over real mode, introducing

features such as memory protection, multitasking, and virtual memory management.
2. In this mode, the processor operates using a flat memory model, where memory
addresses are represented by 32-bit linear addresses.
3. Protected mode provides a more secure and efficient computing environment, similar
to upgrading from a basic tool to a sophisticated machine with built-in safety features
and advanced capabilities.
Virtual Mode:

1. Virtual mode is a unique feature of the 80386 processor that enables it to emulate
multiple virtual 8086 environments simultaneously.
2. In this mode, the processor can create and manage multiple virtual machines, each
running its own instance of the 8086 instruction set architecture.
3. These virtual machines operate independently of each other, with their own virtual
memory space and system resources.

MAM

Q5) - Segment Descriptor

1. In the 80386 processor, a segment descriptor is a data structure used in

protected mode to describe a segment of memory.
2. It contains information such as the base address of the segment, its size,
access privileges, and other attributes necessary for memory management.
3. Segment descriptors are essential for translating logical addresses into linear
addresses and enforcing memory protection mechanisms.
Q6) - Explain protection mechanism of 80386

1. The protection mechanism in the Intel 80386 microprocessor is designed to

ensure that the system operates securely and efficiently by preventing
unauthorized access to memory and resources.
2. It is implemented through memory segmentation and paging, providing three
main categories of protection: limit check, type check, and privilege check.

1. Limit Check

The limit check ensures that any memory access stays within the bounds defined by
the segment descriptor.

This is crucial to prevent processes from accessing memory regions outside their
allocated space, which could lead to system instability or security breaches.

a. Segment Descriptor: Defines the size and location of a segment in memory.

b. G bit (Granularity bit): Determines if the limit is in units of bytes (0) or 4KB
pages (1).
c. Offset: The address within the segment.
d. Checks:
i. For 8-bit operations: OFFSET ≤ LIMIT
ii. For 16-bit operations: OFFSET ≤ LIMIT - 1
iii. For 32-bit operations: OFFSET ≤ LIMIT - 3

2. Type Check
The type check ensures that the type of memory access (data, code, or stack
segment) matches the permissions defined for that segment.

a. Type of Segment:
i. Data Segment: Can be read or written.
ii. Code Segment: Can be executed.
iii. Stack Segment: Used for stack operations.
b. Operations Checked:
i. Read and Write permissions.
ii. Executable permissions.

3. Privilege Check

The privilege check enforces a hierarchy of access levels, ensuring that higher
privilege levels have broader access to system resources, while lower levels are
more restricted.

This is essential for maintaining system stability and security, especially in

multitasking environments.

Privilege Levels (PL):

PL 0: Kernel mode (highest privilege)

PL 1: System services

PL 2: Custom extensions

PL 3: Applications (lowest privilege)

Q7) - GDT
Q Branch Prediction mechanism of pentium mp

1. Branch prediction is a crucial feature that was introduced in Pentium mp.

2. The goal of branch prediction is to minimize the performance impact of conditional
branches in program code by guessing which branch will be taken before it is known
for certain.
3. This is particularly important because the CPU pipeline typically consists of multiple
stages, and accurately predicting branches allows the processor to keep the pipeline
full and maximize performance.
4. The branch prediction mechanism in Pentium processors involves sophisticated
algorithms and hardware structures designed to make accurate predictions based on
past behavior and program context.
5. This helps to maintain a high instruction throughput and improve overall processor
efficiency.

Q2) - Address translation mechanism with diagram

Virtual address → Physical address

1. In the 80386 architecture, address translation converts virtual addresses to physical

addresses using a two-level paging system with page directories and page tables.
2. The need for this mechanism arises from the requirement to efficiently manage
memory, provide process isolation, and support multitasking by ensuring each
process operates within its own protected memory space.

Q3) - 8086 vs 80386 vs pent 1 2 3

Q4) - MAM Explain hyper threading with uses in pentium

Uses:

a. Improved Office Productivity: Hyper-Threading allowed office applications like word

processors, spreadsheets, and email clients to run simultaneously without significant
performance degradation, enhancing overall productivity.
b. Enhanced Web Browsing: Users experienced smoother and faster web browsing with
multiple tabs open, as Hyper-Threading enabled better handling of concurrent web
page loads and multimedia content.
c. Efficient Media Encoding: Hyper-Threading significantly sped up tasks such as video
encoding and compression, allowing users to convert and compress media files more
quickly.

Q5) - Explain pentium 4 net burst micro architecture

1. The Pentium 4 NetBurst microarchitecture was designed by Intel to achieve very high
clock speeds, allowing processors to perform tasks faster.
2. One of its key features was its deep instruction pipeline, which had up to 31 stages.
3. This meant that instructions went through many steps before they were fully
processed. This allowed the processor to handle more instructions at higher speeds.
4. Another significant feature of NetBurst was Hyper-Threading technology.
a. This innovation enabled a single processor to handle multiple threads, or
sequences of instructions, simultaneously.
 b. As a result, the processor could perform multiple tasks at the same time,
improving multitasking and the performance of applications.
5. NetBurst was also optimized for high clock speeds, meaning the processor could
complete many cycles per second, which theoretically increased performance.
6. This high clock speed was complemented by the Rapid Execution Engine, which
allowed the processor to execute certain types of instructions twice per clock cycle,
further enhancing performance.
7. To manage these high speeds, NetBurst included advanced branch prediction
capabilities, which helped the processor make better guesses about which
instructions to execute next. This reduced the delays caused by incorrect guesses,
known as branch mispredictions, and kept the pipeline flowing smoothly.
8. Thus NetBurst played a crucial role in advancing processor technology and laid the
groundwork for future innovations in Intel's processor lineup.

Q6) - MAM IMP MESI protocol

1. The MESI protocol, commonly used in cache coherency mechanisms, stands for
Modified, Exclusive, Shared, and Invalid.
2. When one processor modifies data stored in its cache, other processors accessing
the same data need to be aware of this modification to prevent data inconsistency.
Cache coherence protocols, like MESI (Modified, Exclusive, Shared, Invalid),
maintain data consistency by coordinating cache accesses and updates across
multiple processors.
3. In Pentium microprocessors, including those using the NetBurst architecture, the
MESI protocol helps maintain data consistency between caches in a multiprocessor
system.
4. The protocol operates through four main states:
a. Modified (M): Indicates that the cache line is present in the current cache and
has been modified, reflecting a difference from the main memory. This state
holds the most recent data version.
 b. Exclusive (E): Denotes that the cache line exists only in the current cache and
matches the data in main memory. It hasn't been modified, setting it apart
from the Modified state.
c. Shared (S): Represents a cache line present in multiple caches, all containing
identical data as stored in main memory. This state facilitates efficient data
sharing among multiple processors.
d. Invalid (I): Signifies that the cache line is invalid or absent in the cache,
necessitating data retrieval from main memory

5. These protocols ensure that:

a. Any modifications made to a memory location by one processor are visible to other
processors.
b. Reads by any processor return the most recent data.
c. Data shared between multiple processors is kept consistent to prevent conflicts and
errors.

6. When a processor needs to read or write data, the protocol determines the state of the
cache line and coordinates updates to maintain data consistency across caches.

7. This optimization minimizes unnecessary data transfers between caches and main
memory, enhancing overall system performance.

8. This optimization reduces unnecessary data transfers between caches and main
memory, thereby enhancing overall system performance.

Q7) - SUperScalar architecture

The Internal Architecture of Pentium Processor has been designed based on Superscalar. In
Superscalar architecture, two instructions are executed in parallel. Figure 12.2 shows the
superscalar architecture. Two independent integer pipelines are depicted in Fig. 12.2. In the
PF and D1 stages, the microprocessor can fetch instructions, decode instructions and
generate control words. In this stage, decoded instructions issue them to two parallel U and
V pipelines. For complex instructions, D1 generates microcoded sequences for U and V
pipelines. Several techniques are used to resolve the pairing of instructions.
Q7) - Integer Pipelines U and V

1. Inter-pipelining in the Pentium processor enables simultaneous handling of

instructions from different pipelines.
2. It allows concurrent execution of tasks like fetching, decoding, executing, and storing
instructions.
3. This means while one instruction is being decoded in one pipe, another instruction
can be fetched or executed in the other pipe.
4. The Pentium processor has two separate instruction pipelines, called U and V pipes.
5. It typically consisted of following stages:
a. Instruction Fetch: The processor fetches instructions from memory.
b. Instruction Decode: The fetched instructions are decoded to determine the
operation to be performed.
c. Execution: The decoded instructions are executed, which may involve
arithmetic or logical operations.
d. Write Back: The results of the executed instructions are written back to the
appropriate registers or memory locations.
6. This parallel processing enhances performance by minimizing idle time and
maximizing resource utilization.
7. Instructions such as arithmetic operations (e.g., addition, subtraction), logical
operations, memory access, and control flow instructions are executed concurrently.
8. The CPU efficiently processes tasks like addition, subtraction, bitwise operations,
loading data from memory, and branching in parallel.
9. Through efficient coordination, inter-pipelining ensures smooth execution and avoids
conflicts between instructions.
10. By facilitating simultaneous execution of multiple instructions, inter-pipelining boosts
overall throughput and efficiency of the CPU.

Q8) - MAM Floating point pipeline

1. In the Pentium processor, the Floating-Point Pipeline operates similarly to the Integer
Pipeline, allowing simultaneous handling of floating-point arithmetic instructions.
2. It enables concurrent execution of tasks such as fetching, decoding, executing, and
storing floating-point instructions.
a. It include same as above just with float value
3. This means while one floating-point instruction is being decoded in one pipeline,
another instruction can be fetched or executed in the other pipeline.
4. The Pentium processor's Floating-Point Pipeline consists of stages like Instruction
Fetch, Decode, Execution, and Write Back, similar to the Integer Pipeline.
5. Floating-point arithmetic operations, such as addition, subtraction, multiplication, and
division, are executed concurrently with other instructions.
6. Efficient coordination ensures smooth execution and minimizes conflicts between
floating-point and integer instructions.
7. By facilitating simultaneous execution of multiple instructions, the Floating-Point
Pipeline enhances overall throughput and efficiency of the CPU, particularly for tasks
involving complex mathematical computations.

Q9) - Parallelism and Performance:

The Pentium processor's architecture allowed for parallel execution of integer and
floating-point instructions, improving overall performance. This parallelism enabled
the processor to execute multiple instructions simultaneously, increasing throughput
and efficiency. By dedicating separate pipelines to integer and floating-point
operations, the Pentium processor could handle a wide range of computational tasks
efficiently, making it well-suited for both general-purpose computing and scientific
applications requiring high-performance floating-point arithmetic.

Q10) - MAM DMA 8257 data transfer modes

The DMA controller offers four modes for data transfer:

1. Single Byte Transfer Mode/Cycle Stealing:

a. The DMA controller transfers one byte at a time, alternating control of
the bus with the microprocessor.
b. After each byte transfer, the DMA controller adjusts its control and
waits for the DREQ signal to become active again before initiating the
next transfer.
2. Block Transfer Mode:
a. In this mode, the DMA controller transfers a block of data in one
complete operation, without interrupting the microprocessor.
b. Once all bytes are transferred, control is returned to the
microprocessor, either when the transfer count (TC) is reached or an
end-of-operation (EOP) signal is issued.
3. Demand Transfer Mode:
a. Similar to block transfer mode, but the DREQ signal must remain
active throughout the entire DMA operation.
 b. If DREQ goes low during operation, the DMA operation is paused,
allowing the microprocessor to resume control. The DMA operation
continues once DREQ becomes active again.
4. Cascade Transfer Mode:
a. Multiple DMA controllers are connected in cascade, allowing for
increased device interfacing.
b. A master DMA controller coordinates with one or more slave DMA
controllers, facilitating data transfer between devices and memory.
c. The master DMA controller manages HRQ signals from the slave
controllers and communicates with the microprocessor via the HOLD
signal.

Q11) - MAM explain conditional instruction of 8086

In the 8086 microprocessor, conditional instructions are instructions that are

executed based on certain conditions or flags set by previous instructions. These
instructions allow for branching or altering the flow of program execution based on
the outcome of a comparison or operation.

Conditional instructions typically involve comparing values or conditions and then

executing a specific operation or branching to a different part of the program based
on the result. They rely on the status flags in the flags register (FLAGS) to determine
whether the condition for execution is met.

Some common conditional instructions in the 8086 include:

a. JMP (Jump): This instruction transfers program control to a different memory

location based on a specified condition. For example, JMP if Zero (JZ) jumps
to a specified address if the Zero flag is set.
b. JE (Jump if Equal): Similar to JZ, this instruction jumps to a specified address
if the Zero flag is set, indicating that two operands are equal.
c. JNE (Jump if Not Equal): Jumps to a specified address if the Zero flag is not
set, indicating that two operands are not equal.
d. JG (Jump if Greater) and JL (Jump if Less): These instructions jump to a
specified address based on the result of a signed comparison, such as
greater than (JG) or less than (JL).
e. JC (Jump if Carry) and JNC (Jump if No Carry): These instructions jump to a
specified address based on the state of the Carry flag, which indicates
whether an arithmetic operation generated a carry out of the most significant
bit.
f. JZ (Jump if Zero) and JNZ (Jump if Not Zero): These instructions jump to a
specified address based on the state of the Zero flag, which indicates whether
the result of an operation is zero or not zero.
Conditional instructions are essential for implementing control structures like loops,
branches, and decision-making in assembly language programming for the 8086
microprocessor. They allow for flexible and efficient program execution based on runtime
conditions.