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ELECTRICAL AND ELECTRONICS ENGINEERING & COMPUTER ENGINEERING E E E 2 4 8 C N G 2 3 2 Logic Design

This document outlines a homework assignment for an Electrical and Electronics Engineering course focused on Logic Design. It includes five questions related to combinational and sequential circuits, with specific tasks such as designing circuits, deriving equations, and analyzing state diagrams. The assignment is due on May 9, 2022, and is graded out of 100 points.

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yunusemreyildiz111
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12 views4 pages

ELECTRICAL AND ELECTRONICS ENGINEERING & COMPUTER ENGINEERING E E E 2 4 8 C N G 2 3 2 Logic Design

This document outlines a homework assignment for an Electrical and Electronics Engineering course focused on Logic Design. It includes five questions related to combinational and sequential circuits, with specific tasks such as designing circuits, deriving equations, and analyzing state diagrams. The assignment is due on May 9, 2022, and is graded out of 100 points.

Uploaded by

yunusemreyildiz111
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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ELECTRICAL AND ELECTRONICS ENGINEERING

&
COMPUTER ENGINEERING

EEE 248 CNG 232


Logic Design

2 1 S P R I N G 2 2

HW II
Number of Questions: 4

Due: May 09, 2022


Good Luck

Dr. Gürtaç Yemişcioğlu

Student Number:

Full Name:

Question Achieved Points

1 16

2 20

3 20

4 28

5 16

TOTAL 100
EEE 248 CNG 232
Logic Design
21 SPRING 22
HWII

Question 1 (16 pts.): Design a combinational circuit that converts a 4-bit gray code to a 4-
bit binary number. Implement the circuit using exclusive-OR gates.
Question 2 (20 pts.): Sequential circuit shown below has two flip-flops A and B and one
input x. It consists of a combinatorial logic connected to the flip-flops, as shown in Figure
below. Analyse the circuit:

I0 2-to-1
DT
SET
Q A
MUX Z
I1
S
CLR Q A’
y

DT
SET
Q B
x

CLR Q B’

CLK

a. (6 pts) Derive the next state equations.


b. (6 pts) Derive the state table of the sequential circuit.
c. (6 pts) Draw the corresponding state diagram.
d. (2 pts) Is this a Mealy or Moore model? Explain.
Question 3 (20 pts.): Mod-4 counter is a sequential circuit that has two flip-flops A and B
and one input x. It consists of a combinatorial logic connected to the D flip-flops, as
shown in Figure below. Analyze the circuit:

a. (8 pts.) Derive the next state and output equations.


b. (8 pts.) Derive the state table of the sequential circuit.
c. (4 pts.) Draw the corresponding state diagram.

Dr. Gürtaç Yemişcioğlu Page| 2


EEE 248 CNG 232
Logic Design
21 SPRING 22
HWII

Question 4 (14 pts.):


a. (14 pts.) Given the sequential logic circuit below, complete the timing waveforms
for the outputs, assuming the storage elements have zero propagation delays.
Initial values of OUTA and OUTB are both logic ‘0’ as shown.

CLK
IN
OUTA
OUTB
b. (14 pts.) A new type of flip-flop called “G-flip-flop” is given below:

i. (8 pts.) Find the simplified characteristic equation of this G-flip-flop.


ii. (6 pts.) Fill in the following excitation table for G flip-flop.

Dr. Gürtaç Yemişcioğlu Page| 3


EEE 248 CNG 232
Logic Design
21 SPRING 22
HWII

Question 5 (16 pts.): Use rising edge triggered D-type Flip-Flops and any number and
type of combinational gates and building blocks, in order to design a 4-bit universal shift
register, for which a specification is provided below. Show the schematic of your design
CLEARLY with inputs CLK, CLEAR_B, S1, S0, LEFT_IN, RIGHT_IN, D[3:0], and outputs
Q[3:0].
Control Example to demonstrate the Next State when
S[1:0] Operation the Present State of the universal shift Register
is 0110
00 Shift Left 1100
01 Load New Data D[3:0] D[3:0] – 4 bit input
10 Hold 0110
11 Shift Right 0011

Dr. Gürtaç Yemişcioğlu Page| 4

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