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CMOS comb design examples

The document outlines the implementation of various logic functions in CMOS, focusing on XOR and other Boolean expressions. It details the number of transistors, logic levels, and gates required for each implementation, comparing different methods to achieve minimum transistor usage and logic levels. Additionally, it discusses the implications of using true and complemented input forms in circuit design.

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Anushka Vijay
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© © All Rights Reserved
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Download as PDF, TXT or read online on Scribd
2 views

CMOS comb design examples

The document outlines the implementation of various logic functions in CMOS, focusing on XOR and other Boolean expressions. It details the number of transistors, logic levels, and gates required for each implementation, comparing different methods to achieve minimum transistor usage and logic levels. Additionally, it discusses the implications of using true and complemented input forms in circuit design.

Uploaded by

Anushka Vijay
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Ex4: Implement a 2 I\P XOR in CMOS

Sol: F + A B + A B

F is not complemented and some of the I\P’s are complemented.


we need to do some logic transformations:

F= [ AB+AB] ( expand the 1st complement ) Æ F = (A+B)(A+B)

A A

B B

A B

A B

# of transistors = 12 T
# of logic levels = 2
# of gates = 3 (including two inverters for the inputs)
Another XOR implementation (basically as the complement of the XNOR i.e. A B+A B )

A B

B
A

A A

B B

Ex5) Implement F = A ( B + C + D ) + E Using minimum # of transistors.

Sol : F is not complemented and some I\P are complemented .


2 choices for logic transformation

F=A (B+C+D)+E

F has five literals (the occurrence of each variable in the Boolean expression is a literal
weather the variable is in true or complemented form). E.g. the 2 I/P XOR had 4
literals.

1 ) implement F then invert

Æ the # of T = 4 T ( to invert A & E )


+ 10T ( to implement the expression with “5literals”)
+ 2T to invert the O/P = 16T

3 logic levels , 4 Gates


2) Expand the 1st complement then implement F = [ A + C B D ] . E

# of T = 6 T for I\P : C , B & D inversions


+ 10T for expression = 16 T

# of gates = 4 gates
# of logic levels= 2

choose 2) since it has lower # of logic levels

VDD

B C D

B B A E

C C O/P

E
D D
VDD

C A

------------------------------

Ex6) Redo Ex5 assuming that inputs are available in true and complement form

Sol: first choice # of transistors = 10 T for expression


+ 2 T for O\P inverters

Æ 12 transistors Æ 2 gates Æ 2 logic levels


Second choice # of transistors = 10 T and 1 logic level (1 gate)
So we choose 2nd choice with no need for input inverters..
------------------------------------

Ex7) in the following PD block of a CMOS Gate, find the function of this circuit
& obtain the pull up (PU) block

O/P

A C E H

F = [ ( AB + C ) D + E ] G + H

PU:
Ex8) implement the following function in CMOS using minimum number of
logic levels

F={ [ (A +B) C +D ].E +G} H

Sol:

F={ [ (A +B) C +D ].E +G} H

= ((( AB+C ) . D ) + E ) G + H Æ 2 logic levels (function + input inverters)

VDD
C C
A B D G
D D

E E C

G G

E
H H

H
O/P

A C E H

B
VDD

G
Ex9) Redo Ex8 to obtain minimum number of T

Sol: now we will implement F & invert the output

Æ the # of T = 4 T to invert A & B

+ 14T to implement the expression


+ 2 to invert the output
= 20 T

Æ 20 Transistors Æ 3 logic levels

F = (((( A + B ) . C + D ) . E ) + G ) . H so implement F then invert

(to obtain the circuit schematic exchange the PMOS and NMOS blocks in the
previous circuit, and invert all I/Ps, e.g. A becomes A and C becomes C)

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