drain

COE 360
PMOS
impt output Principles of VLSI
NMOS Design
source
CWD
drain source gated tf
in positivevoltage
metaloxidesemiconductor
out in MOS Inverter
in out
out
oftwotransistorsconnectedonseries
consist
in notgateway inverters
in out MOSFET 6 5
out in
ground out Dr. Ahmed Youssef
logicgateIas
66,7404
bnotgates

1
 bitwiseoutput
glib input wi I'm
Review of Boolean Algebra
A Z A B Z A B Z A B Z A B Z
0 1 0 0 0 0 0 0 0 0 1 0 0 1
1 0 0 1 1 0 1 0 0 1 0 0 1 1
NOT 1 0 1 1 0 0 1 0 0 1 0 1
Truth Table
1 1 1 1 1 1 1 1 0 1 1 0
Z=A
OR AND NOR NAND
Truth Table Truth Table Truth Table Truth Table
Z = A+ B Z = AB Z = A+ B Z = AB
 two
Logic Voltage Level Definitions
Obama j
• VIL – The maximum input voltage that will be
recognized as a low input logic level

C
• VIH – The minimum input voltage that will be
recognized as a high input logic level tween I
• VOH – The output voltage corresponding to an input
voltage of VIL
• VOL – The output voltage corresponding to an input
voltage of VIH

3
 Inverter = NOT Gate

Vin
I Vout
Ideal Transfer Characteristics
Vout

D 1
Vin

A ideal inverter
 real MOS Inverter - Resistor Load
sitet g th t m o'm W

am voltages 15 É
6 IN a
loadresistance

real inverter
5
 MOS Inverter - Resistor Load
• VOH
MOS in Cutoff mode

VOH = VDD – ID RL

ID = 0

VOH = VDD

6
 VOL
• MOS in linear mode
K 2
• ID= 2(𝑉𝐺𝑆 −𝑉𝑇 )𝑉𝐷𝑆 − 𝑉𝐷𝑆
2
𝑉𝐷𝐷 − 𝑉𝐷𝑆
• ID=
𝑅𝐿
K 2 𝑉𝐷𝐷 − 𝑉𝐷𝑆
• 2(𝑉𝐺𝑆 −𝑉𝑇 )𝑉𝐷𝑆 − 𝑉𝐷𝑆 =
2 𝑅𝐿
• VDS=VOL VGS= VOH= VDD

7
 VOL
K 2 𝑉𝐷𝐷 − 𝑉𝑂𝐿
2(𝑉𝐷𝐷 −𝑉𝑇 )𝑉𝑂𝐿 − 𝑉𝑂𝐿 =
2 𝑅𝐿
We can neglect VOL2 because VOL small
K 𝑉𝐷𝐷 − 𝑉𝑂𝐿
2(𝑉𝐷𝐷 −𝑉𝑇 )𝑉𝑂𝐿 =
2 𝑅𝐿
We can solve this equation to find VOL
k 𝑅𝐿 (𝑉𝐷𝐷 −𝑉𝑇 ) 𝑉𝑂𝐿 = 𝑉𝐷𝐷 − 𝑉𝑂𝐿
k 𝑅𝐿 (𝑉𝐷𝐷 −𝑉𝑇 ) 𝑉𝑂𝐿 + 𝑉𝑂𝐿 = 𝑉𝐷𝐷
𝑉𝐷𝐷
VOL =
1+𝐾𝑅𝐿 (𝑉𝐷𝐷 −𝑉𝑇 )

8
 VIL
MOS in saturation mode
𝐾 2 𝐾 2
ID= 𝑉𝐺𝑆 − 𝑉𝑇 = 𝑉𝑖 − 𝑉𝑇 1)
2 2
𝑉𝐷𝐷 − 𝑉𝐷𝑆 𝑉𝐷𝐷 − 𝑉𝑜
ID= = 2)
𝑅𝐿 𝑅𝐿

dvo dvo dI D
= −1 . = −1
dvi dI D dvi
For eq1.

dI D
= k (Vi - VT )
dvi

9
 VIL
• For eq. 2

𝑑𝑣𝑖 −1
• =
𝑑𝐼𝐷 𝑅𝐿

• - 𝑅𝐿 𝑘 𝑉𝑖 − 𝑉𝑇 = −1

• 𝑅𝐿 𝑘 𝑉𝐼𝐿 − 𝑉𝑇 = 1

1
• VIL = 𝑉𝑇 +
𝐾𝑅𝐿

10
MOS Inverter - Resistor Load

11
 IWI was

VOH 𝑉𝐷𝐷
widrain 64126 0 IN osentoski R
PMOStransistor
I
𝑉𝐷𝐷 my Gokak
VOL
ÉEX 1 + 𝐾𝑅𝐿 (𝑉𝐷𝐷 − 𝑉𝑇 )
two W 64502 tag
transistor loadresistance thresholdvoltage

VIH 1 8𝑉𝐷𝐷
𝑉𝑇 − +
𝐾𝑅𝐿 3𝐾𝑅𝐿

1
VIL 𝑉𝑇 +
𝐾𝑅𝐿
12
 an
output
Icy
Effect of RL on VTC h

Main disadvantage of resistor load:

I
• occupies to much chip area (10s or 100s times the area of a
single transistor!)
13
 In A Example
• Consider a resistive load inverter circuit with
VDD=5 V, k = 40A/V2, VT=1V, and RL = 200 K
• Calculate VOH, VOL, VIH, VIL and find the noise
margins of the circuit.
Von Vpp 5V
VE 1tkÉ u 1140
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103
0.152V

t KittÉf t go.io oosIzxoxp

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YEUT Kk It 4oxioo 1.125V

14
 I 2am 0,411 m t stall a ta I l
F se im E WI I l l
Noise Margins
• Noise margins represent “safety margins” that
prevent the circuit from producing erroneous
outputs in the presence of noisy inputs
• Noise margins are defined for low and high
input levels using the following equations:
one’s output is the input of next stage

NML = VIL – VOL

in out
NMH = VOH – VIH
out in

15
Define noise margins:
NMH ≡ VOH - VIH
Noise margin high

NML ≡ VIL - VOL

Noise margin low

16
 oh Power Consumption

PDC average = ½ VDD ID

PDC (average) = ½ VDD [(VDD – VOL) / RL]
PDC average = ½ (VDD2/ (Req + RL))

VDD VDD

RL RL
O/P O/P

I/P Req=NMOS Req

I
 K Example

Consider the following inverter design problem, given

VDD=5V, μCox=20μa/V2, Vt = 0.8V, RL = 200kΩ, and
W/L = 2.
Calculate the critical voltages (VOH, VOL, VIL, VIH)
and the noise margin of the circuit

18
 K Example 1 -Solution

βn = K = (μ Cox) (W / L) = 40 μa/V2
βn RL = K RL = 8 V – 1
VOH = VDD = 5V
VOL = 0.144V
VIL = 0.925V
VIH = 1.97V

Noise Margin low (NML = VIL - VOL) = 0.925 – 0.144 = 0.781V

Noise Margin high (NMH = VOH - VIH) = 5 – 1.97 = 3.03V

19
 K Example 2
Consider a resistive load inverter with VDD=5V, Vt =
0.8V, and RL = 120K Ω. Suppose that the average DC
power dissipation is 100 μW. Determine the values
of VIL and Vout(VIL)
 K Example 3

Consider the following inverter design problem, given

VDD=5V, μCox=30μa/V2, Vt = 1V.
Design a resistive load inverter with VOL = 0.2V
Determine the (W/L) ratio of the transistor and the load
resistor RL that achieve the required VOL

21
 Example 3 -Solution
K
The transistor operates in linear region when VO = VOL and
Vin = VOH = VDD
(VDD – VOL) / RL = (μ Cox / 2) (W / L) [2(VOH – Vt) VOL – VOL 2]
Assuming VOL = 0.2V substitute in the last equation
(W/L) RL = 2.05 * 105 Ω
The selection of (W/L) and RL depends on the trade off between
The power consumption of the circuit
The silicon area

22
 K Example 4
Design a Resistive – load inverter with VOH = 5V, VOL =
0.2V and average DC power 250µW. Assume that Vtn =
1V and µn COX = 50.5µA/V2. Assume that the used
technology is 0.5µm
 NMOS NAND Gate
consistoftwoNMOStransistorsconnected inseries
• Output is low only if both inputs are high
VDD

WN
drain source gated to
RD
Foutput
drain
inputA NMOStransistor

source

drain
Truth Table
A B F
inputB NMOStransistor 0 0 1
source 0 1 1
1 0 1
1 1 0
 NMOS NOR Gate
consistoftwoNMOStransistorsconnected in parallel
• Output is low if either input is high
VDD
WN
rain source gate
tf
RD
F

A Ty B Tz
Truth Table
A B F
0 0 1
0 1 0
1 0 0
1 1 0
 COE 360
Principles of VLSI
Design

Complementary Metal Oxide Semiconductor

CMOS
Logic Gates

Dr. Ahmed Youssef

 CMOS Technology
• Complementary MOS, or CMOS, needs
both PMOS and NMOS devices for their
logic gates to be realized
 Complementary MOS (CMOS)
• N-Channel and P-Channel transistors can be
fabricated on the same substrate as shown below
 MOS Circuit Symbols
• The gate of a MOS transistor controls the flow of the current
between the drain and the source.
• The MOS transistor can be viewed as a simple ON/OFF switch.
 MOS Circuit Symbols
• Series behavior of MOS transistors
nMOS: 1 = ON
pMOS: 0 = ON

Series:
both must be ON
 MOS Circuit Symbols
• Parallel behavior of MOS transistors
nMOS: 1 = ON
pMOS: 0 = ON

Parallel:
either can be ON nMOS

pMOS
 Transistors in Series/Parallel
nMOS in Series nMOS in Parallel
a a Path between a a Path between
X X:X points a and b points a and b
exists if both X Y exists if either
X:X Y:Y
X and Y are 1 X or Y are 1
Y Y:Y → X•Y → X+Y
b b b b

pMOS in Parallel pMOS in Series

a a Path between a a
points a and b Path between
X X:X’ points a and b
X Y exists if either
X:X Y:Y exists if both
X or Y are 0
→ X’+Y’ X and Y are 0
→ (XY)’ Y → X’•Y’
Y:Y’
b b → (X+Y)’
b b

32
 Networks of Switches (cont.)
In general:
– NMOS in series is used to implement AND logic
– PMOS in parallel is used to implement NAND logic

– NMOS in parallel is used to implement OR logic

– PMOS in series is used to implement NOR logic

33
 CMOS Inverter
• CMOS gates are built around the technology
of the basic CMOS inverter:
Vdd

PMOS
in out
in out
NMOS

Symbol

Circuit
 Basic CMOS Logic Technology
• Transistors (two) are
enhancement mode MOSFETs Vdd
s
– N-Channel with its source g
PMOS
grounded d
in out
– P-Channel with its source d
connected to +V g NMOS
s
• Input: gates connected together
• Output: drains connected
 CMOS Inverter - Operation
When input A is grounded (logic
0), the N-MOS is unbiased (off). VDD
It is an open circuit.
Charge
A
At the same time, the PMOS is
forward biased, connecting the Open
output line to the +VDD supply.
This pulls the output up to +VDD
(logic 1).
 CMOS Inverter - Operation
When input A is at +VDD (logic 1),
the PMOS is off and the NMOS is
on, thus pulling the output down to VDD
VDD
ground (logic 0). Open
Out
A

Discharge
 CMOS Inverter

A Y VDD
0
1

A Y

A Y
GND
38
 CMOS Inverter

A Y VDD
0
1 0 OFF
A=1 Y=0

ON
A Y
GND
 CMOS Inverter

A Y VDD
0 1
1 0 ON
A=0 Y=1

OFF
A Y
GND
CMOS Inverter – A Switch Model

a) Circuit schematic for a CMOS inverter

b) Simplified operation model with a high input applied
c) Simplified operation model with a low input applied
 CMOS NAND Gate
A B Y
0 0
0 1
1 0
1 1
 CMOS NAND Gate
A B Y
0 0 1 ON ON
0 1 Y=1
A=0
1 0 OFF
1 1
B=0
OFF

43
 CMOS NAND Gate
A B Y
0 0 1 OFF ON
0 1 1 Y=1
A=0
1 0 OFF
1 1
B=1
ON

Slide 44
 CMOS NAND Gate
A B Y
0 0 1 ON OFF
0 1 1 Y=1
A=1
1 0 1 ON
1 1
B=0
OFF

Slide 45
 CMOS NAND Gate
A B Y
0 0 1 OFF OFF
0 1 1 Y=0
A=1
1 0 1 ON
1 1 0
B=1
ON

Slide 46
 3-input NAND Gate
• Y pulls low if ALL inputs are 1
• Y pulls high if ANY input is 0

Y
A
B
C

Slide 47
 CMOS NOR Gate
A B Y
0 0 1 A
0 1 0
1 0 0 B
1 1 0 Y

Slide 48
 CMOS Gate Design
• A 4-input CMOS NOR gate

A
B
C
D
Y
 COE 360
Principles of VLSI
Design

CMOS
Combinational Logic Circuits

50
 Pull-Up and Pull-Down Network
• CMOS network consists of a Pull-UP Vdd
Network (PUN) and a Pull-Down
Network (PDN)
• PUN consists of a set of PMOS PUN

transistors
• PDN consists of a set of NMOS ….
OUPTUT
transistors
I0
• PUN and PDN implementations are I1
PDN
complimentary to each other
– PMOS  NOMS In-1
– Series topology  Parallel topology
Gnd

51
 Gate Symbol of a CMOS Inverter
Vdd

A B A B

B=Ā

Gnd

CMOS Inverter

52
 How about an AND gate
Vdd

Vdd
A B

C A
C

A B

B C=AB
Gnd

Inverter
NAND
53
 An OR Gate
Vdd

A
Vdd

B
C A
C

B
A B
C=A+B
Gnd

Inverter
NOR
54
 A Systematic Method (I)
Start from Pull-Up Network
• Each variable in the given Boolean eq. corresponds to a
PMOS transistor in PUN and an NMOS transistor in
PDN
• Draw PUN using PMOS based on the Boolean eq.
– AND operation drawn in series
– OR operation drawn in parallel
• Invert each variable of the Boolean eq. as the gate input
for each PMOS in the PUN
• Draw PDN using NMOS in complementary form
– Parallel (PUN) to series (PDN)
– Series (PUN) to parallel (PDN)
• Label with the same inputs of PUN
• Label the output
55
 Example 1 (Method I)
Vdd
In parallel

F = AC + B
In series

(1) Draw the Pull-Up Network

56
 Example 1 (Method I)
Vdd
In parallel
A B
F = AC + B
In series C

(2) Assign the complemented input

57
 Example 1 (Method I)
Vdd
In parallel
A B
F = AC + B
In series C

(3) Draw the Pull-Down Network in

the complementary form C
A

58
 Example 1 (Method I)
Vdd
In parallel
A B
F = AC + B
In series C

(3) Draw the Pull-Down Network in

the complementary form C
A

59
 Example 1 (Method I)
Vdd
In parallel
A B
F = AC + B
In series C

F
Label the output F
A C

60
 Example 1 (Method I)
Vdd
In parallel
A B
F = AC + B
In series C

A C

61
 XNOR Gate (Method I)
Vdd
Truth Table
A B C
A A
0 0 1
0 1 0
B B
1 0 0
1 1 1
C

A A B
C

A B
C = AB+ AB
62
 Example 3
F = A  D + B  (A + C)
A C A

Start from the innermost term

B D

A D

63
 Example 3
F = A  D + B  (A + C)
A C A

Start from the innermost term

B D

A D

64
 Example 3
F = A  D + B  (A + C)
A C A

Start from the innermost term

B D

A D

A
B
C

65
 Example 3 Vdd
F = A  D + B  (A + C)
A C A
Pull-Up
Start from the innermost term Network
B D

A D

Pull-Down
A Network
B
C

66
 Example 4
Vdd
F = (E + D)  (A  D + B  (A + C))
E D

Start from the innermost term Pull-Up

A C A Network

B D
F

A D E
Pull-Down
Network
A
B D
C

67
 Another Example

F = AC + B How ??

68
 A Systematic Method (II)
Start from Pull-Down Network

• Each variable in the given Boolean eqn corresponds to a PMOS

transistor in PUN and an NMOS transistor in PDN
• Invert the Boolean eqn
• With the Right-Hand Side of the newly inverted equation, Draw
PDN using NMOS
– AND operation drawn in series
– OR operation drawn in parallel
• Label each variable of the Boolean eqn as the gate input for each
NMOS in the PDN
• Draw PUN using PMOS in complementary form
– Parallel (PUN) to series (PDN)
– Series (PUN) to parallel (PDN)
• Label with the same inputs of PUN
• Label the output
69
 Drawing the Schematic using Method II
F = AC + B Vdd

A B
F = AC + B
C
F = ACB
F
F = (A + C)  B
A C

B
This is exactly the same
CMOS network with the
schematic by Method I

70
 Fully Complementary CMOS Networks
Complex Gates - Example

F = (A+B)(A+C’)
F’ = A’B’+A’C=A’(B’+C)

13-Mar-23 71
 Compound Gates
• Lets take a
look at a
gate that
implements
a more
complex
function …
 Compound Gates
• Compound gates can do any inverting function
• Ex: Y = A •B +C •D
A C A C
B D B D
(a) (b)

C D
A B C D
A B
(c)
(d)

C D
A
A B
B
Y Y
C
A C
D
B D
(f)

(e)
 Example

• Y = ( A + B + C) D

A
B
C D
Y
D
A B C
 Complex CMOS Gate
Vdd

B
A
C

D
OUT = D + A • (B + C)
A
D
B C

75
Complex CMOS Structures

76
Complex CMOS Gate

B
A
C

D
OUT = (D + A • (B + C))
A
D
B C
 Standard Naming of Logic Functions
A combination of letters and numbers are used to describe the
function and the number of I/Ps.
Letters: A = AND, O = OR, I = Invert
AOI = AND/OR/Invert
OAI = OR/AND/Invert.

Ex1. AOI 222: 3 AND terms, that are ORed then Inverted
We have 3 logic terms each has 2 I/Ps.
F = (1.2) + (3.4) + (5.6)

Ex2. OAI 123 → 3 OR terms that are Anded then Inverted

F = 1.(2+3).(4+5+6)
 AOI example

Inverter

OR

AND

80
 OAI22 Logic Graph

A C OR AND Inverter
B D

X = (A+B)•(C+D)

C D

A B
A
B
C
D

81
 OAI21 Logic Graph
A
j C
B

X = (C • (A + B))
C
i

A B
A
B
C
 Concept of Fan in and Fan out
• Fan in
– The fan in of any complex gate is defined as the number of
inputs of this gate
• Fan out
– The fan out of a complex gate is defined as the number of
driven inputs attached to the output of this gate

N N

Fanout=N Fanin=N

83
Concept of Fan in and Fan out
Basic Specifications of Digital Circuits