Thapar institute of engineering &

TECHNOLOGY, patiala

Course Name : Digital System Design

Course Code : UEC612

Semester : III Semester

 DIGITAL SYSTEM DESIGN UEC612
LIST OF EXPERIMENTS
S. EXPERIMENTs CO
No.
1 Modeling and simulation of 4-to-1 multiplexer using Structural style of coding. CO-1

2 Modeling and simulation of 4-to-1 multiplexer using Behavioral style of coding. CO-1

3 Modeling and simulation of a 4-bit Arithmetic Logic Unit (ALU) that provides the CO-2
following functionalities: addition (A+B), subtraction (A-B), logical operations
(AND, OR, NOT, NAND, NOR and XOR).

4 Modeling and simulation of a 4-bit Serial-In-Parallel-Out shift register using D flip CO-3
flop as a component.

5 Synthesis and implementation of 2-bit Arithmetic Logic Unit (ALU) on FPGA CO-5
Board.

6 Demonstrate the different operations of 4-bit universal shift register IC-74194. CO-4

7 Design a 4-bit binary ripple counter using 7473 JK flip flop ICs. Demonstrate its CO-4
outputs on Mixed Signal Oscilloscope (MSO).

8 Mini Project: Using Verilog Model, Simulate, Synthesize and Test on any FPGA CO-
board the given Standard IC. Your model should be pin compatible and functionally 1-5
verifiable. You may ignore time delays like Set-up, Hold, Propagation delay, etc.
(Use the Data Sheet)

Note: It will require 3 laboratory classes. List of projects are available in the
lab manual.

Course Outcomes (COs)

CO-1: Design the basic logic functions after simplification of expressions.
CO-2: Design the combinational circuits using basic modules, iterative networks.
CO-3: Design flip flops and sequential systems.
CO-4: Compare the performance of a given digital circuits/systems with respect to
their speed, power consumption, number of ICs, and cost.
CO-5: Design, model and simulate the digital systems using VHDL or Verilog.

Course Coordinator
Dr. Alpana Agarwal
Professor DECE|TIET
Program Educational Objectives (PEOs)
Our graduates are expected to:
 Promote excellence in professional engineering practices by applying their
technical knowledge and problem-solving skills.

 Thrive in enhancement of intellectual ability, team skills and lifelong learning by

pursuing higher education / professional acumen.

 Attain leadership roles in their career as an ethical and responsible professional

while working innovatively and diligently for societal development.

Program Specific Outcomes (PSOs)

 Core Competency: Ability to apply the fundamentals of mathematics, science and
engineering knowledge to identify, formulate, design and investigate complex
engineering problems of analog and digital electronics circuits, signal processing,
communication and computational tools.

 Practical Competency: Apply the appropriate engineering techniques using

modern hardware and software tools in electronic and communication engineering
to engage in life-long learning, being ethical to successfully adapt in multi-
disciplinary environment.
 EXPERIMENT NO. 1

Aim: Modeling and simulation of 4-to-1 multiplexer using structural style of coding.

Circuit Diagram of 4-to-1 multiplexer:

Perform the following activities.

Activity-1: Write the Verilog code for 4-to-1 multiplexer and check the syntax errors if any.
 EXPERIMENT NO. 2

Aim: Modeling and simulation of 4-to-1 multiplexer using behavioral style of coding.

Diagram of 4-to-1 multiplexer:

Perform the following activities.

Activity-1: Write the Verilog code for 4-to-1 multiplexer and check the syntax errors if any.
 EXPERIMENT NO. 3

Aim: Modeling and simulation of a 4-bit Arithmetic Logic Unit (ALU) that provides the
following functionalities: addition (A+B), subtraction (A-B), logical operations (AND, OR,
NOT, NAND, NOR and XOR).

Perform the following activities.

Activity 1: Write the Verilog Code for 4-bit ALU design. Check syntax errors if any and
correct them.
 EXPERIMENT NO. 4

Aim: Modeling and simulation of a 4-bit Serial-In-Parallel-Out shift register using D flip flop
as a component.

Circuit Diagram of Serial-In-Parallel-Out shift register:

Perform the following activities.

Activity 1: Write the Verilog Code for D flip flop.

Activity 2: Write the Verilog Code for 4-bit Serial-In-Parallel-Out shift register using above
designed D flip flop as a component.
 EXPERIMENT NO. 5
Aim: Synthesis and implementation of 2-bit Arithmetic Logic Unit (ALU) on FPGA Board.

Perform the following activities.

Fig. SPARTAN-6 FPGA Board

Activity 1: Set the Spartan 6 FPGA device family, device, package and grade.
Activity 2: Write the Verilog Code for 2-bit ALU design. Check syntax errors if any and
correct them.

Activity 3: Create the user constraint file and map the ALU inputs and outputs.
Activity 4: In the UCF file map the ALU inputs and outputs with FPGA boards input switches
and output LEDs.

 Perform the implementation.

 Generate the configuration file i.e. .bit file.

Activity 5: Download the .bit file in the FPGA board.

 Run the manage configuration project. It will open iMPACT window

 Run the boundary scan and initialize the chain. It will open configuration window.

 Click Yes in configuration window

 Locate the .bit file i.e. .alu and open it

  Program the device

Activity 6: Apply the inputs on switches and verify the outputs on LEDs
 EXPERIMENT NO. 6

Aim: Demonstrate the different operations of 4-bit universal shift register IC-74194.

PIN Diagram of 74194:

Perform the following activities.

Activity-1: Parallel Load operation

Activity-2: Left shift and right shift operations
Activity-3: Hold operation
 EXPERIMENT NO. 7

Aim: To design a 4-bit binary ripple counter using 7473 JK flip flop ICs. Demonstrate its
outputs on the Mixed Signal Oscilloscope (MSO).

PIN Diagram of 7473:

Perform the following activities.

Activity-1: Design a 4-bit simple binary counter with a clear input. Display its outputs on
the MSO.
 Thapar Institute of Engineering and Technology, Patiala
Department of Electronics and Communication Engineering
UEC612: Digital System Design
Projects
Instructors: Dr.Alpana Agarwal, Dr. Manu Bansal & Dr Anil Singh

Using Verilog Model, Simulate, Synthesize and Test on any FPGA board the given Standard
IC. Your model should be pin compatible and functionally verifiable. You may ignore time
delays like Set-up, Hold, Propagation delay, etc. (Use the Data Sheet)

S. No Standard
Description
IC Number
1. 74x42 BCD to decimal decoder
2. 74x43 excess-3 to decimal decoder
3. 74x44 Gray code to decimal decoder
4. 74x45 BCD to decimal decoder/driver
5. 74x48 BCD to 7-segment decoder/driver
6. 74x56 50:1 frequency divider
7. 74x57 60:1 frequency divider
8. AND gated J-K master-slave flip-flop, asynchronous preset and clear
74x67
(improved 74L72)
9. dual J-K flip-flop, asynchronous clear (improved 74L73)
74L68

10. 74LS68 dual 4-bit decade counters

11. dual J-K flip-flop, asynchronous preset, common clock and clear
74L69

12. 74LS69 dual 4-bit binary counters

13. AND-gated positive edge triggered J-K flip-flop, asynchronous
74x70
preset and clear
14. 74H71 AND-OR-gated J-K master-slave flip-flop, preset
15. AND-gated R-S master-slave flip-flop, preset and clear
74L71

16. AND gated J-K master-slave flip-flop, asynchronous preset and clear
74x72

17. 74x73 dual J-K flip-flop, asynchronous clear

18. dual D positive edge triggered flip-flop, asynchronous preset
74x74
and clear
19. 74x76 dual J-K flip-flop, asynchronous preset and clear
20. 74x77 4-bit bistable latch
21. dual positive pulse triggered J-K flip-flop, preset, common clock and
74H78
common clear
22. dual positive pulse triggered J-K flip-flop, preset, common clock and
74L78
common clear
23. dual negative edge triggered J-K flip-flop, preset, common clock and
74LS78
common clear
24. dual D positive edge triggered flip-flop, asynchronous preset
74x79
and clear
25. 74x83 4-bit binary full adder
26. 74x85 4-bit magnitude comparator
27. decade counter (separate divide-by-2 and divide- by-5 sections)
74x90

28. 74x91 8-bit shift register, serial in, serial out, gated input
29. divide-by-12 counter (separate divide-by-2 and divide-by-6
74x92
sections)
30. 4-bit binary counter (separate divide-by-2 and divide-by-8
74x93
sections); different pinout for 74L93
31. 74x94 4-bit shift register, dual asynchronous presets
32. 4-bit shift register, parallel in, parallel out, serial input; different
74x95
pinout for 74L95
33. 5-bit parallel-in/parallel-out shift register, asynchronous preset
74x96

34. AND-OR-gated J-K negative-edge-triggered flip-flop, preset

74x101

35. AND-gated J-K negative-edge-triggered flip-flop, preset and clear

74x102

36. 74x103 dual J-K negative-edge-triggered flip-flop, clear

37.
74x104 J-K master-slave flip-flop

38. 74x105 J-K master-slave flip-flop, J2 and K2 inverted

39. dual J-K negative-edge-triggered flip-flop, preset and clear
74x106

40. 74x107 dual J-K flip-flop, clear

41. dual J-K negative-edge-triggered flip-flop, preset, common clear and
74x108
common clock
42. dual J-NotK positive-edge-triggered flip-flop, clear and preset
74x109

43. dual J-K master-slave flip-flop, data lockout, reset, set

74x111

44. dual J-K negative-edge-triggered flip-flop, clear and preset

74x112

45. 74x113 dual J-K negative-edge-triggered flip-flop, preset

46. dual J-K negative-edge-triggered flip-flop, preset, common clock and
74x114
clear
47. 74x115 dual J-K master-slave flip-flop, data lockout, reset
48. 74H120 dual J-K flip-flop, separate clock inputs
49. 3-to-8 line decoder/demultiplexer, inverting outputs
74x138

50. dual 2-to-4 line decoder/demultiplexer, inverting outputs

74x139

51. 74x144 decade counter/latch/decoder/7-segment driver

52. 74x145 BCD to decimal decoder/driver
53. 74x146 3-to-8 line decoder
54. 74x147 10-line to 4-line priority encoder
55. 74x148 8-line to 3-line priority encoder
56. 74x149 8-line to 8-line priority encoder
57. 74x150 16-line to 1-line data selector/multiplexer
58. 74x151 8-line to 1-line data selector/multiplexer
59. 8-line to 1-line data selector/multiplexer, inverting output
74x152

60. 4-to-16 line decoder/demultiplexer, inverting outputs

74x154

61. 74x159 4-to-16 line decoder/demultiplexer

62. synchronous presettable 4-bit decade counter, asynchronous clear
74x160

63. synchronous presettable 4-bit binary counter, asynchronous clear

74x161

64. synchronous presettable 4-bit decade counter, synchronous clear

74x162

65. synchronous presettable 4-bit binary counter, synchronous clear

74x163

66. 8-bit serial-in parallel-out (SIPO) shift register, asynchronous clear,

74x164
not output latch
67. 8-bit parallel-in serial-out (PISO) shift register, parallel load,
74x165
complementary outputs
68. 74x166 parallel-load 8-bit shift register
69. 74x167 synchronous decade rate multiplier
70. synchronous presettable 4-bit up/down decade counter
74x168

71. synchronous presettable 4-bit up/down binary counter

74x169

72. 74x176 presettable decade (bi-quinary) counter/latch

73. 74x177 presettable binary counter/latch
74. 74x180 9-bit odd/even parity bit generator and checker
75. 74x184 BCD to binary converter
76. 74x185 6-bit binary to BCD converter
77. synchronous presettable up/down 4-bit decade counter, clear
74x192

78. synchronous presettable up/down 4-bit binary counter, clear

74x193

79. 74x194 4-bit bidirectional universal shift register

80. 74x196 presettable 4-bit decade counter/latch
81. 74x197 presettable 4-bit binary counter/latch
82. 74x198 8-bit bidirectional universal shift register
83. 74x199 8-bit universal shift register, J-NotK serial inputs
84. 3-to-8 line decoder/demultiplexer, active high outputs
74x238

85. 8-line to 1-line data selector/multiplexer, complementary outputs

74x251

86. 4-bit cascadeable priority registers, latched data inputs

74x278

87. 74x280 9-bit odd/even parity bit generator/checker

88. 74x283 4-bit binary full adder (has carry in function)
89. 9-bit parity generator/checker, bus driver parity I/O port
74x286

90. decade counter (separate divide-by-2 and divide- by-5 sections)

74x290

91. 4-bit binary counter (separate divide-by-2 and divide-by-8

74x293
sections)
92. 74x295 4-bit bidirectional shift register
93. 74x299 8-bit bidirectional universal shift/storage register
94. 8-bit bidirectional universal shift/storage register, synchronous
74x323
clear
95. 74x348 8 to 3-line priority encoder
96. 74x350 4-bit shifter
97. 8-line to 1-line data selector/multiplexer, edge- triggered registers
74x356

98. 74x377 8-bit register, clock enable

99. 74x378 6-bit register, clock enable
100. 4-bit register, clock enable and complementary outputs
74x379

101. 74x388 4-bit D-type register

102. 74x395 4-bit cascadable shift register
103. 74416 modulo 10 counter, preload and clear inputs
104. modulo 2 and modulo 5 counters, common preload and clear inputs
74x417

105. 74418 modulo 16 counter, preload and clear inputs

106. 74F418 32-bit error detection and correction circuit
107. 74LS460 10-bit comparator
108. 74x461 8-bit presettable binary counter
109. 8-bit synchronous up/down counter, parallel load and hold
74x469
capability
110. 74x498 8-bit bidirectional shift register, parallel inputs
111. 74x538 3-to-8 line decoder/demultiplexer
112. 74x560 4-bit decade counter
113. 74x561 synchronous 4-bit binary counter
114. 74x568 decade up/down counter
115. 74x569 binary up/down counter
116. 74x579 8-bit bidirectional binary counter
117. 74x582 4-bit BCD arithmetic logic unit
118. 74x583 4-bit BCD adder
119. 8-bit shift registers, serial-in, parallel-out, output latches
74x594

120. 8-bit shift registers, serial-in, parallel-out, output latches, output

74x595
enable
121. 8-bit shift registers, parallel-in, serial-out, input latches
74x597

122. 8-bit shift register, selectable parallel-in/out input latches

74x598

123. 8-bit shift registers, serial-in, parallel-out, output latches

74x599

124. 74x668 synchronous 4-bit decade up/down counter

125. 74x669 synchronous 4-bit binary up/down counter
126. 4-bit bidirectional shift register/latch/multiplexer, direct clear
74x671

127. 4-bit bidirectional shift register/latch/multiplexer, synchronous

74x672
clear
128. 16-bit serial-in, serial/parallel-out shift register, output storage
74x673
registers
129. 74x674 16-bit parallel-in, serial-out shift register
130. 74x675 16-bit serial-in, serial/parallel-out shift register
131.
74x676 16-bit serial/parallel-in, serial-out shift register

132. 74x681 4-bit parallel binary accumulator

133. 74x682 8-bit magnitude comparator, P>Q output
134. 74x686 8-bit magnitude comparator, P>Q output, enable
135. 74x688 8-bit magnitude comparator, enable
136. 4-bit decimal counter/latch/multiplexer, asynchronous clear
74x690

137. 4-bit decimal counter/latch/multiplexer, synchronous clear

74x692

138. 4-bit decimal counter/latch/multiplexer, synchronous and

74x694
asynchronous clears

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