es i ’ Embedded Systems aL OS eS Cale RUST LD) Simplified & Conceptual Approach ¢ 2 Marks Questions with Answers ¢ Chapterwise Solved AU Questions Dec. 2004 to Dec. 2019 e Solved Model Question Paper(As Per New Syllabus) 3 TECHNICAL PUBLICATIONS An Up-Thrust for KnowledgeDS Sudha SUBJECT CODE : CS3691 Striclly as per Revised Syllabus of ANNA UNIVERSITY Choice Based Credit System (CBCS) Semester - V (IT / CS & BS) Semester - VI (CSE / Al & DS) EMBEDDED SYSTEMS AND IOT Iresh A. Dhotre M.E. (Information Technology) Ex-Foculty, Sinhgad College of Engineering, Pune Atul P Godse M.S. Software Systems (BITS Pilani) B.E. Industrial Electronics Formerly Lecturer in Department of Electronics Engg. Vishwakarma Institute of Technology Pune aeRO e 2 TECHNICAL PUBLICATIONS An Up-Thrust for KnowledgePREFACE The importance of Embedded Systems and IoT is well known in various engineering fields. Overwhelming response to our books on various subjects inspired us to write this book. The book is structured to cover the key aspects of the subject Embedded Systems and loT, | The book uses plain, lucid language to explain fundamentals of this subject. The book provides logical method of explaining various complicated concepts and stepwise methods to explain the important topics. Each chapter is well supported with necessary illustrations, practical examples and solved problems. All the chapters in the book are arranged in a proper sequence that permits each topic to build upon earlier studies. All care has been taken to make students comfortable in understanding the basic concepts of the subject. Representative questions have been added at the end of section to help the students in picking important points from that section. The book not only covers the entire scope of the subject but explains the philosophy of the subject. This makes the understanding of this subject more clear and makes it more interesting. The book will be very useful not only to the students but also to the subject teachers. The students have to omit nothing and possibly have to cover nothing more. We wish to express our profound thanks to all those who helped in making this book a reality. Much needed moral support and encouragement is provided on numerous occasions by our whole family. We wish to thank the Publisher and the entire team of Technical Publications who have taken immense pain to get this book in time with quality printing. Any suggestion for the improvement of the book will be acknowledged and well appreciated Authors DA. Dhotve A.D. Godse Dedicated to God. i)SYLLABUS Embedded Systems and IoT - (CS3691) UNITI 8 - BIT EMBEDDED PROCESSOR 8 - Bit Microcontroller - Architecture - Instruction Set and Programming - Programming Paral, Ports - Timers and Serial Port - Interrupt Handling. (Chapters - 1, 2, 3) UNIT IL EMBEDDED C PROGRAMMING Memory And I/O Devices Interfacing - Programming Embedded Systems in C - Need For RTOS - Multiple Tasks and Processes - Context Switching - Priority Based Scheduling Policies (Chapter - 4) UNIT IIL IOT AND ARDUINO PROGRAMMING Introduction to the Concept of IoT Devices - loT Devices Versus Computers - IoT Configurations - Basic Components - Introduction to Arduino - Types of Arduino - Arduino Toolchain - Arduino Programming Structure - Sketches - Pins - Input / Output From Pins Using Sketches - Introduction to Arduino Shields - Integration of Sensors and Actuators with Arduino. (Chapter - 5) UNIT IV IOT COMMUNICATION AND OPEN PLATFORMS ToT Communication Models and APIs - IoT Communication Protocols - Bluetooth - WiFi - ZigBee - GPS - GSM modules - Open Platform (like Raspberry Pi) - Architecture - Programming - Interfacing ~ Accessing GPIO Pins - Sending and Receiving Signals Using GPIO Pins - Connecting to the Cloud. (Chapter - 6) UNIT V APPLICATIONS DEVELOPMENT Complete Design of Embedded Systems - Development of IoT Applications - Home Automation - Smart Agriculture - Smart Cities - Smart Healthcare. (Chapter - 7) i)TABLE OF CONTENTS es Chapter-1 — 8-Bit Microcontroller Architecture (1 - 1) to (1 - 20) 1.1 Introductior ~1-2 re 1.2 Features of 8051 Microcontrolle! 1.3 Architecture of 8051 1.3.1 Central Processing Unit (CPU)... 1.3.2 Aand B CPU Registers..... Data Pointer (DPTR)..... The Program Counter. 8051 Flag Bits and the PSW Register... Special Function Register of 8051 .. 1.4 Pin Description of 8051... 1.5 _ Internal and External Memories . 1.5.1 Internal RAM Organization... 1.5.1.1 8051 Register Banks (Working Registers) ...n.sennnnnnennnnnnnnnse be MG 1.5.1.2 Bit / Byte Addressable ..rssmsnnnsmnnnnnnnnninisse 1-14 1.5.1.3 General Purpose RAM wa... 1-14 15.2 ROM Space in the 8051... 1-14 1.6 Stack and Stack Pointer...... oe 15 1.7 Two Marks Questions with Answers ... 1-16 Chapter - 2 Instruction Set and Programming (2 - 1) to (2 - 38) 2.1 8051 Addressing Modes... 2.1.1 Register Addressing.. 2.1.2 Direct Byte Addressing....... 2-2 2.1.3 Register Indirect Addressing 2-3 2.14 Immediate Addressing 2-3 w)1S Register Specific 16 index LLT Stack Addressing Mode 22 Classification of instruction Set of 8051. 2.3 Data Transfer instructions....... 131 instructions to Access External Data Memory Instructions to Access External ROM/Program Memory. Data Transfer with Stack (PUSH and POP) Instructions 232 233 234 Data Exchange Instructions. 24 Byte Level Logical Instructions ... 25 Arithmetic instructions... 25.1 incrementing and Decrementing 252 Addition. 253 Subtraction. 254 Multiplication and Division .... 255 Decimal Arithmetic.. 25 Bit Level Logical Instructions... 27 Rotate and Swap Instructions .... 22 Jump and CALL Instructions ... 221 jump and Call Program Range... 242 sump... 243° ChLLand Subroutines. 23 Time Delay for 205: 2.10 Program Examples. 2.11 Two Marks Questions with Answers Chapter-3 Parallel Ports, Timers, Serial Port and Interrupts (3 - 1) to (3- od 2.1 20511/0 Ports Structure .. (a| | | 3.2 1/0 Bit Manipulation Programming... 3.3, 8051 Timers.. 3.3.1 Structure of TMOD Register... 3.3.2 Structure of TCON Register 3.4 8051 Timer Modes and Programming .. 3.5 8051 Counter Programming... 3.5.1 Programming Timers in 8051 C.. 3.6 8051 Serial Port 3.6.1 Operating Modes for Serial Port Generating Baud Rates Programming 8051 for Serial Data Transfer Programming 8051 for Receiving Data Serially. Doubling the Baud Rate in the 8051 .. 8051 Connection to RS 232C. 3.6.7 Serial Communication Programming in C.m.rmrnnninnnntrnnrnnnnnns 3-59 3.7 8051 Interrupt Structure .. 3.7.1 _ Interrupt Control (Enabling and Disabling Interrupts using IE)... 3.7.2 _ Interrupt Priority and Interrupt Destinations (Vector Locations) ......u-3 - 66 3.8 Programming Interrupts... 3.8.1 Programming Timer Interrupts .... 3.8.2 Programming External Hardware Interrupts ... 3.8.3 Programming the Serial Communication Interrupts .. 3-71 3.9 Two Marks Questions with Answers Chapter-4 Embedded C Programming (4-1) to (4 - 64) 4.1 Memory Interfacing... eee And 4.1.1 _ Interfacing and Timing Diagrams for Memory Interfacing... woh 2 4.1.1.1 External Program Memory ae 4-4 4.1.1.2 External Data Memory .. (wit)4.1.1.3 Important Points to Remember in Accessing External Memory... 4.1.2 Memory Address Decoding. _ ‘ 4.1.3 Interfacing Examples.. . 4.1.4 Accessing External Data Memory in 8051C. i 4.2. 1/0 Devices Interfacing..... hy 4.2.1 Keyboard Interfacing. —_ 4.2.1.1 Key Debounce using Hardware ... - 4.2.1.2. Key Debouncing using Software... 4.2.1.3 Simple Keyboard Interface 4.2.1.4 Matrix Keyboard Interface ... 4.2.2 LED Interfacing -u 4.2.3 Multiplexed 7-Segment Display Interfacing, ZB 4.2.3.1 Interfacing LED Displays... 4-% 4.2.4 LCD Interfacing... 4.3 Programming Embedded Systems in C 4.3.1 Difference between C Language and Embedded C... 4.4 Need for RTOS.. 44.1 _ Difference between Hard and Soft Real Time System. 44.2 RealTime OS... 4.4.3 Qualities of Good RTOS.. 4.4.4 — Characteristics of RTOS... 4.4.5 How to Choose RTOS... 4.5 Multiple Tasks and Processes, 45.1 Multirate Systems. 45.2 Process State and Scheduling... 45.3 Scheduling Policies..... 4.6 Context Switching, 4.7 Priority Based Scheduling Policies. 471 Earliest-Deadline-First Scheduling 4.7.2 Rate Monotonic Scheduling eT ——__ (wi)48 4.7.2.1 Comparison between RMS and EDF... 47.3 Priority inversion. Two Marks Questions and Answers. Chapter-5 — IoT and Arduino Programming (5 - 1) to (5 - 32) 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 Introduction to the Concept of loT Devices 5.1.1 loT System Building Blocks.. 5.1.2 loT Devices Versus Computers... Introduction to Arduino .. 5.2.1 Features of Arduino Board.. Types of Arduino .... Arduino Toolchain ... Arduino Programming Structure... 5.5.1 Sketches... 5.5.2. Pins : Introduction to Arduino Shields . Integration of Sensors and Actuators with Arduino ... 5.7.1 Sensor. 5.7.2 Sensor Component...... 5.7.3. Sensor Types 5.7.4 Actuators... 5.7.5 _ Difference between Actuator and Sensor... 5.7.6 Controlling LED by using IR Sensor and Remote 5.7.7 Reading Switch. Two Marks Questions with Answers ..Chapter - 6 61 6.2 63 64 6.5 6.6 6.7 6.8 ToT Communication ‘and Open Platform: loT Communication Models and APIs .. 6.1.1 loT Communication APIS... loT Communication Protocols .. 6.2.1 Bluetooth....... 6.2.2 WiFi. ZigBee 6.3.1 ZigBee Architecture 6.3.2 Logical Device Types 6.3.3. Network Layer 6.3.4 Simple Tree Routing Protocol. 6.3.5 ZigBee-AODV (ZAODY) . 6.3.6 APS Layers... 6.3.7 ZigBee Applications... GPs GSM Modules .. 6.5.1 Base Station Subsystem 6.5.2 Network Switching Subsystem... 6.5.3 Mobile Station.. 6.5.4 GSM Channel Open Platform : Raspberry Pi Architecture. 6.6.1 About the Board... 6.6.2 Linux on Raspberry Fi. 6.6.3 Difference between Raspberry Pi is and Desktop Computers Raspberry Pi Interfacing Raspberry Pi Programming... 6.8.1 Controlling LED with Raspberry Pi. 6.8.2 Interfacing an LED and Switch with Raspberry Pi ()6.9 Connecting to the Cloud... 6.8.3 Interfacing Light Sensor, 647 6.9.1 WAMP : AutoBahn for loT.. 6.9.2 _ Xively Cloud for loT..... . 6-50 6 6-54 Chapter-7 = Applications Development 71 7.2 a3 74 75 (7-1) to (7 - 24) Complete Design of Embedded Systems.. 7.1.1 Design Metrics. 72 7.12 Abstraction Steps in the Design Process. 7.1.2.1 Requirement 7.1.2.2 Specification..... 7.1.2.3 Architecture Design..... 7.1.2.4 Designing Hardware and Software Components... 7.1.2.5. System Integration... 7.1.3 Challenges in Embedded Computing System Design Development of loT Applications... Home Automation .. 73.1 Smart Lighting. 7.3.2 Smart Appliances. 7.3.3 _ Intrusion Detection 7.3.4 Smoke for Gas Detection .. Smart Agriculture .. 7.4.1 Smart Irrigation +15 7.4.2 Green House Control... 7-15 Smart Cities. 7-16 7.5.1 Smart Parking... 7-18 7.5.2 Smart Lighting... 7-21 7.5.3 Smart Roads..... (xi)7.6 Smart Healthcare... 7.6.1 Health and Fitness Monitoring. 7.6.2 Wearable Electronic 7.7 Two Marks Questions with Answers .... ee ee Solved Model Question Paper (M - 1) to (M-qy8-Bit Microcontroller Architecture Syllabus 8-Bit Microcontroller - Architecture. Contents 4.1. Introduction 1.2 Features of 8051 Microcontroller. -- Dec.-04, May-12, 1.3. Architecture of 8051 May-06,08,09,10,11,12,13,16,17,18, : - Dec.-04,09,10,11,14,19, -- Marks 16 Pin Description of 8051 ..... Dec.-11,18, May-11, «+++ Marks 13 Internal and External Memories. ......... . Dec.-10,11,12,16,17,19, ‘Stack and Stack Pointer Two Marks Questions with Answers (t=Embedded Systems and loT 1- Introduction To make a complete microcomputer syst necessary to add other peripherals such memory (RAM), decoders, drivers, number of microcomputer system. In addition, special purpose devices, d flexibility of a microcomputer system, all the features that are found in microprocesg, programmable timers, programmable I/O improve the capability and performance an The microcontroller incorporates However, it has also added features to make own. The microcontroller has built-in ROM, RAM, clock circuit. The advantages of built-in peripheral em, only microprocessor is not Sufficien : as Read Only Memory (ROM), reagj,* | hy 8-Bit Microcontroier input/output devices to make a comp devices, such as interrupt oe DMA controllers may be Added 4, a complete microcomputer system op i parallel 1/O, serial 1/0, counters ang, | devices of microcontroller are : « Built-in peripherals have smaller access times hence speed is more. * Hardware reduces due to single chip microcomputer system. © Less hardware, reduces PCB size and increases reliabil Microprocessor ficroprocessor_ contains ALU, control unit (clock’ and timing circuit), different register and interrupt circuit. It has many instructions to move data between memory and CPU. Tt has one or two bit handling instructions. Access times for memory and I/O devices are more. | } E | 5 Microprocessor based system requires more | hardware. F | 6 Microprocessor based i | 6 Microprocessor based system is mi i flexible in design point of view. — | % It has single memory map for data and code, | & Less number of pins are multifunctioned. Table 1.1.1 Comparison between microprocessor and microcontroller of the system Microcontroller Microcontroller contains microprocessor, memory (ROM and RAM), 1/O interfacing circuit “and peripheral devices such 36 A/D converter, serial 1/O, timer ete. It has one or two instructions to move dala between memory and CPU. Ithas many bit handling instructions. Less access times for built-in memory and) 1/O devices. | | Microcontroller based_system requires les) hardware reducing PCB size and increasing) the reliability. | Less flexible in design point of view. | j al It has separat for data Megas Separate memory map More number pins are multifunctioned TECHNICAL PUBLICA Tions® ~ an up-thrust for knowledgeReeRFlKRtrelwe———————————— Embedded Systems and loT fea Omelet) | 1. Distinguish between microprocessor and microcontroller. Features of 8051 Microcontroller un The 8051 i an 8-bit microcontroller designed by Intel. It was optimized for 8-bit math and single bit Boolean operations. Its family includes 8031, 8051, 8052 and 8751 microcontrollers. Let us see the features of 8051 microcontroller. The features of the 8051 family are as follows : &-Bit Microcontroller Architecture Cae 1, 4096 bytes on - chip program memory. 2. 128 bytes on - chip data memory. 3. Four register banks. 4, 128 user-defined software flags 5. 64 kilobytes each program and external RAM addressability. 6. One microsecond instruction cycle with 12 MHz crystal. 7. 32 bidirectional I/O lines organized as four 8-bit ports (16 lines on 8031). 8. Multiple mode, high-speed programmable serial port. 9. Two multiple mode, 16-bit timers/counters. 10. Two-level prioritized interrupt structure 11. Full depth stack for subroutine return linkage and data storage. 12. Direct byte and bit addressability. 13. Binary or decimal arithmetic 14. Signed-overflow detection and parity computation. 15. Hardware multiple and divide in 4 psec. 16. Integrated boolean processor for control applications. 17. Upwardly compatible with existing 8084 software. | Geen List the features of 8051 microcontroller. . Compare the 8051, 8031 and 8751 microcontroller. i 2. 3. List out the hardware resources available in 8051. Coe 4 What are the main features of 8051 microcontroller ? Cae TECHNICAL PUBLICATIONS® - an up-thrust for knowledgeEmbedded Systems and loT 8051. It consists of a CPU, “ i internal block diagram of 1 two nt 84 So te mnory RAM and program Mr - EPAOynte input/output ports, special function registers and one logic needed 4. timer / counter serial port and interrupt functions: These re ene communica te an eight bit data bus which runs throughout the chip referred as internal data bys bus is buffered to the outside world through an I/O port when memory 9 4 expansion is desired. External interrupts Counter inputs | a (4 Kbytes) Internal bus. Bus Four (8-bit) Serial contro! HO ports port fr tt J 30 pF sors ye Multiplexed ? P1 P2 P3 TxD RxD a |e dataladdress Sica Higher order Multi-functional fe lt normally 11.0592 MHz address Fig. 1.3.1 Block diagram of 8051 EES Central Processing Unit (CPU) The CPU of 8051 consists of eight-bit arithmetic and logic unit with ass registers like A, B, PSW, SP, the sixteen bit program counter and “Data pointer” © registers. Along with these registers it has a set of special function registers. 7 The unique feature of the 8051 architecture is that the ALU can also manipula? bit as well as eight-bit data types. sated TECHNICAL PUBLICATIONS® - an up-thrust for knowledgeEmbedded Systems and loT 1-5 &-Bit Microcontroller Architecture A and B CPU Registers Register A (Accumulator) It is an 8-bit register called accumulator. It holds a source operand and receives the result of the arithmetic instructions (addition, subtraction, multiplication and division). Several functions apply exclusively to the accumulator : Rotate, parity computation, testing for zero and so on. Register B . 16-bit DPTR In addition to accumulator, an —— Sbit B-register is available as a y Memory general purpose register. It is used Daal en maces for the hardware multiply/divide —— operation. att abit Data Pointer (DPTR) The data pointer (DPTR) consists of a high byte (DPH) and a low byte (DPL). Its function is to hold a 16-bit address. It may be manipulated as a 16-bit data register or as two independent 8-bit registers. It serves as a base register in indirect jumps, lookup table instructions and external data transfer. The DPTR does not have a single internal address; DPH (83H) and DPL (82H) have separate internal addresses. The Program Counter The 8051 has a 16-bit program counter. It is used to hold the address of memory location from which the next instruction is to be fetched. 8051 Flag Bits and the PSW Register The Fig. 1.3.2 shows the bit pattern of Program Status Word (PSW) of 8051. PSW is also known as flag register. By Be | cy AC FO RSI RSO OV = P Bs Fig. 1.3.2 The 8051 consists of following flags. * CY-Carry Flag : This flag is set if there is an overflow out of bit 7. The carry flag also serves as a ‘borrow flag for subtraction. In both the examples shown below, the carry flag is set. * AC-Auxiliary Carry Flag : This flag is set if there is an overflow out of bit 3 ie., carry from lower nibble to higher nibble (D, bit to D, bit) TECHNICAL PUBLICATIONS® - an up-thrust for knowledgeEmbedded Systems and loT 1-6 &-Bit Microcontrolier, A © FO - Available for user for general purpose. «RSI - RSO (Register Bank Select) : They select the working register 5,,, a follows : ADDITION SUBTRACTION 11 89H 1000 1001 Bat Lat =_ABH = 1010 1011 1101 1110 01414 0101 + 75H + aoov WOEH Cary TE}10H —TJ0001 0000 Borrow * OV-Over Flow Flag : This flag is set whenever the result of a signed numbe operation is too large, causing the high-order bit to overflow into the sign bit. « P-Parity Flag : Parity is defined by the number of ones present in the accumulator P=0, if number of ones are even and P = 1, if number of ones are odd. Example : The status of CY, AC and P flags after the addition of 9BH and 65H is # follows : H+ Accumulator —et CY =1,AC=1and P=0 There are instructions in 8051, that tests the condition of flags in the PSW regi and make decision based on the status of flags. Thus, programmer use these fl05* ® perform some arithmetic operations which involves carry or borrow or to chang? » program control (using conditional branching). As mention earlier, programmer can select register bank by setting corresponding " in PSW. z TECHNICAL PUBLICATIONS® - an up-thrust for knowledgeEmbedded Systems and loT 1-7 EEG Special Function Register of 8051 The group of registers, immediately above the 128 bytes of RAM are called to the four I/O ports, the CPU registers, &-Bit Microcontroller Architecture implemented to perform special functions and are located interrupt control pecial function registers. All access registers, the timer/counter, UART and power control are performed through registers between 80H and FFH. Direct byte address OFFH (mse) ——*| Bit address (ss) OFOH Fz. Fe] 5 | Fa] Fa | F2| 1] Fo OEOH eT 5 =] |e] 60) 0D0H D7 D6 | D5} D4} 03] 02} D1| bo oBsH BC} 88] BA] B9| BS OBOH 87 86 | BS 83 Bt | BO oagH AF AC Ag OAQH AT 6 A2| at 98H oF 9E | 9D 98 | 94} 99 90H 97 95 | 94 | 93 91 | 90 88H 8E | 6D| 8C| 8B] 8a} 89 80H a7 85 | 84 | 83 | 82 | 81 | 80 Fig. 1.3.3 SFR bit address Hardware register symbol ACC. Psw P3 P2 SCON Pt TCON Po TECHNICAL PUBLICATIONS® - an up-thrust for knowledge1-8 nenhstomttiateieaee tat eo try Special Function Registers (SFRs) are a sort of control table used for nunning monitoring the operation of the microcontroller. Each of these registers as well ag 4 The scope of RAM and precisely dg," bit they include, has its name, address in U ; purpose such as timer control, interrupt control, serial communication control etc, Even though there are 128 memory locations intended to be occupied by them, basic core, shared by all types of 8051 microcontrollers, has only 21 such registers, enable the manufacturer, of locations are intentionally left unoccupied in order ee ; further develop microcontrollers keeping them compatible with the previous versions | al function bit addresses. (See Fig: 1.3.3 on previous page) list of all the SFRs and their addresses and their value in bingy Embedded Systems and oT Fig. 1.3.3 shows speci Table 1.3.1 contains a at reset. 0000 0000 90000111 90000000 0000 0000 4444 4044 SOL e AL tt EBL gLeas = 9051 XXX0 0000 __ e052 XX00 0000 051 OXX0 0000 8052 0X00 0000 0000 0000 TimerfCouner Cont 00000000 Timer/Counter 2 Control 0000 0000 “Tmer/Counter 0 High Byte 8H ooog 000 | Timer/Counter 0 Low Byte __ BAH 0000 0000 | Timer/Counter 1 High Byte 8pH 0000 0000 | Times/Counter 1 Low Byte eH 0000 0000 | 0000 0000 | Timer/Counter 2 High Byte ocDH Timer/Counter 2 Low Byte occ 0000, TECHNICAL PUBLICA TIONS® - an up-thrust for knowledgelod Embedded Systems and loT 1-9 8-Bit Microcontroller Architecture + RCAP2H TIC 2 Capture Reg. High Byte OCBH 0 000 0000 + RCAP2L, TIC 2 Capture Reg. Low Byte OCAH 0000 0000 Econ Serial Control 98H 9000 0000 | | SBUF Seri | IL ial Data Buffer, oes s 99H. —. __.....Indeterming j ES Power Control s7Ht HMOS OXXX XXXX | ck SHMOS XXX 0000 | sem tin nmnnaisies i a ~~ : Table 1.3.4 List of all SFRs (* — Bit addressable, + — 8052 only ) before register name indicates that it is a bit addressable. + before register name indicates that it is supported by only 8052. 1. Give the details of PSW of 6051. 2. Quantify the number of register banks in 8051 and say how the CPU knows which bank is currently in use. 3. Explain the functional block diagram of 8051 in detail. ORDER 4. Describe the architecture of 8051 with neat diagram. 5. List the on-chip peripherals of 8051 microcontroller. 6. Mention the size of DPTR and stack pointer in 8051 microcontroller. 7. What is program status word of 8051 ? 8. Explain with a neat block diagram the architecture of 8051 microcontroller. AU : May-13, 16, 18, Marks 16 9. Explain the functional block diagram of 8051 microcontroller. LO EDESSCM CS eT] EE] Pin Description of 8051 The 8051 is packaged in a 40-pin DIP. The Fig. 1.4.1 shows the pin diagram of 8051. It is important to note that many pins of 8051 are used for more than one function. The alternative functions of pins are shown in bold letters. The 8051 has 32 I/O pins configured as four eight-bit parallel ports (PO, Pl, P2 and P3). All four ports are bidirectional ie. each pin will be configured as input or output (or both). All port-pins are multiplexed except the pins of port 1. Each port consists of a latch, an output driver and an input buffer. Port 0 (Pins 32 - 39): Port 0 pins can be used as I/O pins. The output drives and input buffers of port 0 are used to access external memory. Port 0 outputs the low order byte of the external memory address, time multiplexed with the data being written or tead. Thus, port 0 can be used as a multiplexed address/data bus. Port 1 (Pins 1 - 8): Port 1 pins can be used only as I/O pins. TECHNICAL PUBLICATIONS® - an up-thrust for knowledgeEmbedded Systems and loT PIO 1 30 Pit 2 ae PL 3 a Pott | PS 4 36 Pid 5 Pts 6 e P16 7 ss PL7 8 33 RST 32 - P3.0 (RXD) : EA(Vpp) 3.1 (TxD) i ent 30 ALE (PROG) 3.2 (INTO) 12 29 P3.3 (INT1) Ae 28 Ports | pa 4 ty 3 a7 P38 (4) 15 26 P36 (WR)}—J 16 25 Port 2 P37 (RD) 7 x Oscillator | XTAL 2 signals ALA GND Fig. 1.4.1 Pin-out of 8051 Port 2 (Pins 21 - 28) : The output drives of port 2 are used to access external memory. Port 2 outputs the high order byte > of the external memory address | Symbol Position when the address is 16 bits wide. I Oe | Otherwise, port 2 is used as an I/O I __E7 External memory read signal q a eke PS ettenal memory rte signal. | Port 3 (Pins 10-17): All port TL P35 External timer 1 input | pins of port 3 are multifunctional. | 19 Fat Bsteinal timer 0 input Therefore, each pin of port 3 can be | me Programmed to use as I/O or as Poe 23 External interrupt 1 input. | one of the alternate function, They | INTO P32 Extemal interrupt 0 input. —_| have special functions as shown | ay, at ; below including two external | : Serial data output. interrupts, two counter inputs, two |_ Pao Serial d, special data lines and two timing control strobes. TECHNICAL PUBLICATIO;Embedded Systems and JoT wt 8-Bit Microcontroller Architecture Powersupply Pins Vcc (Pin 40) and Vag (Pin 20) : 8051 operates on dic. power supply of +5 V with respect to ground. The +5 V is to be connected to pin Voc and ground to pin Vs. with rated power supply current of 125 mA. Oscillator Pins XTAL2 (Pin 18) and XTAL1 (Pin 19) : For generating an internal dock signal, the external oscillator is connected at these two pins. ALE (Address Latch Enable, Pin 30): AD, to AD, lines are multiplexed. To demultiplex these lines and for obtaining lower half of an address, an external latch and ALE signal of 8051 is used. RST (Reset, Pin 9): This pin is used to reset 8051. For Proper reset operation, reset signal must be held high at least for two machine cycles, while oscillator is running. PSEN (Program Store Enable, Pin 29) : It is the active low output control signal used to activate the enable signal of the external ROM/EPROM. It is activated every six oscillator periods while reading the external memory. Thus, this signal acts as the read strobe to external program memory. EA (External Access, Pin 31): When the EA pin is high (connected to Veg), program fetches to addresses 0000H through OFFFH are directed to the intemal ROM and program fetches to addresses 1000H through FFFFH are directed to external ROM/EPROM. When EA is low (grounded), all addresses (0000H to FFFFH) fetched by program are directed to the extemal ROM/EPROM. 1. Draw the pin diagram of 8051 microcontroller and explain its port structure, | OR a 2. List the alternative functions assigned to port 3 pins of 8051 microcontroller. COS Tae) 3. Explain the pinouts of 8051 microcontroller CORDS Cae EE internal and External Memories AU : Dec.-10,11,12,16,17,19, May-11 Fig. 1.5.1 shows the basic memory structure for 8051. It can access up to 64 K program memory and 64 K data memory. The 8051 has 4 K bytes of internal program memory and 256 bytes of internal data memory. TECHNICAL PUBLICATIONS® - an up-thrust for knowledgeAccess, External memory —=— oR — 1 0000 Extermaj 1000H OFFFH 4 kbytes Internal 000: Internal memory | Data memory Internal data memory External data memory (SFRs) FFFFH FFH eee ®Y | Accessible by Upper: (nde rect 428 ¢ Addressing 1 addressing only 64 kbytes external memory 80H i 7FH Accessible by direct & indirect addressing Lower 128 RAM of 8051 is organized into three distinct areas * Register bank * Bit addressable * General purpose. TECHNICAL PUBLICATIONS® 8” up-thrust for knowledgeEmbedded Systems and loT 1-13 8-Bit Microcontroller Architecture Byte address Byte address 7F Bank 3 Benk 2 By Be 85 8, B; Br By Bo we [7e[ 7] 7c] 7B] 7A] 7978] 2 77 | 76 [75 | 74 | 73| 72| 71 [70] 2 oF [ee | 60] 60] 65 | 6a] ea | 68] 2 — 67 | 66 | 65 | 64] 63 | 62] 61 [60] 2c oF [Se | 5D| 6c] 68 | 6a] 60 [58] 2B 57 | 56 | 65 | 54 [53 | 52] 61 [60] 20 4F [4 | 4D] 4c] 48 [4a] 49 [48] 29 47 | 46 | 45 | 44 [43 | 42] a1 [40] 28 ‘3F | 3€ | 3D] 3c] 38] 3A] 39] 38) 27 37 | 36 | 35 | 34 [33 | 32] 31 [30] 26 2F | 2e | 20] 2c| 28 | 2a| 29[ 28 | 25 27 | 26 | 25 | 24| 23 | 22| 21 [20] 24 oe jf] 4e| 1D | tc] 18] 1A] 19[ 18] 23 a7 [16 | 15 | 14 [13 | 12] 1 [10] 22 oF [oe [00] 0c] 08 | oA] oa | oa} 21 orfosfosfoafosfo2 for [oo] 20 4, Register Bit addresses Byte General purpose tank addresses Fig. 1.5.2 Organization of internal RAM of 8054 TECHNICAL PUBLICATIONS® - an up-thrust for knowledge@-Bit Microcontroller Arch Embedded Systems and loT et EERE 8051 Register Banks (Working Registers) internal RAM constitute 32 wor, ‘1 x 1FH of in ‘ The first 32-bytes from address 00H to eight registers each. The four "iste registers. They are organized into four banks of isters named Ro to Ry, banks are numbered 0 to 3 and are consists of eight °8 | i ddress. Each register can be addressed by name or by its RAM “ se ne DSW Only one register bank is in use at a time. Bits R50 ant leterming which bank of registers is currently in use. La on On reset, the bank 0 is selected and hence it is a default register bank. Register banks when not selected can be used as general purpose RAM. Bit / Byte Addressable The 8051 provides 16 bytes of a bit-addressable area. It occupies RAM byte addresses from 20H to 2FH, forming a total of 128 (16 x 8) addressable bits. An addressable bit may be specified by its bit address of 00H to 7FH or 8 bits may form any byte address from 20H to 2FH. For example, bit address 4EH refers bit 6 of the byte address 29H. General Purpose RAM The RAM area above bit addressable area from 30H to 7FH is called general purpose RAM. It is addressable as byte. EEE] Rom Space in the 8051 The 8051 has 4 kbyte of internal ROM with addi programmed by manufacturer when the chip is altered after fabrication. This is used to store final using program address register, Tess space from 0000H to OFFFH. It is built. This part cannot be erased ot version of the program. It is accessed 1. What do you understand by bit addressable RAM in 8051 microcontroller? as 2. Discuss the internal memory organization of the 8051 microcontroller. Ces Oe areEmbedded Systems and loT 1-15 8-Bit Microcontroller Architecture 3. Discuss about the organization of internal RAM and special function registers of 8051 ‘microcontroller in detail. 4, Discuss in datail internal data memory organization of microcontroller 8051. 5. Explain the program memory and data memory structure of 8051 microcontroller. 6. Draw the data memory structure of 8051 microcontroller and explain. 7. Explain the RAM structure of 8051 microcontroller. EEG stack and Stack Pointer The stack refers to an area of internal RAM that is used to store and retrieve data quickly. The stack pointer register is used by the 8051 to hold an internal RAM address that is called top of stack. The stack pointer register is 8-bit wide. It is increased before data is stored during PUSH and CALL instructions and decremented after data is restored during POP and RET instructions. The stack array can reside anywhere in on-chip RAM. The stack pointer is initialized to O7H after a reset. This causes the stack to begin at location 08H. The operation of stack and stack pointer is illustrated in Fig. 1.6.1. on-chip RAM Ong Ra ono Rat oe oe _ o oe 08 Bais] 08 oe sp — 7 r= Sick ptr a eset o7 {a) Status of stack and (b) Store operation ack pontr of esst [past] 00 Fame [sree] [s=]—-( baa 98 a8 coher bees] 07 sp =-sP1—ay o {c) Read operation Fig. 1.6.1 TECHNICAL PUBLICATIONS® - an upthrust for knowledgee-Bit Microcontroller Arctitectin, Embedded Systems and loT 1,16 bit-addressable RAM The stack may overwate dat in the weEieh PO i adresable RAM ay scratch-pad RAM, Thus to avoid conflict with the ee in the internal RAM scratch-pad RAM data, the stack is initialized at a higher eT tat 1. Explain the operation of stack in 8051 2. Define SP. Two Marks Questions with Answers in microcontrollers when 1 Name any four additional hardware features available in mict compared to microprocessors. ‘Ans.: The microcontroller has builtin ROM, RAM, parallel W/O, serial Yo, timer/counters and a clock circuit. Q.2 Write the memory capacity of microcontroller 8051. Ans. : The memory capacity of microcontroller 8051 is 64 kbytes. 3 What are the flags available in 8051 ? | AU : May-05] OR What are the flags supported by 8051 microcontroller 7 | AU : Dec-19] Ans. : The flags available in 8051 are : CY (Carry flag), AC (Auxiliary carry flag), OV | (over flow flag) and’P (Parity flag) Q.4 What is meant by SFR in 8051 ? Give an example. ‘Ans. : The group of registers, implemented to perform special function and are located immediately above the 128 bytes of RAM are called special function registers for example, all port registers, TCOM, SCON, IE, IP and so on. Q5 Give the memory size of 8051 microcontroller. (ns) ‘Ans. : The 8051 can access upto 64 Kbyte program memory and 64 kbytes of data memory. Q.6 — Give the details of PSW of 8051, (Refer section 1.3.5) 7 Compare microprocessor and microcontroller. (Refer section 1.1) SUED) | Q.8 What are the applications of 8051 microcontroller 2 5 | Ans. : Microcontrollers are more preferred in embedded microcontroller are : * Calculators : * Game machines . * Mobile systems : «Traffic light control systems * Communication systems products. Some applications of | Accounting systems | Data acquisition systems Complex industrial controllers Military applications TECHNICAL PUBLICATIONS® - an up.thry t for knowledge st for knoEmbedded Systems and loT 1-17 -Bit Microcontroller Architecture 9 Explain the significance of SFRs In 8051 microcontroller. Ans. : The group of registers, implemented to perform special function and are located immediately above the 128 bytes of RAM are called special function registers. They are responsible for operation of ALU, timer, serial port, parallel ports and interrupt control. Q.10 What Is mean by microcontroller 7 Ans. : A device which contains the microprocessor with integrated peripherals like memory, serial ports, parallel ports, timer/counter, interrupt controller, data acquisition interfaces like ADC, DAC is called microcontroller. Q.11 List the features of 8051 microcontroller. (Refer section 1.2) Q.12 State the function of RS1 and RSO bits in the flag register of Intel 8051 microcontroller 7 Ans. : RS1 and RSO are bank selection bits. They are used to select working register bank of 8051 as given below : * 00 Bank 0 © 01Bank 1 * 10 Bank 2 © 11 Bank 3 Q13 Give the alternate functions for the port pins of port3. (Refer Table 1.4.1) Q14 Explain the function of the PSEN pin of 8051. Ans. : PSEN : PSEN stands for program store enable. In 8051 based system in which an external ROM holds the program code, this pin is connected to the OE pin of the ROM. Q15 Explain the function of the EA pin of 8051. Ans.: EA : It stands for external access. When the EA pin is connected to Vcc, program fetched to addresses 0000H through OFFFH are directed to the internal ROM and program fetches to addresses 1000H through FFFFH are directed to external ROM/EPROM. When the EA pin is grounded, all addresses fetched by program are directed to the external ROM/EPROM Q16 Explain the 16-bit registers DPTR of 8051 or what is a function of DPTR 7 Ans. : DPTR : It stands for data pointer. DPTR consists of a high byte (DPH) and a low byte (DPL). Its function is to hold a 16-bit address. It may be manipulated as a 16-bit data register or as two independent &-bit registers. It serves as a base register in indirect jumps, lookup table instructions and external data transfer. Q17 Explain the function of the SP register of 8051. Ans. : SP ; It stands for stack pointer. SP is a 8- bit wide register. It is incremented before data is stored during PUSH and CALL instructions. The stack array can reside anywhere in on-chip RAM. The stack pointer is initialised to 07H after a reset. This causes the stack to begin at location 08H. TECHNICAL PUBLICATIONS® - an up-thrust for knowiedgeBit ‘Microcontroller Architecn, Embedded Systems and loT 1-18 e Q.18 Name the special function registers available In 8051. Ans. : The special function registers available in 8051 are * Program Status Word. * Accumulator B Register . © Stack Pointer, «Data Pointer. © Port 0 « Port © Port 2 « Port3 7 © Interrupt priority control register. «Interrupt enable control register. Q.19 How is stack implemented in 8051 7 Ans. : The 8051 LIFO : Stack can reside anywhere stack pointer to indicate the top of the stack using i During PUSH the SP is incremented by one and POP the SP is dere 0.20 What is the maximum frequency of the clock signal that can 8051 counter 7 Ans. : The maximum frequency of the clock signal that is 1/12 x crystal frequency. 0.21 What are the features of ROM and RAM in 8051 microcontroller ? Ans. : The 8051 has 128-byte internal RAM. It is accessed using RAM address register. The internal RAM of 8051 is organized into three distinct areas: * Register Bank ¢ Bit addressable © General purpose. The 8051 has 4 kbyte of internal ROM with address space from 0000H to OFFFH. It is programmed by manufacturer when the chip is built. This part cannot be erased or altered after fabrication. This is used to store final version of the program. It is accessed using program address register. Q.22 What is the function of program counter in 80517 ‘Ans. : The 8051 has a 16-bit program counter. It is used to hold the address of memory location from which the next instruction is to be fetched. in the internal RAM. It has 8 bit PUSH and POP instructions, mented by one. be counted by t can be counted by 8051 counter Q.23 List the advantages of microcontroller over microprocessor. Ans. : The advantages of microcontroller over microprocessor are * Because of built-in peripheral support they provide single chip microcontroller system. © Less hardware required. © Less hardware increases reliability. Supports internal memory which reduces access time. Q.24 Which ports of 8051 are bit addressable 7 co Ans. : All ports of 8051 - port 0, port 1, port 2 and port 3 are bit addressable. TECHNICAL PUBLICATIONS® - an up-thrust for knowledgeEmbedded Systems and loT 1-19 8-Bit Microcontroller Architecture Q25 A given 8051 chip has a speed of 16 MHz. What Is the range of frequency that can be applied to the XTAL 1 and XTAL 2 pins ? Ans. : The range of frequencies that can be applied to the XTAL 1 and XTAL 2 pins is 1 MHz to 16 MHz. Q.26 What happens in power down mode of 8051 microcontroller ? Ans. : In the Power Down Mode (PD = 0), the CPU puts the whole chip to sleep by tuming off the oscillator. In case if it is running from an external oscillator, it also gates off the path to the intemal phase generators, so no internal clock is generated even if the external oscillator is still running. The on-chip RAM, however, saves its data, as long as Vcc is maintained. In this mode the only Icc that flows is leakage, which is normally in the micro-amp range. Q.27 What is the function of R registers in 8051 microcontroller ? (Refer section 1.5.1.1) Q.28 What is the purpose of overflow flag in 8051 microcontroller ? (Refer section 1.3.5) Q.29 List the on-chip peripherals of 8051 microcontroller. (Refer section 1.3) Q.30 Mention the size of DPTR and stack pointer in 8051 microcontroller (Refer section 1.3) Q.31 List the alternative functions assigned to port 3 pins of 8051 microcontroller. (Refer section 1.4) Q.32 What are the main features of 8051 microcontroller ? (Refer section 1.2) CO Q33 What is program status word of 8051 ? (Refer section 1.3) Qa Q34 Mention the purpose of PSEN and EA in 8051 microcontroller. (Refer section 1.4) Q35 What is meant by PSW 2 (Refer section 1.3.5) CEE Q36 State any four inbuilt features of 8051 microcontrollers. (Refer section 1.2) Q37 What is the use of PSW ? Eg ‘Ans. : PSW (Program Status Word) is used to determine whether or not to execute conditional instructions. In case of 8051, it is also used to select the working register bank. Q.38 What is the significance of PSEN and EA pin in 8051 microcontroller ? (Refer section 1.4) aoa TECHNICAL PUBLICATIONS® - an up-thrust for knowledgeTECHNICAL PUBLICATIONS® - an upthrust fr knowledgeInstruction Set and Programming Syllabus Instruction Set and Programming. Contents 21 051 Addressing Modes .............,.. Jume-08,11, Dec.-07,08,09,11,13,14, May-13,14,16,17: ~~ « Marks 16 22 eee Maye sees + Marks 4 2.3 Data Transfer Instructions «+++ Dee,-07, 08, 11, May-11, »» Marks 16 2.4 — Byte Level Logical instructions ........ May-10, 71, . ++ Marks 10 2.5 Arithmetic Instructions.............. May-05, 08, June-11 +++ Marks 2 2.6 — Bit Level Logical Instructions . sseeees.. May-08,10,11,17, Dec.-18, Marks 13 2.7 Rotate and Swap Instructions 2.8 Jump and CALL Instructions .. Dec,-09, June-09 - + Marks 6 2.9 Time Delay for 8057 2.10 Program Examples ce teeeeeeeeees ++ May-10, Dec.-12, Marks 8 2.11 Two Marks Questions with Answers (2-1)ne Embedded Systems and loT ination addresses are SPe the the data sources OF dest ‘ I d the data, is called ‘addressing mode’. This section 051 with examples. The way, using which instruction mnemonic for moving explains addressing modes used in EEXEI Register Addressing ; , The 8051 can access eight “working registers” (ROR7) THRE bit code within instruction selects one of the eight registers from the selected eT The programmer can select a register bank by modifying bits 4 and 3 in the PSW. source register Destination register Example : Add the contents of register R3 and R4 from bank 2 Step 1 : Select register bank. MOV PSW, #00001000B ; select regi: Step 2 : Add the contents of R3 and R4 MOV A, R3 ADD A, R4 ister Bank 2 EERE Direct Byte Addressing Memory y Destination register y s = Address of memory Data from | >= within the instruction selected memory location Direct addressing can access any on-chip variable or hardware register i.e. on-chip RAM and special function register. The most significant bit of the address decides sheth tion wi \ = whe a is a location within on-chip RAM (MSB = 0) or in special function registet Example : Add the contents of locations 50H and 51H. MOV A, 50H ; load byte from address 50H into A ADD A, 51H ; Add the contents of A and the contents at memory location 51H. TECHNICAL PUBLICATIONS® - an up-thrust for knowledgeEmbedded Systems and loT 2-3 Instruction Set and Programming [2.1.3] Register Indirect Addressing In this addressing mode RO and R1 of each register bank can be used as an index or pointer register. RO and Ri point to the contents in the RAM. The instruction with indirect addressing uses the '@’ sign. Indirect addressing accesses data in dynamic manner rather than static manner. Looping is not possible in direct addressing mode. In indirect addressing we can increment the index or pointer register to access successive locations. Memory Eapree 2 s| Register Destination register t+ moe mei Contents of register are = : used to point memor Data from - feo ry selected memory’ location RO and Ri are the only registers that can be used for pointers in register indirect addressing mode. Example : ADD the contents of memory location addressed by register 1 to the contents of RAM location pointed by register 0. MOV A, @RO ; load the contents pointed by RO in A ADD A, @R1 ; Add the contents of A and the contents pointed by Ri EKE2 immediate Addressing In this addressing mode source operand is a constant rather than a variable. So the _Destination register constant can be incorporated in the Data specified instruction. Sign “#” indicates it is a a De tn immediate addressing mode. Example : Add the constant 52 decimal in accumulator. Mov a, #52 TECHNICAL PUBLICATIONS® - an up-thrust for knowledgeEnibedied Systems and for Instruction Set nd Progra hy Register specific pe in the instruction, these refer to a specific register such as accumulato, Example : SWAP A En Index Only program. memory can be accessed in the index addressing. Either the Dpyp o o + Swap nibbles within the Accumulator PC can be used as an index register. DPTR Register » Program memory Contents of DPTR , ARegister iste, [eee Data from Address of selected memory! memory Contents of register A Example : Read data from the program memory. MOVC A, @A+DPTR ; This instruction adds the unsigned 8-bit and accumulator } contents into sixteen bit Data pointer, and uses the ‘sum as jan address from which byte to be moved into accumulator Stack Addressing Mode It is subtype of direct addressing mode in which stack instructions (PUSH and POP) are used. Instruction such as 'PUSH A’ is invalid. Here, we have to specify the address of register A. Thus, PUSH OE0H is a valid instruction; accumulator on the stack. it pushes/stores the contents of Examples : PUSH 04 ; Push R4 onto stack PUSH 06 ; Push RG onto stack POP 02 ; Pop top of stack into R2 POP OFOH ; Pop top of stack into register B TECHNICAL PUBLICATIONS ‘9n Up-thrust for knowledgeEmbedded Systems and loT 2-5 Pes 1. Classify the addressing modes of 8051 microcontroller. 2. Explain the different addressing modes in 8051 in detail AU : June-08, Dec.-07,08,11 Marks 8 3. What are the addressing modes of 8051 microcontroller ? {OSL ESS UST SEMTET What is register indirect addressing mode of microcontroller 8051 ? Give example. AU : June-11, Marks 2 Instruction Set and Programming 5. Explain the different addressing modes of 8051 microcontroller. AU : May-13,14, Dec.-13, Marks 16 6 What are the addressing modes followed in 8051 Micro controller ? (SCR TET ey 7, Explain the different addressing modes of 8051 microcontroller. LENS TANETT EZ Classification of Instruction Set of 8051 An instruction is a single operation of a processor defined by an instruction set architecture. According to type of operations, the instruction set of 8051 is classified as, = Data Transfer Instructions = Byte Level Logical Instructions Bit Level Logical Instructions Arithmetic Instructions Jump and CALL Instructions. melts 1. List the different types of 8051 instructions AU : May-10, Marks 4 2. Give the classification of 8051 instruction set. Data Transfer Instructions An immediate, direct, register and indirect addressing modes are used in different MOVE instructions. Table 2.3.1 lists all types of data moving (data transfer) ns. instructions. MOV , : Move 8-bit/16-bit Bytes : 1/2/3 Cycles : 1/2 MOV A, RO : This instruction copies the contents of the register RO of Ka selected register bank to the accumulator, Description Copy the byte variable indicated by ‘sre-byte' into the ‘dest-byte’ location, Flags are not affected, | MOV A, Rn Copy the contents of register Rn of selected register bank to A. i Example : | TECHNICA! DIIRL ImATinno®Embedded sy. Instruction Set ang SARE! Systems and ior 2-6 Pram MOV A, di ss 7 i ecified with instruction to 4, i ree Copy the contents of address SPC" Example : ay k sae This instruction copies the contents of memory ja. MOV 4, 30H : Thi the accumulator. : tion whose address is 30H to the MOV. a en kito A. ae Copy the contents of the addres ae cae ob ears Example ; jon COP’ I 2 MOV A, @R1 : This instructio jeter Rl from selected ray, (at k whose address is specified in the regi Biste, tion p me poet aun DATIK : VA, tdata siven in the instruction to 4- . " Load data given in the instruc ee vette Example : MOV A, #30H : This instruction copes gi IMstrUction GOH) into the accumulator. ee i selec er MOV Ra, A Copy the contents of A to vegeta TE Pe cntwiOb soul Example ; MOV R2, A: This instruction copies the lator in py ee register of selected register bank. ee i . ii selec i _ MOV Rn, direct Copy the contents of address see od reister ban aoe MOV Ry 40H This incon ed ester bank ee address 40H into the RI register 2 g MOV Rn, #data Load data given in the instruction to register Rn of selected register Example : bank. : : i : MOV R2, #20H : This instruction loads 20H in the register R2 of Ea = Se sgister bank. z a _ MOV direct, A ‘Copy the contents A to the address specified within instruction, 1 Example : MOV 20H, A : This instruction copies the contents of accumulator ig | the direct memory address specified in the instruction (20H) ' MOV direct, Rn Copy the contents of register Rn of selected bank register to the Example ; address specified within instruction. 7 MOV 30H, R2 : This instruction copies the contents of register R2 of selected register bank to the direct memory address specified in the | oo instruction (0H). : 4 MOV direct, direct Copy the contents of the address specified within instruction to the Example : address specified within instruction 3 MOY 20H, 40H : This instruction copies the contents of memory location whose address is 40H to the memory location whose address | is 20H. MOV direct, @Ri Copy the contents of the address given by register Ri of selected Example : register bank to the address specified within instruction. MOV 20H, @R3 : This instruction copies the contents of memory location whose address is given by register R3 of selected register bank into the memory location whose address is 20H. MOV direct, #data Load data given within instruction to the address specified within Example : instruction. MOV 30H, #12H : This instruction copies data given within instruction (12H) into the memory location whose address = 30H. 3Embedded Systems and ioT 2-7 Instruction Set and Programming Copy the contents of A to the address given by re register bank, MOV @R1, A : This instruction copies the contents of accumulator to the memory location whose address is given by register R1 of selected register bank. Copy the contents of address specified within instruction to the address specified by register Ri of selected register bank, MOV @R2, 30H : This instruction copies the contents of memory location whose address is given within the instruction (30H) into the ‘memory location whose address is specified by register R2 of selected ‘register bank. ae : Load the data specified within instruction to the address specified by register Ri of selected register bank. 4 ‘MOV @R2, #30H : This instruction loads 30H into the memory location whose address is specified by register R2 of selected register bank. ‘The data pointer is loaded with the 16-bit constant indicated. The second byte (DPH) is the high-order byte, while the third byte (DPL) : holds the low-order byte. “ s Example : MOV DPTR, #1234H : This instruction loads the value 1234H into the es Data Pointer : DPH will hold 12H and DPL will hold 34H. Table 2.3.1 | te Instructions to Access External Data Memory The Table 2.3.2 explains the instruction to access external data memot ane coo | MOVX A, @Ri Copy the contents of the external address in Ri to A. | | Bample: MOVX A, @ RO : This instruction copies data from the &-bit address in RO to A. : MOVX A, @DPTR This instruction copies data from the 16-bit address in DPTR to A MOVX @Ri, A Copy data from A to the external address in Ri. Example : MOVX @R1, A : This instruction copies data from A to the S-bit address in R1. nstruction copies data from A to the 16-bit address in DPTR. Table 2.3.2 Important Points to Remember in Accessing External Data Memory * All external data moves with external RAM involve the A register. MOVX @DPTR, A This © While accessing external RAM, Rp can address 256 bytes and DPTR can address 64 Kbytes. * MOVX instruction is used to access external RAM or I/O addresses. EEE] instructions to Access External ROM/Program Memory The Table 2.3.3 explains the instructions to access external ROM/program memory. TECHNICAL PUBLICATIONS® - an up-thrust for knowledgeEmbedded Systems and loT 2-8 Instruction Set and Programing MOVC A, @A + DPTR ary the contents of the external ROM address formed by adding || A and the DPTR, to A. MOVC A, @A + PC Copy the contents of the external ROM addres __Avand the PC, to A. ~ Table 2.3.3 ss formed by adding Stil Important Points to Remember in Accessing External Read Only Memory | i | escdptian sy ihe ‘Stack Pointer is incremented by one. The contents of the indicated variable | Example: PUSH B : This instruction increments the stack pointer by one and stores the : | POP direct: Pop from stack Bytes: 2 Cycles : 2 | Description: The contents of the intemnal RAM location addressed by the Stack Pointer is Important Points to Remember during PUSH and POP by 1 (to point to the . incremented When PC is used to access external ROM, it is al address of exter next instruction) before it is added to A to form the physical ROM. * All external data moves with external ROM involve the A register. * MOVC is used with intemal or external ROM and can address 4K of internal, code or 64 K of external code. ° The DPTR and the PC are not changed. Data Transfer a euch (PUSH anal ual A netructene aon direct Push onto face : Bytes: 2 Cycles : a is then copied into the intemal RAM location addressed by the Stack Pointer. Otherwise no flags are affected. contents of register B to the internal RAM location addressed by the Stack inter (SP). read, and the Stack Pointer is decremented by one. The value read is then transferred to the directly addressed byte indicated. No flags are affected. Example : POP ACC : This instruction copies the contents of the internal RAM location addressed by the stack pointer to the accumulator. Then the stack pointer is decremented by one, * When the SP contents become FFH, for the next PUSH, the SP rolls over to 00H. * The top of the internal RAM, ie. it's end address is 7FH. So next PUSHes after 7FH result in errors. © Generally the SP is set at address above the register banks, ¢ The PUSH and POP operations may be applied to the Stack Pointer (SP). + When PUSH and POP operations are used for the registers from the register banks (bank 0 - bank 3), specify direct addresses within the instructions, Do not use register name from register bank since the regtster name does not specify the bank in use. 7 TECHNICAL PUBLICA Tions® 89 up-thrust for knowledgeEmbedded Systems and JoT 2-9 Instruction Set and Programming pu Data Exchange Instructions When 8051 executes MOV, PUSH or POP instruction, the ‘copy operation’ takes place. The data from the source address is copied to the destination address. The data at the source address remains unchanged. The Exchange instructions move data from source address to destination address and vice versa. Table 2.3.4 lists all types of exchange instructions in 8051. Exchange data bytes between register Rn and A. 7 XCH A, RO : This instruction exchanges contents of accumulator with the contents of register RO of selected register bank. | Exchange data bytes between address directly given within instruction | and A, | i XCH A, 20H : This instruction exchanges contents of accumulator with ch oe of memory whose address is given within the instruction ). Exchange data bytes between A and address in Ri MOV A, @R2 : This instruction exchanges the contents of accumulator with the contents of memory location whose address is given by the contents of register R2 of selected register bank. XCHD exchanges the low-order nibble of the Accumulator (bits 3-0), with that of the internal RAM location indirectly addressed by the specified register. The high-order nibbles (bits 7-4) of each register are not affected. RO contains the address 20H. The Accumulator holds the value 36H (001101108). Internal RAM location 20H holds the value 75H (011101018). The instruction, XCHD A, @R0 will leave RAM location 20H holding the id 35H (001101018) in the Accumulator. Eee] | | Table 2.3.4 Important Points to Remember in Exchange instructions All exchanges involve the A register. «All exchanges take place internally within 8051. © When XCHD A, @Ri instruction is executed, the upper nibble of A and the upper nibble of the address in Ri do not change. + Immediate addressing mode cannot be used in the exchange instructions. w Ques! 1. Write the I/O related instructions in microcontroller 8051. 2. What is the operation carried out when 8051 executes the instruction MOVC A @A+DPTR? 3. Mention the I/O instructions of 8051 nsicrocontroller TECHNICAL PUBLICATIONS® - an up-thrust for knowledgecontro! Explain : rogram the data transfer instructions and. p' microcontroller re executed by 8051, istructions ar Explain the operations carried out when the following in (OH, L2 “ iv) CINE A, 50H, ) MOVX @ R04 ji MOVC A,@A + PC iii) RLC A ») XCH A, 30H where L2 and L3 are labels. a ERE byte Level Logical Instructions * The instructions At and/or Exclusive-} first. No flags are * The da ical functions AND, 9 eae on the affected. the sour ical operations use all four rare “ k byte. Here, directly addressed bytes may be use instructions are usefyy = either the accumulator OF a constant as the source me one or mote bite in. clearing (ANL), setting (ORL) or complementing (XRL) Output ports, or control registers, This is illustrated in following figures. byte-level log XXXX XXX X Unknown B-bit binary number OEE done Masking pattern XXXX 0000 Result Masked bits Fig. 2.4.1 Masking using AND operation XXXK Xxx Unknown 8-bit binary number * 1111 aog9 Setting pattern ee M1440 xxxy Result Set bits 2.4.2 Setting bits using OR Operation XXxXX Uae 8-bit binary number ORCC said Pattem for inverting lower 4-bits XXXX RRR Resuit Inverted bits Fig. 2.4.3 Inversion of part of lumber uy "9 XOR operation TECHNICAL PUBLICATION: — * 89 Up-thrust for knowledgeEmbedded Systems and loT 2-11 Instruction Set and Programming «Table 2.4.1 gives the list of byte level logical operations. ANL performs the bitwise logical-AND operation between the variables indicated and stores the result in the destination variable. No flags are affected. AND register to Accumulator Sake R2 Hegel ANDs Ad Rae or ult in A. A, @R2 : Lo; cally ANDs contents of Atand "memory location whose address is given by Ro and tores result in A. AND immediate data to Accumulator _ANL A, #50H : Logically ANDs contents of A with 50H and stores result in A. Byte 2 Ie ANL direct, A AND Accumulator to direct byte Byte 2 | Example : ANL 20H, A : Logically ANDs contents of A with the | contents of memory location 20H and stores result at | memory location 20H. | -ANL direct, #data__ AND immediate data to direct byte Byte 3 | Example : ANL 20H, #20H : Logically ANDs the contents of memory location 20H with data 20H and stores result I in memory location 20H. | ORL , : Logical-OR for byte variables Bytes : /2/3 Cycles : 1/2 F | Description : ORL performs the bitwise logical-OR operation between the indicated | variables, storing the results in the destination byte. No flags are affected. | ORL A, Rn OR register to Accumulator Byte1 Cycle 1 Example : ORL A, R2 : Logically ORs the contents of A and R2 | and stores result in A. i | ORL A, direct OR direct byte to Accumulator Byte2 Cycled | Example : ORL A, 20H : Logically ORs the contents of A and i | memory location 20H and stores result in A. { | ORL A, @Ri OR indirect RAM to Accumulator Bytel Cycle 1 | Example : ORL A, ©R2 : Logically ORs the contents of A and i | memory location whose address is given by register { | R2 and stores result in A. d | ORLA, #data OR immediate data to Accumulator Byte2 Cycle 1 Example : ORL A, #32H : Logically ORs the contents of A with i _32H and stores result in A. __itStheced Systm andor 2-12 _ instsction Stand Progra ORL direct, a Example : Byte2 Cy OR Accumulator io direct by! ee os ele | ORL 30H, A : Logically ORs the contents & the contents of memory location 30H and stores result at memory location 30H. OR immediate data to direct byte f ORL 204, #30H ; Logically ORs the contents 0! memory location 20H and data 30H and stores result at memory location 20H. xR , oo : Logical Exclusive-OR for byte salable Bytes : 1/2/3 Cycles : 1/2 ORL direct, #data Byte3 Cycle Example ; ‘Description : ine log ExcniveOR operation beeen he cal f ‘indicated variables, storing the results in the Soe ation. No flags are (ORLA, Ra Byte Cycle 1 | Example + | OXRL A, direct gered | Example : : ALAR Byte Cycle 1 Bamples 4, @RZ : Logically XORs the contents of A end o emory location whose address is give 2 | XRL A, #data Byte2 — Cycle1_ | Example : - 40H : Logically XORs the contents of A with | | a data 40H and stores result in A. u XRL direct, A ~ Exclusive-OR Accumulator to direct byte Byte2 Cycle T _ Example : _ XRL 20H, A : Logically XORs the contents at 20H ~ 4 ft . and the A and stores the result at 30H. : ; XRL direct, #data _Exchisive-OR immediate data to direct Byte3 Cycle? Example : _-XRE 30H, #40H : Logically XORs the contents at 30H i © and data 40H and stores the result at 30H. CLR A: Clear Accumulator Bytes: 1 Cycles:1 | Description : The Accumulator is cleared (all bits set on zero). No flags are affected. CPL A: Complement Accumulator He i Gyles Description : Each bit of the Accumulator is logically complemented (one’s complement). Bits which previously contai to a zero and vice-versa, No flags are affected. Table 2.4.4 ined a one are changed instructions : XRL A, direct ? wal ven 8051 microvo, 1. What is the operation of the gi 2, Explain the instruction sel of 8051 microconti LeEmbedded Systems and loT 2-13 Instruction Set and Programming [EGF Arithmetic instructions The arithmetic operations of 8051 include increment, decrement, addition, subtraction, multiplication, division and decimal operations. [2G incrementing and Decrementing Incrementing and decrementing instructions allow addition and subtraction of 1 from a given number. These instructions not affect C, AC and OV flags. Table 2.5.1 lists the increment and decrement instructions. INC : InctementBytes : 1/2 Cycles : 1/2 Description: INC increments the indicated variable by 1. An original value of OFFH will ie overflow to OOH. No flags are affected, | INCA Increment Accumulator by 1 Byte1 Cycle 1 INC Rn Increment register Bytel Cycle Example : INC R2 : Increments contents of R2 by 1 INC direct Increment direct byte Byte2 Cyclel — . Exainple : INC 20H : Increments contents of memory location whose address is given within the instruction (20H) by 1 INC @Ri Increment indirect RAM Bytel © Cycle 1 Example : INC @R2 : increment contents of memory location whose address is given by register R: INC DPTR Increment Daia Pointer by i Byte1 Cycle 2 ryies: 1/2 Cycles DEC : Decrement Description : ‘The variable indicate: emented by 1. An original value of 00H will underflow to OFFH. No flags are affected, DEC A Decrement Accumulator Byte1 Cycle 1 DEC Rn Decrement register Bytel Cyde1 Example : DEC R3 : Decrements contents of R3 by 1 DEC direct Decrement direct byte Byte2 Cyde1 Example : DEC 20H : Decrements the contents of memery location whose address is 20H by 1 DEC @Ri Decrement indirect RAM Bytel Cyde i Example Decrements the contents ation whose acid given by register TECHNICAL PUBLICATIONS® - an up-thrust for knowledgeInstruction Set and Programm Embedded Systems and loT ease EEE adaition : 8051. Table shows the list of addition instructions supported by 8051 rn Bytes : 1/2 Cycles : 4 ADD A, : Add wving the result in | Description : Adds the byte variable indicated to the Accumulator, leaving spectively, | the Accumulator. The carry and auxiliary-carry Ne Nerve Bt | there is a carry-out from bit 7 or bit 3, and cleared, tines Beda ' ‘When adding signed integers, OV indicates a eee two negative i the sum of two positive operands, or a positive sum i | operands. peer nens y ee Byte 1 | ADD A, Rn Add register to Accumulator a : Example : ADD A, R2 : Adds contents of A and R2 and store _ = result in A oe : Ff : Byte2 Cycle i | ADDA, direct Add dizect byte to Accumulator Dey, Pre? Veees |. Example : ADD A, 20H ; Adds contents of A and memory whose i address is 20H and store result in A. es | ADD A,@Ri Add indirect RAM to Accumulator oe Byte! Gyles | Eample : ADD A, @R2: Adds the contents of A and memory whose address is given by register R2 and stores result in ae ADD A, #data Add immediate data to Accumulator Exampl ADD A, #20H : Adds the contenis of A and 20H | ADDC A, : Add with Carry Bytes: 1/2 Cycles : 1 | Description : ADDC simultaneously adds the byte variable indicated, the carry flag and the Accumulator, respectively, if there is a carry-out from bit 7 or bit 3, and cleared otherwise. | ADDC A, Rn Add register to Accumulator with carry flag Bytel Cycle 1 | Example : ADDC A, R2 : Adds the contents of A, R2 and carry _ flag, and stores result in A. : | ADDCA, direct Add direct byte to A with carry flag Byte2 Cyde1 | Example : ADDC A, 20H : Adds the contents of A, memory | location whose address is 20H and the carry flag and stores result in A, 2 ‘ ADDC A, @Ri Add indirect RAM to A with carry flag Example : ADDC A, @R2: Adds the contenis of A, memory location whose address is given by register R2 and the carry flag and stores result in the’. © Z Byte1 Cyde1 ADDC A, #data Add immediate data to A with carry flag Byte 2 Cycle t Example : ADDC A, #20H : Adds the contents f flag and 20H and stores result in a © Ad carry TECHNICAL PUBLICA TIONs® = N UD-thryet fnr 4...Embedded Systems and loT 2-15 Instruction Set and Programming EGE! subtraction Table shows the list of subtraction instructions supported by 8051. SUBB A, : Subtract with Borrow Description : Precaution : SUBB A, Rn Example : SUBB A,direct Example : SUBB AORi ‘Example : SUBB A,tdata Example : Bytes: U2 Cycles : 1 Accumulator, leaving the result in the Accumulator. SUBB sets the carry (borrow) flag if a borrow is needed for bit 7, and clears otherwise. AC is set | if a borrow is needed for bit 3 and cleared otherwise. OV is set _38 needed into bit 6, but not into bit 7 or into bit 7, but not bit 6. 1 | | SUBB subtracts the indicated variable and the cary flag together from the | | aborrow | i If the state of the carry is not known before starting a single or | multiple-precision subtraction, it should be explicitly cleared by aCLRC instruction. | __ Subtract register from A with borrow Byte | Cyned __ SUBB A, R3 : Subtracts contents of R3 and carry together from A and stores results in A. z SUBB A, 20H : Subtracts the contents of memory location 20H and carry together from A stores result inA. Subtract indirect RAM from A with borrow Bytel Cycle 1 SUBB A, @R2 : Subtracts the contents of memory oe location whose address is given by R2 and carry 1 together from A and stores result in A. | / a Subtract direct byte from A with borrow Byte2 — Cyde1 ] : Subtract immediate data from A with borrow Byte2 Cycle SUBB A, #20H : Subtracts 20H from A and stores result | ind. EZ] multiplication and Division | MUL AB : Multiply Bytes:1 Cycles: 4 Description Example : MUL AB multiplies the unsigned eight-bit integers in the Accumulator and register B. The low-order byte of the sixteen-bit product is left in the ‘Accumulator, and the high-order byte in B. If the product is greater than 255 (FFH) the overflow flag is set; otherwise it is cleared. The carry flag is always cleared. | Originally the Accumulator holds the value 80 (50H), Register B holds the value 160 (0AOH). The instruction, MUL AB will give the product 12,800 (3200), so B is changed to 32H (001100108) and the Accumulator is cleared. The overflow flag is set, carry is cleared. TECHNICAL PUBLICATIONS® - an up-thrust for knowledge| DIV AB : Divide Description : 3._List the arithmetic instructions of mieroco [EI Bit Level Logical Instructions Bit level manipulations are very convenient when it is ne particular bit in the internal RAM or SFRs, The internal ‘Thus the final result = 1. What is the time taken to exet How can you perform multiplication using 8051 microcontrol instruction Se and Programing + yes Cycles: 4 q «coer in the Accumulator by the DIV AB divides the unsigned eight intege’ the tor receives the integer "unsigned eightbit integer in register B. The ACCENT er The camy and pattof the quotient register B receives the integ! OV flags will be cleared. seed on the valves returned inthe Exception : If B had originally contained 00H, OW vo erflow flag will be ‘Accumulator and Brregister will be undefined an set. The carry flag is cleared in any case: | | | | | tains 18 (2H or | ‘The Accumilator contains 250 OFBH or 111110108) and B commer ase (000100108). The instruction, DIV AB will leave fa Ee naa) | 00001101B) and the value 16 (10H or 00010000B) este } Carry and OV will both be cleared. a4 Bytes :1 Cycles: | ; i it ‘ing from the earlier i Adjusts the eight-bit value in the Accumulator resulting | addition of two variables (each in packed-BCD format), to produce packed-BCD result. : If the lower nibble of the accumulator is greater than 9 or AF is set, it corrects the result by adding 06 in the lower nibble. If the upper nibble of the { accumulator is greater than 9 or CF is set, it corrects the result by adding 06 in the upper nibble. A= 55H, B= 68H and CF =1. Then instruction sequence | ADDC A, R3 DAA | will frst perform a standard binary addition, resulting in the value BEH. | (IO11110) in the Accumulator. The carry and auxiliary carry flags will be cleared. Since lowe: le > 9, Lower nibble = H = 4H with AF =1 j nibble > 9, Upper nibble = BH + 6H + AF(1) = 2H with CF =1 ' 24, which is yalid BCD sum, Since upper te MUL instruction i 8031 ? roller 8051 ‘cessary to set or reset @ RAM of 8051 from address 20H TECHNICAL PUBLICATIONS® « an up-thust for krowlog Ist for knowledge