Module-02

Important Questions

Q. Write down important features of 8086 Microprocessor along with its architecture.

Ans. Some of the important features of 8086 microprocessor are are as follows:

o Intel 8086 microprocessor is the enhanced version of Intel 8085 microprocessor. It was
designed by Intel in 1976.
o The 8086 microprocessor is a16-bit, N-channel, HMOS microprocessor. Where the
HMOS is used for "High-speed Metal Oxide Semiconductor".
o Intel 8086 is built on a single semiconductor chip and packaged in a 40-pin IC package.
The type of package is DIP (Dual Inline Package).
o Intel 8086 uses 20 address lines and 16 data- lines. It can directly address up to 2 20 = 1
Mbyte of memory.
o It consists of a powerful instruction set, which provides operation like division and
multiplication very quickly.
o 8086 is designed to operate in two modes, i.e., Minimum and Maximum mode.
Q.- Differentiate between 8085 and 8086 Microprocessor

Ans.- Difference between 8085 and 8086 Microprocessor

8085 Microprocessor 8086 Microprocessor

It is an 8-bit microprocessor. It is a 16-bit microprocessor.

It has a 16-bit address line. It has a 20-bit address line.

It has a 8-bit data bus. It has a 16-bit data bus.

The memory capacity is 64 KB. The memory capacity is 1 MB.

The Clock speed of this microprocessor is 3 The Clock speed of this microprocessor
MHz. varies between 5, 8 and 10 MHz for
different versions.
 It has five flags. It has nine flags.

8085 microprocessor does not support 8086 microprocessor supports memory

memory segmentation. segmentation.

It does not support pipelining. It supports pipelining.

It is accumulator based processor. It is general purpose register based

processor.

It has no minimum or maximum mode. It has minimum and maximum modes.

In 8085, only one processor is used. In 8086, more than one processor is used.
An additional external processor can also be
employed.

It contains less number of transistors It contains more number of transistors

compare to 8086 microprocessor. It contains compare to 8085 microprocessor. It
about 6500 transistor. contains about 29000 in size.

The cost of 8085 is low. The cost of 8086 is high.

Q. Explain 8086 pins configuration

Ans.- 8086 pins configuration

The description of the pins of 8086 is as follows:

AD0-AD15 (Address Data Bus): Bidirectional address/data lines. These are low order address
bus. They are multiplexed with data.

When these lines are used to transmit memory address, the symbol A is used instead of AD, for
example, A0- A15.

A16 - A19 (Output): High order address lines. These are multiplexed with status signals.

A16/S3, A17/S4: A16 and A17 are multiplexed with segment identifier signals S3 and S4.

A18/S5: A18 is multiplexed with interrupt status S5.

A19/S6: A19 is multiplexed with status signal S6.

BHE/S7 (Output): Bus High Enable/Status. During T1, it is low. It enables the data onto the
most significant half of data bus, D8-D15. 8-bit device connected to upper half of the data bus
use BHE signal. It is multiplexed with status signal S7. S7 signal is available during T3 and T4.

RD (Read): For read operation. It is an output signal. It is active when LOW.

Ready (Input): The addressed memory or I/O sends acknowledgment through this pin. When
HIGH, it denotes that the peripheral is ready to transfer data.

RESET (Input): System reset. The signal is active HIGH.

CLK (input): Clock 5, 8 or 10 MHz.

INTR: Interrupt Request.

NMI (Input): Non-maskable interrupt request.

TEST (Input): Wait for test control. When LOW the microprocessor continues execution
otherwise waits.

VCC: Power supply +5V dc.

GND: Ground.

Operating Modes of 8086

There are two operating modes of operation for Intel 8086, namely the minimum mode and
the maximum mode.

When only one 8086 CPU is to be used in a microprocessor system, the 8086 is used in
the Minimum mode of operation.

In a multiprocessor system 8086 operates in the Maximum mode.

Pin Description for Minimum Mode

In this minimum mode of operation, the pin MN/MX is connected to 5V D.C. supply i.e.
MN/MX = VCC.

The description about the pins from 24 to 31 for the minimum mode is as follows:

INTA (Output): Pin number 24 interrupts acknowledgement. On receiving interrupt signal, the
processor issues an interrupt acknowledgment signal. It is active LOW.
ALE (Output): Pin no. 25. Address latch enable. It goes HIGH during T1. The microprocessor
8086 sends this signal to latch the address into the Intel 8282/8283 latch.

DEN (Output): Pin no. 26. Data Enable. When Intel 8287/8286 octal bus transceiver is used
this signal. It is active LOW.

DT/R (output): Pin No. 27 data Transmit/Receives. When Intel 8287/8286 octal bus transceiver
is used this signal controls the direction of data flow through the transceiver. When it is HIGH,
data is sent out. When it is LOW, data is received.

M/IO (Output): Pin no. 28, Memory or I/O access. When this signal is HIGH, the CPU wants
to access memory. When this signal is LOW, the CPU wants to access I/O device.

WR (Output): Pin no. 29, Write. When this signal is LOW, the CPU performs memory or I/O
write operation.

HLDA (Output): Pin no. 30, Hold Acknowledgment. It is sent by the processor when it receives
HOLD signal. It is active HIGH signal. When HOLD is removed HLDA goes LOW.

HOLD (Input): Pin no. 31, Hold. When another device in microcomputer system wants to use
the address and data bus, it sends HOLD request to CPU through this pin. It is an active HIGH
signal.

Pin Description for Maximum Mode

In the maximum mode of operation, the pin MN/¯MX is made LOW. It is grounded. The
description about the pins from 24 to 31 is as follows:

QS1, QS0 (Output): Pin numbers 24, 25, Instruction Queue Status. Logics are given below:

QS1 QS0 Operation

0 0 No operation

0 1 1st byte of opcode from queue.

1 0 Empty the queue

1 1 Subsequent byte from queue

S0, S1, S2 (Output): Pin numbers 26, 27, 28 Status Signals. These signals are connected to the
bus controller of Intel 8288. This bus controller generates memory and I/O access control
signals. Logics for status signal are given below:
 S2 S1 S0 Operation

0 0 0 Interrupt acknowledgement

0 0 1 Read data from I/O port

0 1 0 Write data from I/O port

0 1 1 Halt

1 0 0 Opcode fetch

1 0 1 Memory read

1 1 0 Memory write

1 1 1 Passive state

LOCK (Output): Pin no. 29. It is an active LOW signal. When this signal is LOW, all
interrupts are masked and no HOLD request is granted. In a multiprocessor system all other
processors are informed through this signal that they should not ask the CPU for relinquishing
the bus control.

RG/GT1, RQ/GT0 (Bidirectional): Pin numbers 30, 31, Local Bus Priority Control. Other
processors ask the CPU by these lines to release the local bus.

In the maximum mode of operation signals WR, ALE, DEN, DT/R etc. are not available
directly from the processor. These signals are available from the controller 8288.

Q. Explain the Functional units of 8086

Ans.- 8086 contains two independent functional units: a Bus Interface Unit (BIU) and
an Execution Unit (EU).
Fig: Block Diagram of Intel 8086 Microprocessor (8086 Architecture)

Bus Interface Unit (BIU)

The segment registers, instruction pointer and 6-byte instruction queue are associated with the
bus interface unit (BIU).

The BIU:

o Handles transfer of data and addresses,

o Fetches instruction codes, stores fetched instruction codes in first-in-first-out register set
called a queue,
o Reads data from memory and I/O devices,
o Writes data to memory and I/O devices,
 o It relocates addresses of operands since it gets un-relocated operand addresses from EU.
The EU tells the BIU from where to fetch instructions or where to read data.

It has the following functional parts:

o Instruction Queue: When EU executes instructions, the BIU gets 6-bytes of the next
instruction and stores them in the instruction queue and this process is known as
instruction pre fetch. This process increases the speed of the processor.
o Segment Registers: A segment register contains the addresses of instructions and data in
memory which are used by the processor to access memory locations. It points to the
starting address of a memory segment currently being used.
There are 4 segment registers in 8086 as given below:
o Code Segment Register (CS): Code segment of the memory holds instruction
codes of a program.
o Data Segment Register (DS): The data, variables and constants given in the
program are held in the data segment of the memory.
o Stack Segment Register (SS): Stack segment holds addresses and data of
subroutines. It also holds the contents of registers and memory locations given in
PUSH instruction.
o Extra Segment Register (ES): Extra segment holds the destination addresses of
some data of certain string instructions.

o Instruction Pointer (IP): The instruction pointer in the 8086 microprocessor acts as a
program counter. It indicates to the address of the next instruction to be executed.

Execution Unit (EU)

o The EU receives opcode of an instruction from the queue, decodes it and then executes it.
While Execution, unit decodes or executes an instruction, then the BIU fetches
instruction codes from the memory and stores them in the queue.
o The BIU and EU operate in parallel independently. This makes processing faster.
o General purpose registers, stack pointer, base pointer and index registers, ALU, flag
registers (FLAGS), instruction decoder and timing and control unit constitute execution
unit (EU). Let's discuss them:
 o General Purpose Registers: There are four 16-bit general purpose registers: AX
(Accumulator Register), BX (Base Register), CX (Counter) and DX. Each of these 16-bit
registers are further subdivided into 8-bit registers as shown below:

16-bit 8-bit high-order 8-bit low-order

registers registers registers

AX AH AL

BX BH BL

CX CH CL

DX DH DL

o Index Register: The following four registers are in the group of pointer and index
registers:
o Stack Pointer (SP)
o Base Pointer (BP)
o Source Index (SI)
o Destination Index (DI)
o ALU: It handles all arithmetic and logical operations. Such as addition, subtraction,
multiplication, division, AND, OR, NOT operations.
o Flag Register: It is a 16?bit register which exactly behaves like a flip-flop, means it
changes states according to the result stored in the accumulator. It has 9 flags and they
are divided into 2 groups i.e. conditional and control flags.
o Conditional Flags: This flag represents the result of the last arithmetic or logical
instruction executed. Conditional flags are:
o Carry Flag
o Auxiliary Flag
o Parity Flag
o Zero Flag
o Sign Flag
o Overflow Flag
o Control Flags: It controls the operations of the execution unit. Control flags are:
 o Trap Flag
o Interrupt Flag
o Direction Flag

Q.- Explain the Interrupts in 8086 microprocessor

Ans.- Interrupt is a process of creating a temporary halt during program execution and allows
peripheral devices to access the microprocessor.

Microprocessor responds to these interrupts with an interrupt service routine (ISR), which is a
short program or subroutine to instruct the microprocessor on how to handle the interrupt.

There are different types of interrupt in 8086:

Hardware Interrupts

Hardware interrupts are that type of interrupt which are caused by any peripheral device by
sending a signal through a specified pin to the microprocessor.

The Intel 8086 has two hardware interrupt pins:

o NMI (Non-Maskbale Interrupt)

o INTR (Interrupt Request) Maskable Interrupt.
NMI: NMI is a single Non-Maskable Interrupt having higher priority than the maskable
interrupt.

o It cannot be disabled (masked) by user using software.

o It is used by the processor to handle emergency conditions.
For example: It can be used to save program and data in case of power failure. An
external electronic circuitry is used to detect power failure, and to send an interrupt signal
to 8086 through NMI line.

INTR: The INTR is a maskable interrupt. It can be enabled/disabled using interrupt flag (IF).
After receiving INTR from external device, the 8086 acknowledges through INTA signal.

It executes two consecutive interrupt acknowledge bus cycles.

Software Interrupt

A microprocessor can also be interrupted by internal abnormal conditions such as overflow;

division by zero; etc. A programmer can also interrupt microprocessor by inserting INT
instruction at the desired point in the program while debugging a program. Such an interrupt is
called a software interrupt.

The interrupt caused by an internal abnormal conditions also came under the heading of software
interrupt.

Example of software interrupts are:

o TYPE 0 (division by zero)

o TYPE 1 (single step execution for debugging a program)
o TYPE 2 represents NMI (power failure condition)
o TYPE 3 (break point interrupt)
o TYPE 4 (overflow interrupt)

Interrupt pointer table for 8086

Fig: Interrupt pointer table for 8086

The 8086 can handle up to 256, hardware and software interrupts.

1KB memory acts as a table to contain interrupt vectors (or interrupt pointers), and it is called
interrupt vector table or interrupt pointer table. The 256 interrupt pointers have been numbered
from 0 to 255 (FF hex). The number assigned to an interrupt pointer is known as type of that
interrupt. For example, Type 0, Type 1, Type 2,...........Type 255 interrupt.

Q. What are the addressing modes of 8086

Ans. The way for which an operand is specified for an instruction in the accumulator, in a
general purpose register or in memory location, is called addressing mode.
The 8086 microprocessors have 8 addressing modes. Two addressing modes have been provided
for instructions which operate on register or immediate data.

These two addressing modes are:

Register Addressing: In register addressing, the operand is placed in one of the 16-bit or 8-bit
general purpose registers.

Example

o MOV AX, CX
o ADD AL, BL
o ADD CX, DX

Immediate Addressing: In immediate addressing, the operand is specified in the instruction

itself.

Example

o MOV AL, 35H

o MOV BX, 0301H
o MOV [0401], 3598H
o ADD AX, 4836H

The remaining 6 addressing modes specify the location of an operand which is placed in a
memory.

These 6 addressing modes are:

Direct Addressing: In direct addressing mode, the operand?s offset is given in the instruction as
an 8-bit or 16-bit displacement element.

Example

o ADD AL, [0301]

The instruction adds the content of the offset address 0301 to AL. the operand is placed at the
given offset (0301) within the data segment DS.

Register Indirect Addressing: The operand's offset is placed in any one of the registers BX,
BP, SI or DI as specified in the instruction.
Example

o MOV AX, [BX]

It moves the contents of memory locations addressed by the register BX to the register AX.

Based Addressing: The operand's offset is the sum of an 8-bit or 16-bit displacement and the
contents of the base register BX or BP. BX is used as base register for data segment, and the BP
is used as a base register for stack segment.

Effective address (Offset) = [BX + 8-bit or 16-bit displacement].

Example

o MOV AL, [BX+05]; an example of 8-bit displacement.

o MOV AL, [BX + 1346H]; example of 16-bit displacement.

Indexed Addressing: The offset of an operand is the sum of the content of an index register SI
or DI and an 8-bit or 16-bit displacement.

Offset (Effective Address) = [SI or DI + 8-bit or 16-bit displacement]

Example

o MOV AX, [SI + 05]; 8-bit displacement.

o MOV AX, [SI + 1528H]; 16-bit displacement.

Based Indexed Addressing: The offset of operand is the sum of the content of a base register
BX or BP and an index register SI or DI.

Effective Address (Offset) = [BX or BP] + [SI or DI]

Here, BX is used for a base register for data segment, and BP is used as a base register for stack
segment.

Example

o ADD AX, [BX + SI]

o MOV CX, [BX + SI]

Based Indexed with Displacement: In this mode of addressing, the operand's offset is given by:

Effective Address (Offset) = [BX or BP] + [SI or DI] + 8-bit or 16-bit displacement
Example

o MOV AX, [BX + SI + 05]; 8-bit displacement

o MOV AX, [BX + SI + 1235H]; 16-bit displacement

Q. Explain Hardwired and Micro-programmed Control Unit.

Ans.- In a system or computer, most of the tasks are controlled with the help of a processor or
CPU (Central processing unit), which is the main component of a computer. The CPU usually
has two main systems: control unit (CU) and arithmetic and logic unit (ALU). The control unit
(CU) is used to synchronize the tasks with the help of sending timings and control signals. On
the other hand, mathematical and logical operations can be handled with the help of ALU. Micro
programmed control units and hardwired control units can be called two types of control units.
We can execute an instruction with the help of these two control units.

In the hardwired control unit, the execution of operations is much faster, but the
implementation, modification, and decoding are difficult. In contrast, implementing, modifying,
decoding micro-programmed control units is very easy. The micro-programmed control unit is
also able to handle complex instructions. With the help of control signals generated by micro-
programmed and hardwired control units, we are able to fetch and execute the instructions.

Control Signals

In order to generate the control signals, both the control signals were basically designed. The
functionality of a processor's hardware is operated with the help of these control signals. The
control signals are used to know about various types of things, which are described as follows:

o Control signals are used to know what operation is going to be performed.

o It is used to know about the sequence of operations that are performed by the processor.
o It is used to know about the timing at which an operation must be executed and many
other types of things.

Hardwired Control Unit

With the help of generating control signals, the hardwired control unit is able to execute the
instructions at a correct time and proper sequence. As compared to the micro-programmed, the
hardwired CU is generally faster. In this CU, the control signals are generated with the help of
PLA circuit and state counter. Here the Central processing unit requires all these control signals.
With the help of hardware, the hardwired control signals are generated, and it basically uses the
circuitry approach.

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The image of a hardwired control unit is described as follows, which contains various
components in the form of circuitry. We will discuss them one by one so that we can properly
understand the "generation of control signals".

o The instruction register is a type of processor register used to contain an instruction that
is currently in execution. As we can see, the instruction register is used to generate the
OP-code bits respective of the operation as well as the addressing mode of operands.
o The above generated Op-code bits are received in the field of an instruction decoder.
The instruction decoder interprets the operation and instruction's addressing mode. Now
on the basis of the addressing mode of instruction and operation which exists in the
instruction register, the instruction decoder sets the corresponding Instruction signal
INSi to 1. Some steps are used to execute each instruction, i.e., instruction
fetch, decode, operand fetch, Arithmetic and logical unit, and memory store.
Different books might be contained different steps. But in general, we are able to execute
an instruction with the help of these five steps.
 o The information about the current step of instruction must be known by the control unit.
Now the Step Counter is implemented, which is used to contain the signals from T1,….,
T5. Now on the basis of the step which contains the instruction, one of the signals of a
step counter will be set from T1 to T5 to 1.
o Now we have a question that how the step counter knows about the current step of
instruction? So to know the current step, a Clock is implemented. The one-clock cycle of
the clock will be completed for each step. For example, suppose that if the stop counter
sets T3 to 1, then after completing one clock cycle, the step counter will set T4 to 1.
o Now we have a question, i.e., what will happen if the execution of an instruction is
interrupted for some reason? Will the step counter still be triggered by the clock? The
answer to this question is No. As long as the execution is current step is completed,
the Counter Enable will "disable" the Step Counter so that it will stop then increment to
the next step signal.
o Now we have a question, i.e., what if the execution of instruction depends on some
conditions? In this case, the Condition Signals will be used. There are various conditions
in which the signals are generated with the help of control signals that can be less than,
greater than, less than equal, greater than equal, and many more.
o The external input is the last one. It is used to tell the Control Signal Generator about the
interrupts, which will affect the execution of an instruction.

So, on the basis of the input obtained by the conditional signals, step counter, external inputs,
and instruction register, the control signals will be generated with the help of Control signal
Generator.

Micro-programmed Control Unit

A micro-programmed control unit can be described as a simple logic circuit. We can use it in two
ways, i.e., it is able to execute each instruction with the help of generating control signals, and it
is also able to do sequencing through microinstructions. It will generate the control signals with
the help of programs. At the time of evolution of CISC architecture in the past, this approach was
very famous. The program which is used to create the control signals is known as the "Micro-
program". The micro-program is placed on the processor chip, which is a type of fast memory.
This memory is also known as the control store or control memory.

A micro-program is used to contain a set of microinstructions. Each microinstruction or control

word contains different bit patterns. The n bit words are contained by each microinstruction. On
the basis of the bit pattern of a control word, every control signals differ from each other.
Like the above, the instruction execution in a micro-programmed control unit is also performed
in steps. So for each step, the micro-program contains a control word/ microinstruction. If we
want to execute a particular instruction, we need a sequence of microinstructions. This process is
known as the micro-routine. The image of a micro-programmed control unit is described as
follows. Here, we will learn the organization of micro-program, micro-routine, and control word/
microinstruction.

Now we will learn about the organization of Micro-program CU. Then we will learn about the
flow of instruction execution with the help of instruction execution steps, which are described as
follows:

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o Instruction fetch is the first step. In this step, the instruction is fetched from the IR
(Instruction Register) with the help of a Microinstruction address register.
o Decode is the second step. In this step, the instructions obtained from the instruction
register will be decoded with the help of a microinstruction address generator. Here we
will also get the starting address of a micro-routine. With the help of this address, we can
easily perform the operation, which is mentioned in the instruction. It will also load the
starting address into the micro-program counter.
o Increment is the third step. In this step, the control word, which corresponds to the
starting address of a micro-program, will be read. When the execution proceeds, the value
of the micro-program counter will be increased so that it can read the successive control
words of a micro-routine.
 o End bit is the fourth step. In this step, the microinstruction of a micro-routine contains a
bit, which is known as the end bit. The execution of the microinstruction will be
successfully completed when the end bit is set to 1.
o This is the last step, and in this step, the micro-program address generator will again go
back to Step 1 so that we can fetch a new instruction, and this process or cycle goes on.

So in the micro-programmed control unit, the micro-programs are stored with the help of Control
memory or Control store. The implementation of this CU is very easy and flexible, but it is
slower as compared to the Hardwired control unit.

Q. Differentiate between Hardwired Control unit and Micro-programmed Control unit

Ans. There are various differences between Micro-programmed CU and Hardwired CU, which
are described as follows:

Hardwired Control Unit Micro-programmed Control Unit

With the help of a hardware circuit, we can While with the help of programming, we can
implement the hardwired control unit. In implement the micro-programmed control
other words, we can say that it is a circuitry unit.
approach.

The hardwired control unit uses the logic The micro-programmed CU uses
circuit so that it can generate the control microinstruction so that it can generate the
signals, which are required for the processor. control signals. Usually, control memory is
used to store these microinstructions.

In this CU, the control signals are going to be It is very easy to modify the micro-
generated in the form of hard wired. That's programmed control unit because the
why it is very difficult to modify the modifications are going to be performed only
hardwired control unit. at the instruction level.

In the form of logic gates, everything has to The micro-programmed control unit is less
be realized in the hardwired control unit. costly as compared to the hardwired CU
That's why this CU is more costly as because this control unit only requires the
compared to the micro-programmed control microinstruction to generate the control
unit. signals.

The complex instructions cannot be handled The micro-programmed control unit is able
 by a hardwired control unit because when we to handle the complex instructions.
design a circuit for this instruction, it will
become complex.

Because of the hardware implementation, the The micro-programmed control unit is able
hardwired control unit is able to use a limited to generate control signals for many
number of instructions. instructions.

The hardwired control unit is used in those The micro-programmed control unit is used
types of computers that also use the RISC in those types of computers that also use the
(Reduced instruction Set Computers). CISC (Complex instruction Set Computers).

In the hardwired control unit, the hardware is In this CU, the microinstructions are used to
used to generate only the required control generate the control signals. That's why this
signals. That's why this control unit is faster CU is slower than the hardwired control unit.
as compared to the micro-programmed
control unit.

Some Other differences between Micro-programmed control unit and Hardwire control
unit

Now we will describe these differences on the basis of some parameters, such as speed, cost,
modification, instruction decoder, control memory, etc. These differences are described as
follows:

Speed

In the hardwired control unit, the speed of operations is very fast. In contrast, the micro-
programmed control unit needs frequent memory access. So the speed of operation of a micro-
programmed control unit is slow.

Modification

If we want to do some modifications to the Hardwired control unit, we have to redesign the
entire unit. In contrast, if we want to do some modification in the micro-programmed control
unit, we can do that just by changing the microinstructions in the control memory. In this case,
the more flexible control unit is a micro-programmed control unit.

Cost
The implementation of a Hardwire control unit is very much compared to the Micro-
programmed control unit. In this case, the micro-programmed control unit will save our money at
the time of implementation.

Handling Complex Instructions

If we try to handle the complex instructions with the help of a hardwired control unit, it will be
very difficult for us to handle them. But if we try to handle the complex instructions with the
help of micro-programmed control unit, it will be very easy for us to handle them. In this case
also, the Micro-programmed control unit is better.

Instruction decoding

In the hardwired control unit, if we want to perform instruction decoding, it will be very difficult.
But if we do the same thing in a micro-programmed control unit, it will be very easy for us.

Instruction set size

A small instruction set is used by the hardwired CU. On the other hand, a large instruction set is
used by the micro-programmed control unit.

Control Memory

The hardwired control unit does not use the control memory to generate the control signals, but
the micro-programmed CU needs to use the control memory to generate the control signals.

Applications

The hardwired control unit is used in those types of processors that basically use a simple
instruction set. This set is called a Reduced Instruction Set Computer. On the other hand, a
micro-programmed control unit is used in those types of processors that basically use a complex
instruction set. This set is called a Complex Instruction Set Computer.

Q. – Explain Input-Output Interface in CPU environment.

Ans.- Input-Output Interface is used as a method which helps in transferring of information
between the internal storage devices i.e. memory and the external peripheral device. A
peripheral device is that which provide input and output for the computer, it is also called
Input-Output devices. For Example: A keyboard and mouse provide Input to the computer are
called input devices while a monitor and printer that provide output to the computer are called
output devices. Just like the external hard-drives, there is also availability of some peripheral
devices which are able to provide both input and output.
 Input-Output Interface
In micro-computer base system, the only purpose of peripheral devices is just to
provide special communication links for the interfacing them with the CPU. To resolve the
differences between peripheral devices and CPU, there is a special need for communication
links.
The major differences are as follows:
1. The nature of peripheral devices is electromagnetic and electro-mechanical. The nature of
the CPU is electronic. There is a lot of difference in the mode of operation of both
peripheral devices and CPU.
2. There is also a synchronization mechanism because the data transfer rate of peripheral
devices are slow than CPU.
3. In peripheral devices, data code and formats are differ from the format in the CPU and
memory.
4. The operating mode of peripheral devices are different and each may be controlled so as
not to disturb the operation of other peripheral devices connected to CPU.
There is a special need of the additional hardware to resolve the differences between CPU and
peripheral devices to supervise and synchronize all input and output devices.
Functions of Input-Output Interface:
1. It is used to synchronize the operating speed of CPU with respect to input-output devices.
2. It selects the input-output device which is appropriate for the interpretation of the input-
output signal.
3. It is capable of providing signals like control and timing signals.
4. In this data buffering can be possible through data bus.
5. There are various error detectors.
6. It converts serial data into parallel data and vice-versa.
7. It also convert digital data into analog signal and vice-versa.

The method that is used to transfer information between internal storage and external I/O
devices is known as I/O interface. The CPU is interfaced using special communication links by
the peripherals connected to any computer system. These communication links are used to
resolve the differences between CPU and peripheral. There exists special hardware
components between CPU and peripherals to supervise and synchronize all the input and
output transfers that are called interface units.
Q. Explain the data Transfer in CPU systems.
Ans. The binary information that is received from an external device is usually stored in the
memory unit. The information that is transferred from the CPU to the external device is
originated from the memory unit. CPU merely processes the information but the source and
target is always the memory unit. Data transfer between CPU and the I/O devices may be done
in different modes. Data transfer to and from the peripherals may be done in any of the three
possible ways
1. Programmed I/O.
2. Interrupt- initiated I/O.
3. Direct memory access( DMA).
Now let’s discuss each mode one by one.
1. Programmed I/O: It is due to the result of the I/O instructions that are written in the
computer program. Each data item transfer is initiated by an instruction in the program.
Usually the transfer is from a CPU register and memory. In this case it requires constant
monitoring by the CPU of the peripheral devices.
Example of Programmed I/O: In this case, the I/O device does not have direct access to
the memory unit. A transfer from I/O device to memory requires the execution of several
instructions by the CPU, including an input instruction to transfer the data from device to
the CPU and store instruction to transfer the data from CPU to memory. In programmed
I/O, the CPU stays in the program loop until the I/O unit indicates that it is ready for data
transfer. This is a time consuming process since it needlessly keeps the CPU busy. This
situation can be avoided by using an interrupt facility. This is discussed below.
2. Interrupt- initiated I/O: Since in the above case we saw the CPU is kept busy
unnecessarily. This situation can very well be avoided by using an interrupt driven method
for data transfer. By using interrupt facility and special commands to inform the interface
to issue an interrupt request signal whenever data is available from any device. In the
meantime the CPU can proceed for any other program execution. The interface meanwhile
keeps monitoring the device. Whenever it is determined that the device is ready for data
transfer it initiates an interrupt request signal to the computer. Upon detection of an
external interrupt signal the CPU stops momentarily the task that it was already
performing, branches to the service program to process the I/O transfer, and then return to
the task it was originally performing.
 The I/O transfer rate is limited by the speed with which the processor can test and
service a device.
 The processor is tied up in managing an I/O transfer; a number of instructions must be
executed for each I/O transfer.
 Terms:
 Hardware Interrupts: Interrupts present in the hardware pins.
 Software Interrupts: These are the instructions used in the program
whenever the required functionality is needed.
 Vectored interrupts: These interrupts are associated with the static vector
address.
 Non-vectored interrupts: These interrupts are associated with the dynamic
vector address.
 Maskable Interrupts: These interrupts can be enabled or disabled explicitly.
  Non-maskable interrupts: These are always in the enabled state. we cannot
disable them.
 External interrupts: Generated by external devices such as I/O.
 Internal interrupts: These devices are generated by the internal components
of the processor such as power failure, error instruction, temperature sensor,
etc.
 Synchronous interrupts: These interrupts are controlled by the fixed time
interval. All the interval interrupts are called as synchronous interrupts.
 Asynchronous interrupts: These are initiated based on the feedback of
previous instructions. All the external interrupts are called as asynchronous
interrupts.
3. Direct Memory Access: The data transfer between a fast storage media such as magnetic
disk and memory unit is limited by the speed of the CPU. Thus we can allow the
peripherals directly communicate with each other using the memory buses, removing the
intervention of the CPU. This type of data transfer technique is known as DMA or direct
memory access. During DMA the CPU is idle and it has no control over the memory buses.
The DMA controller takes over the buses to manage the transfer directly between the I/O
devices and the memory unit.
1. Bus grant request time.
2. Transfer the entire block of data at transfer rate of device because the device is usually
slow than the speed at which the data can be transferred to CPU.
3. Release the control of the bus back to CPU So, total time taken to transfer the N bytes =
Bus grant request time + (N) * (memory transfer rate) + Bus release control time.
4. Buffer the byte into the buffer
5. Inform the CPU that the device has 1 byte to transfer (i.e. bus grant request)
6. Transfer the byte (at system bus speed)
7. Release the control of the bus back to CPU.

Advantages:

Standardization: I/O interfaces provide a standard way of communicating with external

devices. This means that different devices can be connected to a computer using the same
interface, which makes it easier to swap out devices and reduces the need for specialized
hardware.
Modularity: With I/O interfaces, different devices can be added or removed from a computer
without affecting the other components. This makes it easier to upgrade or replace a faulty
device without affecting the rest of the system.
Efficiency: I/O interfaces can transfer data between the computer and the external devices at
high speeds, which allows for faster data transfer and processing times.
Compatibility: I/O interfaces are designed to be compatible with a wide range of devices,
which means that users can choose from a variety of devices that are compatible with their
computer’s I/O interface.
Disadvantages:

Cost: I/O interfaces can be expensive, especially if specialized hardware is required to connect
a particular device to a computer system.
Complexity: Some I/O interfaces can be complex to configure and require specialized
knowledge to set up and maintain. This can be a disadvantage for users who are not familiar
with the technical aspects of computer hardware.
Compatibility issues: While I/O interfaces are designed to be compatible with a wide range of
devices, there can still be compatibility issues with certain devices. In some cases, device
drivers may need to be installed to ensure proper functionality.
Security risks: I/O interfaces can be a security risk if they are not properly configured or
secured. Hackers can exploit vulnerabilities in I/O interfaces to gain unauthorized access to a
computer system or steal data.