MODULE 2

Assembly language programming of 8051 - addressing modes -

instruction set - simple programs (program for addition,
multiplication, division, data transfer, subtraction, port
reading/writing) -interrupts in 8051 - interrupt types - steps in
interrupt processing - IE special function register – IP special
function register - priority of interrupts
Module 2
Addressing modes
It is the way of locate target data or source operand
1. Immediate
2. Direct
3. Register direct
4. Register indirect
5. Indexed
1.Immediate:
Data available in the instruction itself
MOV A,#5AH
Since it is a 2 byte instruction ,the PC is incremented by two at the end of the
instruction .The # symbol before the hexadecimal number indicates that it is a
data. If the # symbol is not present, then the hexadecimal number would be
treated as an address
2. Direct
Address of the data is available in the instruction
MOV A, direct address
MOVR2, 45H; for getting content from 45H to R2.
3. Register direct
Register name containing data is available in the instruction
MOV A,R3
If R3 contains F5H ,it will be copied to register A
4.Rgister indirect addressing mode
The address of the data is available in the register
MOV A,@R1
R1 contains the address of the data available in the register
5.Indexed
Address of the data is obtained by adding the content of a base register and
an offset register
MOV A,@A+DPTR
Here, the address for the operand is the sum of contents of DPTR and
Accumulator.
• With Indexed Addressing Mode, the effective address of the Operand is
the sum of a base register and an offset register. The Base Register can be
either Data Pointer (DPTR) or Program Counter (PC) while the Offset
register is the Accumulator (A).
• In Indexed Addressing Mode, only MOVC and JMP instructions can be
used. Indexed Addressing Mode is useful when retrieving data from look-
up tables.
• Instruction Set
Based on the operation they perform, all the instructions in the 8051 Microcontroller Instruction Set are divided into
five groups. They are:
• Data Transfer Instructions
• Arithmetic Instructions
• Logical Instructions
• Boolean or Bit Manipulation Instructions
• Program Branching Instructions
1. Data Transfer Instructions
The Data Transfer Instructions are associated with transfer with data between registers or external program memory or
external data memory. The Mnemonics associated with Data Transfer are given below.(MOVE,PUSH,POP AND
EXCHANGE)

• MOV-general data loading and data transfer within internal RAM and SFRs
Move the content of a register Rn to accumulator where n changes from 0 to 7
MOV A,R2
MOV A,R7
MOV R2,A
Move an immediate 8 bit data to register A or Rn or to a memory location
MOV A,#45H
MOV R6,#56H
MOV 33H,#44H
MOV@R0,#0E8H
MOV DPTR,#F5A2H
• MOVC-load accumulator by a byte from program memory
• MOVX- transfer a byte between external RAM and accumulator
• XCH –exchange bytes between two locations within internal memory
• XCHD-exchange digits (lower nibble) between two locations within internal memory
• MOVC-load accumulator by a byte from program memory
• MOVX- transfer a byte between external RAM and accumulator
• XCH –exchange bytes between two locations within internal memory
• XCHD-exchange digits (lower nibble) between two locations within internal memory
• PUSH- store a byte over system Stack
• POP – Load a byte from system stack
These two instructions are related to the stack. Stack is a block of memory location for temporary
storage of data. To store content in the stack we use PUSH instruction and to take data from the
stack we use POP instruction.
2. Arithmetic Instructions
Using Arithmetic Instructions, you can perform addition, subtraction,
multiplication and division. The arithmetic instructions also include increment
by one, decrement by one and a special instruction called Decimal Adjust
Accumulator. The operations performed by the arithmetic instructions affect
flags like carry, overflow, zero, etc. in the PSW Register.
The Mnemonics associated with the Arithmetic Instructions of the 8051
Microcontroller Instruction Set are:
• ADD-add two operands ,all the flags are affected ADD AL,OFH
• ADDC-add two operand with carry ADC AX,BX
• SUBB-subtract one operand from another
• CMP-compare the content of 2 registers ,only flags are affected
• INC- increment operand by one, all flags are modified
• DEC-decrement operand by one, all flags are modified
• MUL-unsigned integer multiplication
• DIV-unsigned integer division
• DAA-decimal adjust for accumulator
3. Logical Instructions
It perform logical operations like AND, OR, XOR, NOT, Rotate, Clear and
Swap. Logical Instruction are performed on Bytes of data on a bit-by-
bit basis.
Mnemonics associated with Logical Instructions are as follows:
• ANL-logical AND operation
• ORL-logical OR operation
• XRL-logical XOR operation
• CLR-clear accumulator
• CPL-complement accumulator
• RL-rotate accumulator left
• RLC-rotate accumulator left through carry
• RR-rotate accumulator right
• RRC-rotate accumulator right through carry
• SWAP-swap nibbles within the accumulator
4.Boolean or Bit Manipulation Instructions
Boolean or Bit Manipulation Instructions will deal with bit variables.These
instructions can perform set, clear, and, or, complement etc.
The Mnemonics corresponding to the Boolean or Bit Manipulation
instructions are:
• CLR-clear bit
• SETB-set bit
• MOV-mov bit
• JC-jump if carry
• JNC-jump if no carry
• JB-jump if bit is set
• JNB-jump if bit is not set
• JBC-jump if bit is set and clear bit
• ANL-logically AND bit with carry
• ORL-Logically OR bit with carry
• CPL-complement bit
5.Program Branching Instructions
These instructions control the flow of program logic. The mnemonics of the
Program Branching Instructions are as follows.
• LJMP-unconditional long jump
• AJMP-unconditional absolute jump
• SJMP-unconditional short jump
• JZ-jump if accumulator is zero
• JNZ-jump if accumulator is zero
• CJNE-compare and jump if not equal
• DJNZ-decrement and jump if not zero
• NOP-No operation
• LCALL-unconditional long call
• ACALL-unconditional absolute call
• RET-return from call
• RETI-return from interrupt
• JMP-jump to the address location indicated by DPTR and A
• All these instructions, except the NOP (No Operation) affect the Program
Counter (PC) in one way or other. Some of these instructions has decision
making capability before transferring control to other part of the program.
• Program for Addition
ORG 0000H -directive indicates the start of the program. ORG 0000h tells
the compiler all subsequent code starting at address 0000h.
MOV A, #05h—Move the Value 05h to Register A
MOV R0, #09H--Move the Value 09h to Register R0
ADD A, R0- Add A value with R0 value and stores the result in A
END
Subtraction:
ORG 0000h
MOV R0, #03H // move the value 3 to register R0//
MOV A, #05H // move the value 5 to accumulator A//
SUBB A, R0 // Result value is stored in the Accumulator A //
END
Multiplication:
ORG 0000h
MOV B, #03H // move the value 3 to the register B//
MOV A, #05H // move the value 5 to accumulator A//
MUL A,B // Multiplied result is stored in the Accumulator A //
END
Division:
ORG 0000h
MOV B, #03H // move the value 3 to register B//
MOV A, #15H // move the value 5 to accumulator A//
DIV AB // final value is stored in the Accumulator A //
END
Program for data transfer
Let N = 05h, location A: 30h location B: 40h
mov r0,#30h //source address
mov r1,#40h //destination address
mov r7,#05h //Number of bytes to be moved
back: mov a,@r0
mov @r1,a
inc r0
inc r1
djnz r7,back //repeat till all data transferred
end
8051 interrupts:

• An interrupt is a signal which forces the processor to leave its current

sequence of activities and jump to another predefined set of activities .
• During program execution, if peripheral devices needs service from
microcontroller ,device will generate interrupt and then get the service
from microcontroller
• When peripheral device activate the interrupt signal, the processor
branches to a program called interrupt service routine (ISR).
• After executing ISR the processor returns to the main program and
execute the remaining instruction.
Steps in interrupt processing
When an interrupt comes microcontroller perform the following operation
1.Complete the execution of the current instruction
2.PSW is pushed to stack
3.PC content is pushed to stack
4.Interrupt flag is reset
5.PC is loaded with ISR address
Then execute interrupt
ISR will always ends with RET instruction. The execution of RET instruction
results in:-
1.POP the current stack top to PC
2. POP the current stack top to PSW
Classification of interrupts
1.
• External interrupts
• Internal interrupts
External interrupts are initiated by the peripheral devices through the
external pins of the microcontroller.
External interrupt 0-INT0
External interrupt 1-INT1
Internal interrupts are activated by internal peripherals ( like timers and serial
input output ports ) of the microcontroller.
Timer 0 Interrupt
Timer 1 Interrupt
Serial Interrupt
2.
• Maskable Interrupt
• Non Maskable Interrupt
Maskable interrupts can be disables by the controller using program
Non maskable interrupts cannot disable by the program
3.
• Vectored Interrupt
• Non vectored Interrupt
Classified on the basis of the address of the service routine.
If the address of the service routine is fixed or predefined (starting address)
,it is known as vectored interrupt .
Starting address is provided by the peripherals then it is known as non
vectored interrupts. Peripheral device send request to microcontroller. With
respect to this request,MC will send an acknowledgement signal(INTA) to the
peripheral device .After receiving the acknowledgment peripheral device
sends the interrupt vector address to MC.
8051 Interrupts:
There are 5 interrupts in 8051
Among this two external interrupt and 3 internal interrupt
All these 5 interrupts are maskable and vectored

Interrupts Vector Address Priority

External interrupt 0 (INT0) 0003 1 (Highest)
Timer 0 000B 2
External interrupt 1 (INT1) 0013 3
Timer 1 001B 4
Serial interrupt 0023 5(Lowest)
Special function registers (SFR) related to interrupts
8051 make use of 2 registers to deal with the interrupts.
These registers are used for the all the processing of the interrupts in 8051
1. Interrupt Enable-IE Register (8 bit )
2. Interrupt Priority-IP Register (8 bit)
8 bits of these two registers are define some functions
IE register is used for enabling or disabling the interrupt (Mask or non mask)
IE register
• The main function of this SFR is to enable or disable different
interrupts by setting or clearing its designated bits.
• IE is a bit addressable SFR with individual bit addresses and bit
designations
1-enable
0-disable
EA –(Global interrupt control bit) MSB used to disable/enable all
interrupt
EA=0 all interrupts disabled/No interrupt will be acknowledged
EA=1 Interrupt enabled as per the condition of the individual enable
bits
ES –For enable serial interrupt
ET1-Interrupting timer 1
EX1-Interrupting INT1
ET0-Interrupting timer 0
EX0-Interrupting INT0
IP register
IP is also bit addressable SFR,which helps the programmer to resolve the
priority issues of multiple interrupts.

Bit 0 –Corresponding interrupt has lower priority

Bit 1-Corresponding interrupt has higher priority