DEVELOPMENT OF ROBUST

CONFIGURABLE LOGIC BLOCK

FOR FAULT-TOLERANT FPGA
SYSTEMS
AN INTERNSHIP REPORT
Submitted in partial fulfillment of the requirements
for the award of

BACHELOROFTECHNOLOGY
IN
ELECTRONICS & COMMUNICATION ENGINEERING
BY
DANDA SAI VYSNAVI
(21761A0411)

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

LAKIREDDY BALI REDDY COLLEGE OF ENGINEERING
(AUTONOMOUS)
L. B. Reddy Nagar, Mylavaram –521230.
Affiliated to JNTUK, Kakinada & Approved by AICTE, New Delhi
Accredited by NBA and NAAC
Certified by ISO 21001-2018
2024-2025
 LAKIREDDYBALI REDDY COLLEGE OFENGINEERING
(AUTONOMOUS)
L.B.ReddyNagar,Mylavaram–521230.
Affiliated to JNTUK, Kakinada& Approved by AICTE, New Delhi
Accredited by NBA and NAAC, Certified by ISO 21001-2018
DEPARTMENT OF ELECTRONICS & COMMUNICATIONENGINEERING

CERTIFICATE

This is to certify that Internship report entitled “DEVELOPMENT OF ROBUST

CONFIGURABLE LOGIC BLOCK FOR FAULT-TOLERANT FPGA
SYSTEMS” is a Bonafide work done in National Institute of Technology (NITR),
Rourkela and submitted by DANDA SAI VYSHNAVI (21761A0411) in partial
fulfillment of requirement for the award of Bachelor of Technology in Electronics and
Communication Engineering in Lakireddy Bali Reddy College of Engineering (A),
Mylavaram, during the academic year 2024-2025.

Internship Coordinator Head of the Department

 ACKNOWLEDGEMENT

The Satisfaction that accompanies that the successful completion of any task
would be in complete without the mention of people whose ceaseless co-operation
made it possible, whose constant guidance and encouragement crown all efforts with
success.
I humbly express our thanks to our Principal Dr. K. Appa Rao for extending
his support and for providing us with an environment to complete our Internship
successfully.
I would also like to thank our Vice Principal, Dr. B. Ramesh Reddy for
encouraging us which certainly helped to complete the internship in time.
I deeply in debted to our Head of Department Dr. G. Srinivasulu, who
modeled us both technically and morally for achieving greater success in life.
I would like to express our heart full thanks to our parents for their unflinching
support and constant encouragement throughout the period of our Internship work for
making it a successful one.
I would like to thank all the teaching and non-teaching staff members of
Electronics and Communication Engineering, who have extended their full co-
operation during the course of our Internship.
I thank all our friends who helped us sharing knowledge and by providing
material to complete the Internship in time.

DANDASAIVYSHNAVI
(21761A0411)
 TABLE OF CONTENTS

SI. No Chapter Name Page No

1. INTRODUCTION 1-3
Introduction to VLSI and SoC Design 1
Evolution and Importance of VLSI 1
Overview of System on Chip (SoC) 2
Role of SoC in Modern Technology 2
Objective of the Internship 3
2. INTERNSHIP ORGANIZATION OVERVIEW 4
3. INTERNSHIP WORK AND LEARNING 5-8
–Introduction to Fault-Tolerant FPGA Design 5
–Configurable Logic Block (CLB) Design 7
–Fault Injection and Simulation 8
–Dynamic Redundancy Mechanism 8
4. TOOLS & TECHNOLOGIES 9-10
5. PROJECTS/ ASSIGNMENTS 11
6. CONCLUSION 12
7. REFERENCES 13
 LIST OF FIGURES

Fig no. Fig name Page no

VLSI Technology 1
Block Diagram for Dynamic Reconfiguration 6
CLB 7
Faulty FPGA 10
 CHAPTER - 1
INTRODUCTION

Introduction to VLSI and SoC Design

Intoday’s world of rapidly evolvingtechnology,thedemandformoreefficient,
compact, and faster electronic devices continues to grow. At the heart of these
innovationslieadvancementsinsemiconductortechnologies,specificallyVery-Large-
Scale Integration (VLSI) and System on Chip (SoC) design. Thesetwofields have
been instrumental in revolutionizing the electronics industry, enabling the creation of
powerful, multifunctional devices that we use daily, such as smartphones, tablets, and
embedded systems in automobiles.

Evolution and Importance of VLSI

The evolution of electronics has undergone significant transformations sincethe

early days of large, discrete component-based systems. Initially, electronic circuits
were built using individual transistors, resistors, and capacitors,which limitedthesize,
efficiency, and performance of the systems. However, with the development of
integrated circuits (ICs) in the 1960s, engineers could combine several components on
a single silicon chip, leading to the rise of Small-Scale Integration (SSI), Medium-
Scale Integration (MSI), and Large-Scale Integration (LSI).

Fig-1.1 VLSI Technology.

VLSI represents the next step in this evolution. It refers to the process of
integrating millions (or even billions) of transistors onto a single chip. This level of
integration has led to exponential improvements in processing power, memory
capacity,andoverallsystemperformance,allwhilereducingthephysicalfootprint

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 and energy consumption of the devices. With VLSI, entire systems, such as
microprocessorsandmemoryunits,canbeplacedonasinglesiliconsubstrate,enabling the
design of modern computing and communication systems.
The importance of VLSI in today’s world cannot be overstated. As technology
pushes towards smaller, faster, and more energy-efficient devices, VLSI continues to
beakeyenablerfortheseadvancements.Fromconsumerelectronicstomedicaldevices and
aerospace applications, the ability to design, simulate, and manufacture complex
integratedcircuitsisessentialtomeetingmoderndemandsforhigh-performance,low-
power electronic systems.

Overview of System on Chip (SoC)

While VLSI focuses on integrating transistors and other components onto a

chip, SoC (System on Chip) design takes integration to a higher level by combining
an entire system onto a single chip. An SoC typically includes a central processingunit
(CPU), memory blocks (RAM, ROM), input/output ports, and secondary storage, all
interconnected and working together on one integrated circuit. SoCs are critical in
reducing the size and cost of electronic systems, particularly in devices like
smartphones, IoT devices, and embedded systems.
The concept of SoC design arises from the need to improve efficiency, cost-
effectiveness,andperformanceinmodernelectronics.Traditionally,electronicsystems
were composed of multiple ICs that performed different functions, which led to
increased power consumption, larger circuit boards, and slower processing times due
tothephysicalseparationofcomponents.SoCaddressesthesechallengesbyintegrating all
system components onto one chip, allowing for faster data transfer, lower power
consumption, and greater compactness.

Role of SoC in Modern Technology

SoC technology is becoming increasingly vital due to the growing complexity

of modern systems. In many applications, especially in IoT (Internet of Things)
devices and smartphones, space and power are at a premium. SoCs provide a solution
bycombiningmultiplecomponentsintoasingle,energy-efficientchip.Thisintegration
reduces not only the size and weight of devices but also their power consumption,
making SoCs ideal for battery-powered devices.

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 An example of SoC's impact can be seen in mobile phones. Modern
smartphones contain multiple processing cores, memory, sensors, and connectivity
components,allpackedintoacompactSoC.Thisenablesthephonetoperformawide
rangeoftasks,fromcommunicationtomultimediaprocessing,whilemaintaininghigh
performance and battery efficiency.

Objective of the Internship

The primary objective of this internship at NIT Rourkela was to provide

practical experience in designing fault-tolerant digital systems within FPGA
architectures. This project-based training focused on developing and testing a
Configurable Logic Block(CLB)capableoffaultdetectionanddynamicredundancy.
Participantswereintroducedtothefulldigitaldesignflow,fromspecificationandRTL
design to simulation, fault injection, and FPGA-based implementation.
A core focus was on hands-on experience with Electronic Design
Automation (EDA) tools, particularly Xilinx Vivado and Icarus Verilog, allowing
participants to simulate, debug, and validate their fault-tolerant designs in a controlled
environment. The internship aimed to bridge the gap between theoretical knowledge
in VLSI and practical skills in fault-tolerant digital design, preparing students for
future careers in the semiconductor and embedded systems industries.
Bytheendoftheinternship,participantswereexpectedtohaveasolidgraspof FPGA-
based fault-tolerant design principles, proficiency in EDA tools, and an understanding
of the challenges involved in resilient system design. This experience provided a
comprehensive foundation in fault tolerance and FPGA architectures, equipping
participants with the skills and insights needed to address the complexities of reliable
digital systems in critical applications.

3
 CHAPTER-2
INTERNSHIP ORGANIZATION OVERVIEW

The National Institute of Technology (NIT) Rourkela is a premier public

engineering institution in India, recognized for its contributions to research and
developmentinengineering,technology,andappliedsciences.AsoneofIndia’sleading
institutions, NIT Rourkela emphasizes bridging theoretical learning with real-world
applications, particularly in areas such as VLSI design, embedded systems, and fault-
tolerantFPGAsystems.TheDepartmentofElectronicsandCommunicationEngineering at
NIT Rourkela offers state-of-the-art facilities and advanced research opportunities,
making it an ideal environment for training in digital design and semiconductor
technologies.

NIT Rourkela is equipped with a range of industry-standard tools for digital

design, including Xilinx Vivado for FPGA design and simulation, Icarus Verilog for
Verilog simulation, and FPGA hardware platforms like the Basys3 and PYNQZ2
boards. These resources provide students with practical experience in the complete
VLSI design flow, from RTL coding to FPGA deployment, preparing them for careers
in the semiconductor and electronics industries.

One of the key initiatives at NIT Rourkela is the focus on fault-tolerant system
design, a critical field for applications where reliability is essential, such as aerospace,
automotive, and medical electronics. The fault-tolerant FPGA design project aimed to
address the growing need for resilient digital systems capable of maintaining
functionalityinthepresenceoffaults.

My internship project at NIT Rourkela provided me with in-depth knowledge

and hands-on experience in designing fault-tolerant Configurable Logic Blocks
(CLBs). This opportunity strengthened my understanding of FPGA architecture,
redundancy techniques, and fault-injection testing, significantly enhancing my readiness
for future roles in digital circuit design and the semiconductor industry.

Address & Contact-Details of Organization: NIT Rourkela, Prof. Md. Equeenuddin

(PIC, Summer Internship Programme -2024) Email id: [email protected], Ph: 0661 - 246 2939

Duration of the Internship: 15-05-2024 to 16-07-2024.

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 CHAPTER - 3
INTERNSHIP WORK AND LEARNING
The project at the National Institute of Technology(NIT) Rourkela was
centered on designing and implementing a robust, fault-tolerant Configurable Logic
Block (CLB) within Field-Programmable Gate Arrays (FPGAs). This effort was
aimed at ensuring enhanced reliability and continuous operation in environments
where failure can have critical consequences, such as in aerospace, medical, and
automotive applications. The project included both theoretical understanding and
practical hands- on tasks, incorporating the latest practices in fault tolerance and
redundancy within digital circuits. Below is a comprehensive outline of the project’s
focus areas and learning outcomes:
Introduction to Fault-Tolerant FPGA Design
• FPGA design is a complex process that involves configuring reprogrammable
logicresourcestoperformawidevarietyoffunctions.Thisprojectspecifically
focused on developing Configurable Logic Blocks (CLBs) with fault-tolerant
capabilities to maintain system integrity even in the presence of component
failures.

• Concept of Fault Tolerance in CLBs: Traditional FPGAs often lack built-in

faulttolerance mechanisms, making them vulnerable to faults in critical
applications. The project aimed to overcome these limitations by adding fault-
tolerant features that can dynamically detect and correct faults within the CLB
without interrupting operation.

• Dynamic Redundancy Approach: In contrast to static methods like Triple

Modular Redundancy (TMR), dynamic redundancy leverages a spare
component that activates only when faults are detected, saving power and
resources while increasing resilience.

• Steps Involved in Fault-Tolerant FPGA Design

The structured design process in this project covered multiple stages from
concept to implementation, similar to industry-standard VLSI design flow but
adapted to focus on fault tolerance:

Specification: This initial phase defined the system’s requirements, including reliability,
fault-handling capacity, latency, power efficiency, and overall functional goals. Specific
metricsforfaulttolerance,suchassingle-pointfailuredetectionanddynamicrerouting
5
capacity,were established.

• Design Entry (RTL Design): The design of the CLB was captured at the
Register Transfer Level (RTL) using Verilog. Here, five independent 3-input
Lookup Tables (LUTs) were modeled, with the fifth LUT serving as a spare.
The RTL design allowed precise control over data flow between registers and
easy modification of control logic for fault tolerance.

• FaultDetectionandRerouting:Acriticalpartofthedesignwasintegratinga fault-
detection mechanism within the CLB. Comparators monitored LUT outputs
continuously, raising a fault flag if discrepancies were detected. Upon
detecting a fault, input signals would automatically reroute to the spare LUT,
ensuring uninterrupted functionality.

• Verification and Validation: Rigorous verification was conducted to confirm

that the fault detection and rerouting mechanisms functioned as intended.
Simulations were performed under various scenarios to ensure robustness and
compliance with defined reliability metrics.

Fig:3.1 Block Diagram for dynamic reconfiguration

6
Configurable Logic Block (CLB) Design

The project’s core was the development of a Configurable Logic Block (CLB)
containing five Lookup Tables (LUTs) capable of dynamic redundancy.
 LookupTable(LUT)Architecture:Each3-inputLUTwasdesignedtoimplementspecific logic
functions based on input signals, such as AND, OR, and XOR. These LUTs used SRAM
cells for storing truth tables, enabling quick access and updating of logic functions.
 Spare LUT Integration: A fifth LUT was designed to serve as a spare, ready to take over
ifanyoftheprimaryLUTsfailed. ThisspareLUTwas seamlesslyintegratedintotheCLB, and
control logic was established to reroute signals from faulty LUTs to the spare, thus
maintaining continuous operation.
 SRAM and Mux-Based Design: Each LUT included an 8:1 multiplexer (MUX) that
selected the appropriate logic output based on input combinations. This configuration
allowed efficient use of the FPGA’s physical resources and provided flexibility for
implementing a wide range of combinational logic functions.


Fig:3.2 CLB

7
Fault Injection and Simulation

To validate the fault-tolerant design, the project included systematic fault

injection and simulation.
 Fault Injection Using Vivado: Vivado was used to inject various types of faults, such as
stuck-atfaultsanddelayfaults,intoindividualLUTswithintheCLB.Thiscontrolledtesting
method enabled the team to evaluate the system’s response to faults under real-world
conditions.
 Fault Scenarios and System Response: Multiple fault scenarios were simulated, including
single and multiple stuck-at faults across different SRAM cells in the LUTs. These
simulations helped assess how quickly and effectively the CLB could detect faults, reroute
signals, and continue operation without any disruption.
 Validation of Redundancy Mechanisms: The fault injection process validated the dynamic
redundancy feature, confirming that the spare LUT could successfully handle the load of a
faulty LUT. This testing demonstrated the robustness of the fault tolerance approach and
helped fine-tune the CLB’s reliability.
Dynamic Redundancy Mechanism:
Dynamic redundancy was a key innovation of the project, allowing the CLB to adapt
to faults without impacting overall performance or efficiency.
 Spare LUT Activation Process:
The design featured a fault-detection unit that continuously monitored the primary
LUTs.Whenafaultwasdetected,thesystemautomaticallydisabledthefaultyLUT
andactivatedthespare,redirectinginputsignalsseamlesslytoensurenodisruption.
 Comparator-BasedFault Detection:
The use of comparators enabled immediate fault detection by checking for
discrepancies between expected and actual outputs. Upon detecting a fault, the
system raised a fault flag, triggering the rerouting of signals.
 Energy and Resource Efficiency:
Unlikestaticredundancyapproaches,dynamicredundancyactivatedonlythe
necessaryresourcesuponfaultdetection,savingpowerandimprovingtheFPGA’s
overall efficiency. This approach made the CLB suitable for applications where
both reliability and energy efficiency are critical.
 Hardware Validation and Testing:
Tofurthervalidatethedesign’srobustness,hardwaretestswereconductedafterthe
simulation phase

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 CHAPTER-4
TOOLS &
TECHNOLOGIES

A key component of the project at NIT Rourkela was gaining hands-on

experience with Electronic Design Automation (EDA) tools, which are essential for
designing,simulating,andimplementingresilientdigitalcircuitsinfault-tolerantFPGA and
VLSI design. Each tool provided specific functionalities that bridged theoretical
knowledge with practical applications. Below is a detailed overview of the tools and
their roles in the project:
 Role in the Project: Vivado served as theprimary tool forthedesignandsimulation ofthe
fault-tolerant Configurable Logic Block (CLB). Using Vivado, RTL designs of the CLB
were synthesized, and essential dynamic redundancy features were implemented to handle
faults efficiently.
 Simulation and Fault Injection:Vivado’ssimulationenvironmentenabledcontrolledfault
injections, such as introducing stuck-at faults in specificLUTs, to evaluate theresilienceof
the CLB design. The tool’s debugging capabilities helped verify the effectiveness of the
fault-detection and rerouting mechanisms, particularly in redirecting functionality to the
spare LUT upon fault detection.
 FPGADeployment:Followingsuccessfulsimulation,Vivadofacilitatedthedeploymentof the
fault-tolerant CLB design onto an FPGA board for real-time validation, providing
insightsintotheCLB’sresponseunderactualhardwareconditions.Thisdeploymentallowed for
testing of operational reliability, with a focus on ensuring fault-tolerance mechanisms
functioned as intended.
 PYNQZ2 FPGA Board:ThePYNQZ2board,basedonXilinxZynq,wasusedforfurther testing
and allowed interactive programming.
o Role in the Project:ThePYNQZ2board’sprogrammablelogicenabledintegration
with Jupyter Notebook, which facilitated interactive debugging of the CLB design
and real-time monitoring of the fault-tolerance mechanisms.
o Educational Value: The PYNQ Z2 board provided a hands-on approach to
experimenting with hardware integration, particularly using Python-based
interaction. This feature allowed testing of fault scenarios and the observation of
rerouting in real time, solidifying knowledge of programmable logic and fault-
tolerant design principles.

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Fig:4.1 Faulty FPGA

10
 CHAPTER - 5
PROJECTS/ASSIGNMENTS
Fault-Tolerant Configurable Logic Block (CLB) Design
 Objective: To design a fault-tolerant Configurable Logic Block (CLB) comprising five 3-
inputLookupTables(LUTs),includingaspareLUTtohandlepotentialfaultsinanyprimary LUT.
 Design and Simulation:UsingVerilog,theCLBwasmodeledwithabuilt-infault-detection
mechanism. Simulation was conducted in Vivado, focusing on validating fault tolerance by
monitoring outputs and triggering rerouting to the spare LUT upon fault detection. This
assignment provided insights into fault-tolerant design and the importance of dynamic
redundancy in critical applications.
3-Input LUT(Look up Table) Circuit Design
 Objective:Todevelopa3-inputLUTcircuitforeachprimaryCLBandspareLUT,allowing
flexible logic configuration based on inputs.
 Simulation and Testing: Each LUT was modeled using Verilog and tested for multiple
input combinations to ensure accurate logic representation. SRAM cells were used for
storing truth tables, and the design incorporated an 8:1 multiplexer for output selection.
Vivado simulations validated the fault-free operation, and fault injection simulations
evaluated the system's resilience under fault conditions.
Comparator Circuit for Fault Detection
 Objective: To design a comparator circuit that continuously monitors the outputs of the
primary LUTs, identifying discrepancies to flag faults and initiate input rerouting.
 Implementation: The comparator was integrated within the CLB to enable real-time fault
detection. When a fault was detected, the circuit generated a fault flag to trigger dynamic
reroutingtothespareLUT,ensuringcontinuousoperationwithoutperformancedegradation.
Fault Injection Scenarios Using Vivado
 Objective: To systematically inject faults into individual LUTs within the CLB, such as
stuck-at faults and delay faults, and observe the system’s response.
 Testing Methodology: Faults were injected at specific nodes, and the behavior of the
comparator and spare LUT activation was observed. This testing process validated the
dynamic redundancy feature, highlighting the CLB’s ability to reroute inputs seamlessly to
the spare LUT, thereby maintaining functionality under various fault conditions.

11
 CHAPTER-6
CONCLUSION

The project experience at NIT Rourkela significantly deepened my practical

knowledge of fault-tolerant digital circuit design, particularly within FPGA systems,
bridging the theoretical foundations gained in academics with hands-on, real-world
applications. The assignments on circuit design, fault injection, simulation, and
validationofferedcomprehensiveexposuretothecomplexitiesanddemandsofmodern
VLSI (Very Large Scale Integration) and fault-tolerant SoC (System on Chip) design.
Working extensively with EDA tools like Vivado for simulation, Verilog for
RTLcoding,andSRAMandMUXconfigurationswithintheCLBprovidedathorough
understanding of the design flow—from initial specification and coding to validation
through fault injection. These tools allowed me to explore essential components like
ConfigurableLogicBlocks(CLBs),LookupTables(LUTs),andredundancycircuitsin
depth, reinforcing theoretical concepts within a practical framework. This experience
not only strengthened technical proficiency but also cultivated critical thinking and
advanced problem-solving abilities, both vital in digital circuit and embedded system
design.
The knowledge and skills acquired during this project are foundational for a
career in VLSI and FPGA-based system design, especially in critical fields such as
aerospace, automotive, and medical electronics where fault tolerance is indispensable.
Understanding dynamic redundancy methods and fault-handling techniques has
prepared me to address challenges in resilient design, enabling reliable operation even
under fault conditions. This experience has equipped me with the tools to tackle the
complexitiesofthesemiconductorindustry,andIamconfidentthattheinsightsgained will
facilitate innovative contributions to advancing fault-tolerant and resilient digital
systems.

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 REFERENCES

1. https://www.sciencedirect.com/science/article/abs/pii/S0026271414005332

2. https://ieeexplore.ieee.org/abstract/document/6526560

3. https://www.amd.com/en/products/adaptive-socs-and-fpgas/soc/zynq-ultrascale-plus-mpsoc.html

4. https://www.arrow.com/en/research-and-events/articles/fpga-basics-architecture-applications-and-uses

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