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Real World FPGA Design with Verilog
Ken Coffman
President, Bytech Services
Prentice Hall PTR
Upper Saddle River, NJ 07458
www.phptr.com
Contents
Forword
Notes on the Current State of the Art IX
Preface
Digital Design in the Real World XI
Acknowledgments xv
Chapter 1 Verilog Design in the Real World
Trivial Overheat Detector Example 3
Synthesizable Verilog Elements 8
Verilog Hierarchy 12
Built-in Logic Primitives 14
Latches and Flipflops 18
Blocking and Nonblocking Assignments 25
Miscellaneous Verilog Syntax Items 29
Chapter 2 Digital Design Strategies and Techniques 41
Design Processing Steps 42
Analog Building Blocks for Digital Primitives 42
Using a LUT to Implement Logic Functions 44
Discussion of Design Processing Steps 48
Synchronous Logic Rules 57
Clocking Strategies 65
Logic Minimization 68
What Does the Synthesizer Do? 72
Area/Delay Optimization 75
vi Contents
Chapter 3 A Digital Circuit Toolbox 77
Verilog Hierarchy Revisited 77
Tristate Signals and Busses 78
Bidirectional Busses 83
Priority Encoders 84
Area/Speed Optimization in Synthesis 88
Trade-off Between Operating Speed and Latency 92
Delays in FPGA Logic Elements 94
State Machines 97
Adders 105
Subtractors 114
Multipliers 116
Chapter 4 More Digital Circuits: Counters, RAMs, and FIFOs 121
Ripple Counters 121
Johnson Counters 122
Linear Feedback Shift Registers 124
Cyclic Redundancy Checksums 133
ROM 135
RAM 136
FIFO Notes 151
Chapter 5 Verilog Test Fixtures 153
Compiler Directives 154
Automated Testing 167
Chapter 6 Real World Design: Tools, Techniques, and Trade-offs 173
Compiling with LeonardoSpectrum 175
Complete Design Flow, 8-Bit Equality Comparator 185
8-Bit Equality Comparator with Hierarchy 191
Optimization Options In the Xilinx Environment 200
Mapping Options 201
Logic Level Timing Report/Post Layout Timing Report 205
VHDL/Verilog Simulation Options 208
Other Design Manager Tools 211
Contents vii
Chapter 7 A Look at Competing Architectures 219
Factors that Determine Integrated Circuit Pricing 220
FPGA Device Design 220
FPGA Technology Selection Checklist 222
Xilinx FPGA Architectures 224
Altera CPLD Architectures 231
Chapter 8 Libraries, Reusable Modules, and IP 235
Keys to Increased Productivity 236
Library Elements 238
Structural Coding Style 243
A Small Diversion to Compare a Schematic to a Verilog Design 244
Using LogiBLOX Module Generator 247
Design Reuse, Reusing Your Own Code 252
Buying IP Designs 254
Summing Up 255
Chapter 9 Designing for ASIC Conversion 257
Hardwire Devices 258
Semicustom Devices 259
Design Rules for ASIC Conversion 261
Synchronous Design Rules 262
Oscillators 264
Delay Lines 265
The Language of Test 267
Print-on-Change Test Vectors 269
Afterword—A Look into the Future 271
Resources 273
Glossary and Acronyms 275
Bibliography 285
Contents
VIII
Index 287
The Author 291
