BECE102L

DIGITAL SYSTEM DESIGN

Module-7
Programmable Logic Devices
Module-7 (Programmable Logic Devices)
Types of Programmable Logic Devices: PLA, PAL, CPLD, FPGA
Generic Architecture.

(4 hours)

2
Content
• Types of Programmable Logic Devices:
• PLA,
• PAL,
• CPLD,
• FPGA Generic Architecture.

3
PLDs Introduction
• Any Boolean function or combinational circuit can be represented by minterms
and maxterms.
• The Decoders and Multiplexers can be used to implement Boolean functions in
terms of minterms/ maxterms. (Can be a general purpose device)
• This fact leads to the development of IC packages with larger integration that
contain decoders with a number of OR gates or one single chip containing a
large number of basic gates—AND, OR, and NOT.
• These ICs can be programmed according to desired functions by the
manufacturers or the designers.
• PLDs serve as the general circuits for realization of a set of Boolean
functions.

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PLDs Introduction
• The general structure of programmable logic devices is illustrated in Figure.
• The inputs to the PLD are applied to a set of buffers/inverters.
• Buffers/inverters provide the true values of the inputs as well as the
complemented values of the inputs.

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PLDs Introduction
• In addition, the PLDs are made up of AND array and OR array.
• The AND array produces “p” product terms from “n” of input variables and their
complements.
• These product terms are fed to the OR array, which follows next.
• The OR array consists of several numbers of OR gates and realizes a set of “m”
of outputs at sum of the products form.
• One or both of the OR, AND arrays of PLDs are programmable.
• The logic designer can select the connections within the array as per requirement.
• It is assumed that the open inputs of an AND gate array are connected to logic 1
and open inputs of an OR gate are connected to logic 0.

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PLDs Introduction
• In a programmable array, the connections of gates can be selected
(programmable).
• The simple approach for fabricating the programmable gate is to employ fuse
links at each of the inputs of the gate.
• Some of the fuses are programmed to blow out to achieve the desired output from
the gate.
• As an example, if the desired output of the gate is BC, then fuses at A and D are
to be blown out as shown in Figure.

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PLDs Introduction
• The general and simplified structure of PLDs are illustrated in Figure.

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PLDs Advantages
The advantages of using programmable logic devices are:
1. Reduced space requirements.
2. Reduced power requirements.
3. Design security.
4. Compact circuitry.
5. Short design cycle.
6. Low development cost.
7. Higher switching speed.
8. Low production cost for large-quantity production.

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PLDs-Types
Programmable logic devices are broadly classified as
• Read Only Memory or ROM
• Programmable Logic Array or PLA, and
• Programmable Array Logic or PAL.

S. No. Device AND Array OR Array

1 ROM Fixed Programmable
2 PLA Programmable Programmable
3 PAL Programmable Fixed

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Programmable Logic Array or PLA
• PLA implements the Boolean
function in terms of SOP.
• All minterms are not generated and
required terms alone is produced.
• Both AND array and OR arrays are
programmable.
• Output is taken from Ex-OR gates.
• Size: No. of Inputs X No. of AND
Gates (product terms) X No. of
Outputs
• Example: 3*4*2

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Programmable Logic Array or PLA
Consider the following Boolean functions and implement using 3X4X2 PLA Array.
𝐹1 = 𝐴𝐵′ + 𝐴𝐶 + 𝐴′ 𝐵𝐶 ′ (1)
𝐹2 = (𝐴𝐶 + 𝐵𝐶)′ (2)
• In above functions, the terms are 𝐴𝐵′ , 𝐴𝐶, 𝐵𝐶, 𝑎𝑛𝑑 𝐴′ 𝐵𝐶′.
• The X mark indicates intact fuse (logical connection).
• The output of an OR gate gives the logical sum of the selected product terms.
• The output may be complemented or left in its true form, depending on the logic
being realized.

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Programmable Logic Array or PLA
• The Fuse map/ Programming table gives complete information
about the programming of a PLA.
• 1 A variable appears directly, 0 A variable appears complemented
• __  Absence of variable in the product.
Outputs
Inputs
S. No. Product Term (T) (C)
A B C 𝐹1 𝐹2
1 𝑨𝑩′ 1 1 0 __ 1 __
2 𝑨𝑪 2 1 __ 1 1 1
3 𝑩𝑪 3 __ 1 1 __ 1
4 𝑨′ 𝑩𝑪′ 4 0 1 0 1 __
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Programmable Logic Array or PLA
The fuse map/ Programming map contains three regions.
• 1st region deals with the product terms numerically.
• 2nd regions have the information about the required paths between the
inputs and AND gates.
• 3rd region gives information about the paths between the AND and
OR gates.
• 3rd region also have the information about the true form/
complement form of output.

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Programmable Logic Array or PLA
Consider the following Boolean functions

𝐹1 𝐴, 𝐵, 𝐶 = Σ(0, 1, 3, 4) (1)

𝐹2 𝐴, 𝐵, 𝐶 = Σ(1, 2, 3, 4, 5) (2) and

implement them using 3*4* 2 PLA.

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Programmable Logic Array or PLA
• The K-maps and the simplified Boolean expression are
BC 0 0 01 11 10
A
0 1 1 1
𝐹1 = 𝐵′ 𝐶 ′ + 𝐴′ 𝐶
1 1

BC 0 0 01 11 10
A
0 1 1 1
𝐹2 = 𝐴′ 𝐵 + 𝐴′ 𝐶 + 𝐴𝐵′
1 1 1

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Programmable Logic Array or PLA
• In these expressions, there are
four distinct product terms —
B′C′, A′C, A′B, and AB′.
• So these functions can be
realized by the specified 3 × 4 ×
2 PLA.

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Programmable Logic Array or PLA
• The program table or fuse table is
Outputs
Inputs
S. No. Product Terms (T) (T)
A B C 𝐹1 𝐹2
1 𝑨′𝑩 1 0 1 __ __ 1
2 𝑨′𝑪 2 0 __ 1 1 1
3 𝑨𝑩′ 3 1 0 __ __ 1
4 𝑩′𝑪′ 4 __ 0 0 1 __

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Programmable Logic Array or PLA
Implement the following Boolean functions using a 3 x 4 x 2 PLA.
𝐹1 𝐴, 𝐵, 𝐶 = (3, 5, 6, 7) and
𝐹2 𝐴, 𝐵, 𝐶 = (0,2,4,7).

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Programmable Logic Array or PLA
• The K-maps and the simplified Boolean expression are
BC 0 0 01 11 10
A
0 1
𝐹1 = 𝐴𝐵 + 𝐵𝐶 + 𝐴𝐶
1 1 1 1

BC 0 0 01 11 10
A
0 1 1
𝐹2 = 𝐵′ 𝐶 ′ + 𝐴′ 𝐶 ′ + 𝐴𝐵𝐶
1 1 1

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Programmable Logic Array or PLA
• The K-maps and the simplified Boolean expression are
BC 0 0 01 11 10
A
0 0 0 1 0
𝐹1′ = 𝐴′ 𝐵′ + 𝐴′ 𝐶 ′ + 𝐵′ 𝐶′
1 0 1 1 1

BC 0 0 01 11 10
A
0 1 0 0 1
𝐹2′ = 𝐵′ 𝐶 + 𝐴′ 𝐶 + 𝐴𝐵𝐶′
1 1 0 1 0

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Programmable Logic Array or PLA
• The simplified Boolean expression are
𝐹1 = 𝐴𝐵 + 𝐵𝐶 + 𝐴𝐶
𝐹1′ = 𝐴′ 𝐵′ + 𝐴′ 𝐶 ′ + 𝐵′ 𝐶′ → 𝐹1 = (𝐴′ 𝐵′ + 𝐴′ 𝐶 ′ + 𝐵′ 𝐶′)′
𝐹2 = 𝐵′ 𝐶 ′ + 𝐴′ 𝐶 ′ + 𝐴𝐵𝐶
𝐹2′ = 𝐵′ 𝐶 + 𝐴′ 𝐶 + 𝐴𝐵𝐶 ′ → 𝐹2 = (𝐵′ 𝐶 + 𝐴′ 𝐶 + 𝐴𝐵𝐶 ′ )′
• If we use 𝑭𝟏 and 𝑭𝟐 it requires 4 different product terms. (Available AND gates
are only 4!).
• So we can use 𝐹1 ′ and 𝐹2 .
𝐹1′′ = 𝐹1 = (𝐴′ 𝐵′ + 𝐴′ 𝐶 ′ + 𝐵′ 𝐶′)′
𝐹2 = 𝐵′ 𝐶′ + 𝐴′ 𝐶 ′ + 𝐴𝐵𝐶
• Now the required products are 𝑨′ 𝑩′ , 𝑨′ 𝑪′ , 𝑩′ 𝑪′ and 𝑨𝑩𝑪 (only 4!).

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Programmable Logic Array or PLA
• Now the required products are 𝑨′ 𝑩′ , 𝑨′ 𝑪′ , 𝑩′ 𝑪′ and 𝑨𝑩𝑪 (only 4!).
• The PLA diagram is

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Programmable Logic Array or PLA
• The program table or fuse table is
Outputs
Inputs
S. No. Product Terms (C) (T)
A B C 𝐹1 𝐹2
1 𝑨′𝑩′ 1 0 0 __ 1 __
2 𝑨′𝑪′ 2 0 __ 0 1 1
3 𝑩′ 𝑪 3 __ 0 1 1 1
4 𝑨𝑩𝑪 4 1 1 1 __ 1

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Programmable Logic Array or PLA
Implement the following two Boolean functions with a PLA.
𝐹1 𝐴, 𝐵, 𝐶 = (0,1,2,4) and
𝐹2 𝐴, 𝐵, 𝐶 = (0,5,6,7).

Answer:
𝐹1 = (𝐴𝐵 + 𝐴𝐶 + 𝐵𝐶)′
𝐹2 = 𝐴𝐵 + 𝐴𝐶 + 𝐴′ 𝐵′ 𝐶′

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Programmable Array Logic or PAL
• The general structure of this device is similar to PLA, but in a PAL device only
AND gates are programmable.
• The OR array in this device is fixed by the manufacturer.
• This makes PAL devices easier to program and less expensive than PLA.
• On the other hand, since the OR array is fixed, it is less flexible than a PLA
device.
• Size: No. of Inputs X No. of Product terms (AND gates) X No. of Outputs.
• Example: 4 x 8 x 3.

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Programmable Array Logic or PAL
• Figure gives the general structure of a PAL device.

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Programmable Array Logic or PAL

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Programmable Array Logic or PAL

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Programmable Array Logic or PAL
• Figure gives the general structure of a PAL device.
• It has n input lines which are fed to buffers/inverters.
• Buffers/inverters are connected to inputs of AND gates through programmable
links.
• Outputs of AND gates are then fed to the OR array with fixed connections.
• It should be noted that, all the outputs of an AND array are not connected to an
OR array.
• In contrast to that, only some of the AND outputs are connected to an OR
array which is at the manufacturer's discretion.
• In designing with a PAL, the Boolean functions must be simplified to fit into each
section.
• Unlike the situation with a PLA, a product term cannot be shared among two or
more OR gates.

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Programmable Array Logic or PAL
• Note that while every buffer/inverter is connected to AND gates through links,
F1-related OR gates are connected to only three AND outputs, F2 with three
AND gates, and F3 with two AND gates.
• So this particular device can generate only eight product terms, out of which
two of the three OR gates may have three product terms each and the rest of
the OR gates will have only two product terms.
• Therefore, while designing with PAL, particular attention is to be given to the
fixed OR array.

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Programmable Array Logic or PAL
• Let us consider that the following functions are to be realized using a PAL device.
𝐹1 𝐴, 𝐵, 𝐶 = (1,2,4,5,7)
𝐹2 𝐴, 𝐵, 𝐶 = (0, 1,3,5,7)
• As like PLA, in PAL implementation also we need simplified expressions.

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Programmable Array Logic or PAL
• The Simplified expressions from K-map are
BC 0 0 01 11 10
A
0 1 1
𝐹1 = 𝐴𝐵′ + 𝐴𝐶 + 𝐵′ 𝐶 + 𝐴′ 𝐵𝐶′
1 1 1 1

BC 0 0 01 11 10
A
0 1 1 1
𝐹2 = 𝐶 + 𝐴′ 𝐵′
1 1 1

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Programmable Array Logic or PAL
• With given PAL IC, a problem occurs that the specified PAL device has at
the most three product terms associated with one OR gate, whereas one
of the given functions F1 has four product terms.
• However, realization of the functions are achievable with the specified PAL
device by the following method.
• The simplified expressions can be rewritten as
𝐹3 = 𝐴𝐵′ + 𝐴𝐶
So, 𝐹1 = 𝐹3 + 𝐵′ 𝐶 + 𝐴′ 𝐵𝐶′
𝐹2 = 𝐶 + 𝐴′ 𝐵′
• Now there are three functions each of which contains no more than three
product terms and these can be realizable by the specified PAL.

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Programmable Array Logic or PAL
• The connection diagram of PAL is illustrated in Figure.

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Programmable Array Logic or PAL
• The connection diagram of PAL is illustrated in Figure.
• Here, one sub-function F3 has been generated with two product terms, and
this sub-function is connected to one of the inputs to realize the final function F1.
• To realize F2, only two terms need to be generated.
• Since a three-input OR gate is used, the input must be kept at logic 0, so as not to
affect the F2 output.

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Programmable Array Logic or PAL
• PAL Programming table
Product AND inputs
Outputs
term A B C 𝐹3
1 __ 0 1 __
𝐹1 = 𝐹3 + 𝐵′ 𝐶 + 𝐴′ 𝐵𝐶′
2 0 1 0 __
3 __ __ __ 1
4 __ __ 1 __
5 0 0 __ __ 𝐹2 = 𝐶 + 𝐴′ 𝐵′
6 __ __ __ __
7 1 0 __ __ 𝐹3 = 𝐴𝐵′ + 𝐴𝐶
8 1 __ 1 __

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Programmable Array Logic or PAL
• Consider the following Boolean functions, given in sum‐of‐minterms form:
𝑤 𝐴, 𝐵, 𝐶, 𝐷 = Σ(2,12,13)
𝑥 𝐴, 𝐵, 𝐶, 𝐷 = Σ(7, 8,9,10,11,12,13,14,15)
𝑦 𝐴, 𝐵, 𝐶, 𝐷 = Σ(0,2,3,4,5,6,7,8,10,11,15)
𝑧 𝐴, 𝐵, 𝐶, 𝐷 = Σ 1,2,8,12,13
• Simplified Boolean functions using K-map are
𝑤 = 𝐴𝐵𝐶 ′ + 𝐴′ 𝐵′ 𝐶𝐷′
𝑥 = 𝐴 + 𝐵𝐶𝐷
𝑦 = 𝐴′ 𝐵 + 𝐶𝐷 + 𝐵′ 𝐷′
𝑧 = 𝐴𝐵𝐶 ′ + 𝐴′ 𝐵′ 𝐶𝐷′ + 𝐴𝐶 ′ 𝐷′ + 𝐴′ 𝐵′ 𝐶 ′ 𝐷
= 𝒘 + 𝐴𝐶 ′ 𝐷′ + 𝐴′ 𝐵′ 𝐶 ′ 𝐷

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 Programmable Array Logic or PAL
Product AND inputs
• Note that the function for z term
Outputs
A B C D w
has four product terms.
1 1 1 0 __ __
• The logical sum of two of 2 0 0 1 0 __
𝑤 = 𝐴𝐵𝐶 ′ + 𝐴′ 𝐵′ 𝐶𝐷′
these terms is equal to w. 3 __ __ __ __ __
By using w, it is possible
4 1 __ __ __ __
to reduce the number of 𝑥 = 𝐴 + 𝐵𝐶𝐷
5 __ 1 1 1 __
terms for z from four to
three. 6 __ __ __ __ __
7 0 1 __ __ __
• PAL Programming table,
8 __ __ 1 1 __ 𝑦 = 𝐴′ 𝐵 + 𝐶𝐷 + 𝐵′ 𝐷′

9 __ 0 __ 0 __

10 __ __ __ __ 1
𝑧 = 𝒘 + 𝐴𝐶 ′ 𝐷′ + 𝐴′ 𝐵′ 𝐶 ′ 𝐷
11 1 __ 0 0 __
12 0 0 0 1 __
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 Programmable Array Logic or PAL
• PAL Programming diagram.

Simplified Boolean functions using K-map are

𝑤 = 𝐴𝐵𝐶 ′ + 𝐴′ 𝐵′ 𝐶𝐷′
𝑥 = 𝐴 + 𝐵𝐶𝐷
𝑦 = 𝐴′ 𝐵 + 𝐶𝐷 + 𝐵′ 𝐷′
𝑧 = 𝐴𝐵𝐶 ′ + 𝐴′ 𝐵′ 𝐶𝐷′ + 𝐴𝐶 ′ 𝐷′ + 𝐴′ 𝐵′ 𝐶 ′ 𝐷
= 𝒘 + 𝐴𝐶 ′ 𝐷′ + 𝐴′ 𝐵′ 𝐶 ′ 𝐷

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Programmable Array Logic or PAL
The following is a truth table of a three‐input, four‐output combinational circuit:
Inputs Outputs
S. No.
x y z A B C D
0 0 0 0 0 1 0 0
1 0 0 1 1 1 1 1
2 0 1 0 1 0 1 1
3 0 1 1 0 1 0 1
4 1 0 0 1 1 1 0
5 1 0 1 0 0 0 1
6 1 1 0 1 0 1 0
7 1 1 1 0 1 1 1
Tabulate the PAL programming table for the circuit, and mark the fuse map in a PAL
Diagram.
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Programmable Array Logic or PAL
• The simplified expressions using K-maps are
yz 0 0 01 11 10
x
0 0 1 0 1 𝐴 = 𝑦𝑧 ′ + 𝑥𝑧 ′ + 𝑥 ′ 𝑦 ′ 𝑧

1 1 0 0 1

yz 0 0 01 11 10
x
0 1 1 1 0
𝐵 = 𝑥 ′ 𝑦 ′ + 𝑥𝑦 + 𝑦𝑧
1 0 0 1 1

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Programmable Array Logic or PAL
• The simplified expressions using K-maps are
yz 0 0 01 11 10
x
0 0 1 0 1 𝐶 = 𝑦𝑧 ′ + 𝑥𝑧 ′ + 𝑥 ′ 𝑦 ′ 𝑧 + 𝑥𝑦𝑧

1 1 0 1 1

yz 0 0 01 11 10
x
0 0 1 1 1
𝐷 = 𝑧 + 𝑥′𝑦
1 0 1 1 0

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Programmable Array Logic or PAL
Product AND inputs
Outputs
term x y z A
1 __ 1 0 __
𝐴 = 𝑦𝑧 ′ + 𝑥𝑧 ′ + 𝑥 ′ 𝑦 ′ 𝑧
2 1 __ 0 __
3 0 0 1 __
4 0 0 __ __
𝐵 = 𝑥 ′ 𝑦 ′ + 𝑥𝑦 + 𝑦𝑧
5 1 1 __ __
6 0 1 1 __
7 0 __ -- 1
8 1 1 1 __ 𝐶 = 𝐴 + 𝑥𝑦𝑧
9 0 __ __ __

10 0 __ 1 __
𝐷 = 𝑧 + 𝑥 ′𝑦
11 0 1 __ __
12 __ __ __ __
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Sequential Programmable Devices
• Digital systems are often designed with flip‐flops and gates.
• Since the combinational PLD consists of only gates, it is necessary to include
external flip‐flops when they are used in the design.
• Sequential programmable devices include both gates and flip‐flops.
• There are several types of sequential programmable devices available
commercially, and each device has vendor‐specific variants within each type.
• The internal logic of these devices is too complex.
• Three major types of sequential programmable devices are
• Sequential (or simple) programmable logic device (SPLD)
• Complex programmable logic device (CPLD)
• Field‐programmable gate array (FPGA)

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Sequential (or simple) programmable logic device
(SPLD)
• The sequential PLD is sometimes referred to as a simple PLD to differentiate it
from the complex PLD.
• The SPLD includes flip‐flops, in addition to the AND–OR array, within the
integrated circuit chip.
• The circuit outputs can be taken from the OR gates or from the outputs of the
flip‐flops.
• Additional programmable connections are available to include the flip‐flop
outputs in the product terms formed with the AND array.

46
Complex programmable logic device (CPLD)
• The design of a digital system using PLDs often requires the connection of
several devices to produce the complete specification.
• For this type of application, it is more economical to use a complex
programmable logic device (CPLD), which is a collection of individual PLDs
on a single integrated circuit.
• A programmable interconnection structure allows the PLDs to be connected
to each other in the same way that can be done with individual PLDs.
• The device consists of multiple PLDs interconnected through a programmable
switch matrix.
• The input–output (I/O) blocks provide the connections to the IC pins.
• Each I/O pin is driven by a three‐ state buffer and can be programmed to act as
input or output.

47
Complex programmable logic device (CPLD)

48
Complex programmable logic device (CPLD)
• The switch matrix receives inputs from the I/O block and directs them to the
individual macrocells.
• Similarly, selected outputs from macrocells are sent to the outputs as needed.
• Each PLD typically contains from 8 to 16 macrocells, usually fully connected.
• If a macrocell has unused product terms, they can be used by other nearby
macrocells.
• In some cases the macrocell flip‐flop is programmed to act as a D, JK, or T
flip‐flop.
• Different manufacturers have taken different approaches to the general
architecture of CPLDs.
• Areas in which they differ include the individual PLDs the type of macrocells,
the I/O blocks, and the programmable interconnection structure.
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Field‐programmable gate array (FPGA)
• A field‐programmable gate array (FPGA) is a VLSI circuit that can be
programmed at the user’s location.
• A typical FPGA consists of an
• Array of millions of logic blocks,
• Surrounded by Programmable input and output blocks and
• connected together via programmable interconnections.
• There is a wide variety of internal configurations within this group of devices.
• The performance of each type of device depends on the circuit contained in its
logic blocks and the efficiency of its programmed interconnections.

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Field‐programmable gate array (FPGA)
• A typical FPGA logic block consists of
• Look Up Tables (LUT),
• Multiplexers (MUX),
• Gates, and
• Flip‐flops (FF).
• A lookup table is a truth table stored in an SRAM and provides the
combinational circuit functions for the logic block.
• The functions are realized using the lookup table, in the same way that
combinational circuit functions are implemented with ROM/ Decoders.
• For example, a 16 * 2 SRAM can store the truth table of a combinational circuit
that has four inputs and two outputs.
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Field‐programmable gate array (FPGA)
• The combinational logic section, along with a number of programmable
multiplexers, is used to configure the input equations for the flip‐flop and the
output of the logic block.
• The advantage of using RAM instead of ROM to store the truth table is that the
table can be programmed by writing into memory. The disadvantage is that the
memory is volatile.
• The program remains in SRAM until the FPGA is reprogrammed or the power is
turned off.
• The device must be reprogrammed every time power is turned on.

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Field‐programmable gate array (FPGA)
• The design with PLD, CPLD, or FPGA requires extensive computer‐aided
design (CAD) tools to facilitate the synthesis procedure.
• Among the tools that are available are schematic entry packages and hardware
description languages (HDLs), such as ABEL, VHDL, and Verilog.
• Synthesis tools are available that allocate, configure, and connect logic blocks to
match a high‐level design description written in HDL.
• One such example is Xilinx CMOS FPGA technology.

53
Field‐programmable gate array (FPGA)
FPGA Basic Xilinx Architecture:
• The basic architecture of Spartan and
earlier device families consists of
• An Array of configurable logic
blocks (CLBs),
• A variety of local and global routing
resources, and
• Input–Output (I/O) blocks (IOBs),
• Programmable I/O buffers, and
• An SRAM‐based configuration
memory.

54
 Field‐programmable gate array (FPGA)
Configurable logic blocks
(CLBs):
Each CLB consists of
• Programmable LUT,
• Multiplexers,
• Registers, and
• Paths for Control signals.

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 Field‐programmable gate array (FPGA)
Configurable logic blocks (CLBs):
• Two of the function generators (F and G) of the lookup table can generate any
arbitrary function of four inputs, and the third (H) can generate any Boolean
function of three inputs.
• The three function generators can be programmed to generate
1. Three different functions of three independent sets of variables.
2. An arbitrary function of five variables,
3. An arbitrary function of four variables together with some functions of six
variables, and
4. Some functions of nine variables.
• Each CLB has two storage devices that can be configured as edge‐triggered flip‐flops
with a common clock.

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 Field‐programmable gate array (FPGA)
Configurable logic blocks (CLBs):
Distributed RAM:
• The three function generators within a CLB can be used as either a 16 * 2 dual‐port
RAM or a 32 * 1 single‐port RAM.
• The XC4000 devices do not have block RAM, but a group of their CLBs can form an
array of memory.
• Spartan devices have block RAM in addition to distributed RAM.

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 Field‐programmable gate array (FPGA)
Interconnect Resources:
• A grid of switch matrices overlays the architecture of CLBs to provide
general‐purpose interconnect for branching and routing throughout the device.
• The interconnect has three types:
• Single‐length lines,
• Double‐length lines, and
• Long lines.
• A grid of horizontal and vertical single‐length lines connects an array of switch
boxes that provide a reduced number of connections between signal paths within
each box.
• Direct (dedicated) interconnect lines provide routing between adjacent vertical and
horizontal CLBs in the same column or row (high speed lines compared to general
purpose lines).

58
 Field‐programmable gate array (FPGA)
Interconnect Resources:
• A grid of switch matrices overlays the architecture of CLBs to provide
general‐purpose interconnect for branching and routing throughout the device.
• The interconnect has three types:
• Single‐length lines,
• Double‐length lines, and
• Long lines.
• A grid of horizontal and vertical single‐length lines connects an array of switch
boxes that provide a reduced number of connections between signal paths within
each box.
• Direct (dedicated) interconnect lines provide routing between adjacent vertical and
horizontal CLBs in the same column or row (high speed lines compared to general
purpose lines).

59
 Field‐programmable gate array (FPGA)
Interconnect Resources:
• Double‐length lines traverse the distance of two CLBs before entering a switch
matrix, skipping every other CLB.
• Long lines span the entire array vertically and horizontally.
• The programmable interconnect resources of the device connect CLBs and IOBs,
either directly or through switch boxes.

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 Field‐programmable gate array (FPGA)
I/O Block (IOB):
• Each programmable I/O pin has a
programmable IOB having buffers
for compatibility with TTL and
CMOS signal levels.
• Figure shows a simplified
schematic for a programmable IOB.
• It can be used as an input, an
output, or a bidirectional port.

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 Field‐programmable gate array (FPGA)
I/O Block (IOB):
• An IOB that is configured as an input can have direct, latched, or registered input.
• In an output configuration, the IOB has direct or registered output.
• The output buffer of an IOB has skew and slew control.
• The registers available to the input and output path of an IOB are driven by separate,
invertible clocks.
• There is a global set/reset.
• The three‐state output of an IOB puts the output buffer in a high‐impedance state.
• The output and the enable for the output can be inverted.

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 Field‐programmable gate array (FPGA)
I/O Block (IOB):
• There is an on‐chip test access port (TAP) controller, and the I/O cells can be
configured as a shift register.
• Under testing, the device can be checked to verify that all the pins on a PC board are
connected and operate properly by creating a serial chain of all of the I/O pins of the
chips on the board.
• A master three‐state control signal puts all of the IOBs in high‐impedance mode for
board testing.

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Summary
• Programming Logic Devices
• Combinational Programmable devices
• PLA
• PAL
• Sequential programmable devices
• CPLD.
• FPGA.

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