Lecture 12 Memory Reference Instruction and Input Output
Lecture 12 Memory Reference Instruction and Input Output
T0
AR <-- PC
T1
IR <-- M[AR], PC <-- PC + 1
T2
Decode Opcode in IR(12-14),
AR <-- IR(0-11), I <-- IR(15)
T3 T3 T3 T3
Execute Execute AR <-- M[AR] Nothing
input-output register-reference
instruction instruction
SC <-- 0 SC <-- 0 Execute T4
memory-reference
instruction
SC <-- 0
CSE 211
Basic Computer Organization and Design 2
D'7IT3: AR M[AR]
D'7I'T3:Nothing
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CSE 211
In case of Register Reference Instructions, CLA Stands for ……….
- The effective address of the instruction is in AR and was placed there during
timing signal T2 when I = 0, or during timing signal T3 when I = 1
- Memory cycle is assumed to be short enough to complete in a CPU cycle
- The execution of MR instruction starts with T4
CSE 211
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CSE 211
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BSA:
D 5 T4 : M[AR] PC, AR AR + 1
D 5 T5 : PC AR, SC 0
BSA: Example
M[135] 21, PC 135 + 1=136
AR = 135 135 21
136 Subroutine PC = 136 Subroutine
CSE 211
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D6T4: DR M[AR]
D6T5: DR DR + 1
D6T4: M[AR] DR, if (DR = 0) then (PC PC + 1), SC 0
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D 0T 4 D 1T 4 D 2T 4 D 3T 4
D 0T 5 D 1T 5 D 2T 5
AC AC DR AC AC + DR AC DR
SC 0 E Cout SC 0
SC 0
D 4T 4 D 5T 4 D 6T 4
PC AR M[AR] PC DR M[AR]
SC 0 AR AR + 1
D 5T 5 D 6T 5
PC AR DR DR + 1
SC 0
D 6T 6
M[AR] DR
If (DR = 0)
then (PC PC + 1)
SC 0
CSE 211
Which of the following instructions is used to save the return
address?
A) BUN
B) BSA
C) ISZ
D) None of the above
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AC
Transmitter
Keyboard interface INPR FGI
INPR Input register - 8 bits
OUTR Output register - 8 bits Serial Communications Path
FGI Input flag - 1 bit
Parallel Communications Path
FGO Output flag - 1 bit
IEN Interrupt enable - 1 bit
Initially FGO=1,
- computer checks flag bit if 1, then OUTR AC and
clears FGO=0
- O/P device accepts information prints character and
finally sets FGO=1.
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Basic Computer Orgsnisation and Design 13
Input/Output Instructions
I/O instructions are needed for transferring info to and from AC register, for
checking the flag bits and for controlling interrupt facility
D7IT3 = p
IR(i) = Bi, i = 6, …, 11
p: SC 0 Clear SC
INP pB11: AC(0-7) INPR, FGI 0 Input char. to AC
OUT pB10: OUTR AC(0-7), FGO 0 Output char. from AC
SKI pB9: if(FGI = 1) then (PC PC + 1) Skip on input flag
SKO pB8: if(FGO = 1) then (PC PC + 1) Skip on output flag
ION pB7: IEN 1 Interrupt enable on
IOF pB6: IEN 0 Interrupt enable off
CSE 211