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Lecture 12 Memory Reference Instruction and Input Output

The document outlines the basic computer organization and design, focusing on instruction types and their execution cycles. It details the processes for register reference and memory reference instructions, including specific operations like AND, ADD, LDA, and STA. Additionally, it covers input/output instructions and their interaction with registers and flags for managing data transfer between the computer and external devices.

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0% found this document useful (0 votes)
13 views

Lecture 12 Memory Reference Instruction and Input Output

The document outlines the basic computer organization and design, focusing on instruction types and their execution cycles. It details the processes for register reference and memory reference instructions, including specific operations like AND, ADD, LDA, and STA. Additionally, it covers input/output instructions and their interaction with registers and flags for managing data transfer between the computer and external devices.

Uploaded by

YOT BSS
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Basic Computer Organization and Design 1

Determine the Type of Instructions


Start
SC <-- 0

T0
AR <-- PC

T1
IR <-- M[AR], PC <-- PC + 1

T2
Decode Opcode in IR(12-14),
AR <-- IR(0-11), I <-- IR(15)

(Register or I/O) = 1 = 0 (Memory-reference)


D7

(I/O) = 1 = 0 (register) (indirect) = 1 = 0 (direct)


I I

T3 T3 T3 T3
Execute Execute AR <-- M[AR] Nothing
input-output register-reference
instruction instruction
SC <-- 0 SC <-- 0 Execute T4
memory-reference
instruction
SC <-- 0

Fig : Flow chart for Instruction Cycle

CSE 211
Basic Computer Organization and Design 2

Determining Type of Instruction

D'7IT3: AR M[AR]

D'7I'T3:Nothing

D7I'T3: Execute a register-reference instr.

D7IT3: Execute an input-output instr.

CSE 211
Basic Computer Organization and Design 3

Register Reference Instruction


Register Reference Instructions are identified when
- D7 = 1, I = 0
- Register Ref. Instr. is specified in b0 ~ b11 of IR
- Execution starts with timing signal T3

r = D7 IT3 => Register Reference Instruction


Bi = IR(i) , i=0,1,2,...,11 e.g. rB11=CLA
r: SC  0
CLA rB11: AC  0
CLE rB10: E0
CMA rB9: AC  AC’
CME rB8: E  E’
CIR rB7: AC  shr AC, AC(15)  E, E  AC(0)
CIL rB6: AC  shl AC, AC(0)  E, E  AC(15)
INC rB5: AC  AC + 1
SPA rB4: if (AC(15) = 0) then (PC  PC+1)
SNA rB3: if (AC(15) = 1) then (PC  PC+1)
SZA rB2: if (AC = 0) then (PC  PC+1)
SZE rB1: if (E = 0) then (PC  PC+1)
HLT rB0: S  0 (S is a start-stop flip-flop)

CSE 211
In case of Register Reference Instructions, CLA Stands for ……….

A) Clear Address Register


B) Clear Accumulator Register
C) Clear Account Register
D) None of the above
Basic Computer Organization and Design 5

Memory Reference Instructions


Operation
Symbol Symbolic Description
Decoder
AND D0 AC  AC  M[AR]
ADD D1 AC  AC + M[AR], E  Cout
LDA D2 AC  M[AR]
STA D3 M[AR]  AC
BUN D4 PC  AR
BSA D5 M[AR]  PC, PC  AR + 1
ISZ D6 M[AR]  M[AR] + 1, if M[AR] + 1 = 0 then PC  PC+1

- The effective address of the instruction is in AR and was placed there during
timing signal T2 when I = 0, or during timing signal T3 when I = 1
- Memory cycle is assumed to be short enough to complete in a CPU cycle
- The execution of MR instruction starts with T4

AND to AC //performs AND logic with AC and memory word specified by EA


D0T4: DR  M[AR] Read operand
D0T5: AC  AC  DR, SC  0 AND with AC

CSE 211
Basic Computer Organization and Design 6

Memory Reference Instructions


ADD to AC // add content of memory word specified by EA to value of AC
sum is transferred to AC and Carry to E (Extended Accumulator)

D1T4: DR  M[AR] Read operand


D1T5: AC  AC + DR, E  Cout, SC  0 Add to AC and store carry in E

LDA: Load to AC // Transfers memory word specified by memory address to AC


D2T4: DR  M[AR]
D2T5: AC  DR, SC  0

STA: Store AC // Stores the content of AC into memory specified by EA


D3T4: M[AR]  AC, SC  0

BUN: Branch Unconditionally // Transfer program to instruction specified by EA


D4T4: PC  AR, SC  0

CSE 211
Basic Computer Organization and Design 7

Memory Reference Instructions


BSA: Branch and Save Return Address // 1. stores address of next instruction in sequence (PC) into
address specified by EA 2. EA+1 transfer to PC serve as 1st inst. In subroutine
M[AR]  PC, PC  AR + 1

BSA:
D 5 T4 : M[AR]  PC, AR  AR + 1
D 5 T5 : PC  AR, SC  0
BSA: Example
M[135]  21, PC  135 + 1=136

Memory, PC, AR at time T4 Memory, PC after execution


20 0 BSA 135 20 0 BSA 135
PC = 21 Next instruction 21 Next instruction

AR = 135 135 21
136 Subroutine PC = 136 Subroutine

1 BUN 135 1 BUN 135

CSE 211
Basic Computer Organization and Design 8

Memory Reference Instructions

ISZ: Increment and Skip-if-Zero


// increments the word specified by effective address,
and if incremented value=0 , PC incremented by 1

D6T4: DR  M[AR]
D6T5: DR  DR + 1
D6T4: M[AR]  DR, if (DR = 0) then (PC  PC + 1), SC  0

CSE 211
Basic Computer Organization and Design 9

Flow Chart - Memory Reference Instructions


Memory-reference instruction

AND ADD LDA STA

D 0T 4 D 1T 4 D 2T 4 D 3T 4

DR  M[AR] DR  M[AR] DR  M[AR] M[AR]  AC


SC  0

D 0T 5 D 1T 5 D 2T 5
AC  AC DR AC  AC + DR AC  DR
SC  0 E  Cout SC  0
SC  0

BUN BSA ISZ

D 4T 4 D 5T 4 D 6T 4
PC  AR M[AR]  PC DR  M[AR]
SC  0 AR  AR + 1

D 5T 5 D 6T 5

PC  AR DR  DR + 1
SC  0
D 6T 6
M[AR]  DR
If (DR = 0)
then (PC  PC + 1)
SC  0

CSE 211
Which of the following instructions is used to save the return
address?

A) BUN
B) BSA
C) ISZ
D) None of the above
Basic Computer Organization and Design 11

Input/Output and Interrupt


A Terminal with a keyboard and a Printer
Input-Output Configuration
Input-output Serial Computer
terminal communication registers and
interface
flip-flops
Receiver
Printer interface OUTR FGO

AC

Transmitter
Keyboard interface INPR FGI
INPR Input register - 8 bits
OUTR Output register - 8 bits Serial Communications Path
FGI Input flag - 1 bit
Parallel Communications Path
FGO Output flag - 1 bit
IEN Interrupt enable - 1 bit

- The terminal sends and receives serial information


- The serial info. from the keyboard is shifted into INPR
- The serial info. for the printer is stored in the OUTR
- INPR and OUTR communicate with the communication interface serially and with
the AC in parallel.
- The flags are needed to synchronize the timing difference between I/O device and
the computer
CSE 211
Basic Computer Organization and Design 12

Determining Type of Instruction

 FGI =1 when new information available at input device,


and cleared to 0 when information accepted by
computer

 Initially FGI=0, new key pressed , 8 bit alphanumeric


shifted to INPR and FGI=1, Computer checks flag if 1
then transfer content to AC and clear FGI to 0.

 Initially FGO=1,
- computer checks flag bit if 1, then OUTR  AC and
clears FGO=0
- O/P device accepts information prints character and
finally sets FGO=1.

CSE 211
Basic Computer Orgsnisation and Design 13

Input/Output Instructions
I/O instructions are needed for transferring info to and from AC register, for
checking the flag bits and for controlling interrupt facility

D7IT3 = p
IR(i) = Bi, i = 6, …, 11

p: SC  0 Clear SC
INP pB11: AC(0-7)  INPR, FGI  0 Input char. to AC
OUT pB10: OUTR  AC(0-7), FGO  0 Output char. from AC
SKI pB9: if(FGI = 1) then (PC  PC + 1) Skip on input flag
SKO pB8: if(FGO = 1) then (PC  PC + 1) Skip on output flag
ION pB7: IEN  1 Interrupt enable on
IOF pB6: IEN  0 Interrupt enable off

CSE 211

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