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lab5

The lab assignment involves designing a circuit to display numbers 0 to 7 on a seven-segment display using a modular approach, with specific operations for writing and reading data. Students are required to create a test bench, synthesize the circuit, and analyze resource utilization in an FPGA. A written report detailing design sketches, K-maps, and synthesis summaries is also required, with an emphasis on understanding the code and avoiding blind copying.

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Ahsaan
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2 views

lab5

The lab assignment involves designing a circuit to display numbers 0 to 7 on a seven-segment display using a modular approach, with specific operations for writing and reading data. Students are required to create a test bench, synthesize the circuit, and analyze resource utilization in an FPGA. A written report detailing design sketches, K-maps, and synthesis summaries is also required, with an emphasis on understanding the code and avoiding blind copying.

Uploaded by

Ahsaan
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Lab Assignment 5

Sequential Circuits

1 Lab Tasks
a) The customer asks you to build a circuit to display different numbers (0
to 7) on a seven-segment display. The circuit has the following modular
diagram. The user stores the number to display on first seven-segment dis-
4

1
3
num

sel 2

wr
clk
reset 7

Figure 1: A block diagram of the circuit.

play by choosing sel = 2‘b00, num_in = desired number and turning


the switch wr ON and then OFF. Similarly, the user stores the numbers
to display on other three seven-segment display by following the same
method except choosing a different memory location with the help of sel
signal. At the end of the writing process, with WR=0, all the seven-segment
displays should show all the stored numbers at the same time.
Table 1 explains the operations in the circuit in more detail. We will first
use the write operation to store the four values corresponding to different
seven-segment displays. After the write operation, we will read the stored
numbers using WR=0 only.
All the seven-segment displays share the same data wires. Therefore,
at any point in time, we are limited to display only one number on a
single display. However, if we enable different seven-segment displays fast
enough, it can create an illusion that all seven-segment displays are turned
The lab manual is for the exclusive use of the students of University of Engineering and
Technology, Lahore. c 2019 UET Lahore.

1
Table 1: Input/Output Truth Table
OPERATION RESET SEL WR DATA D1 D2 D3 D4
RESET OPERATION 1 XX 0 X 0 0 0 0
0 00 1 1 1 OFF OFF OFF
0 01 1 2 OFF 2 OFF OFF
WRITE OPERATION
0 10 1 3 OFF OFF 3 OFF
0 11 1 4 OFF OFF OFF 4
READ OPERATION 0 XX 0 X 1 2 3 4

ON. Human eyes cannot perceive that a display is turning ON and OFF
if this switching happens for more than 24 times a second. To be on the
safe side, you can switch different displays ON and OFF at a rate of 100
times per second (100 Hz).
The lab requires that the circuit should have a time reference in it. The
starter kit board provides an on board clock signal of 50 MHz (see the
starter kit data sheet for more information). However, if you make a
circuit that switches different seven-segment displays at a rate of 50M
times per second, the seven-segment display drivers may not be able to
respond to such a high frequency change. Therefore, you will need to
bring the clock down to approximately 100 Hz as discussed above (Hint:
To bring the clock down to 100 Hz from 50 MHz, you may be able to use
a toggle flip-flop in a clever way. Look at the output of a toggle flip-flop
carefully.).
For information on seven-segment display, refer to the data sheet of the
starter kit.
You are NOT allowed to use latches in your design for the assignment.
b) Design a test bench for the circuit of part (a). The test bench should
simulate the way you test your hardware in the lab. For example, in the
start of the test bench, try writing to all memory locations and then start
the read operation instead of iterating through all the possible input data
patterns.
c) Synthesize the circuit for the starter kit available in the lab. Tie inputs to
the switches and outputs to the seven-segment displays available on the
board.

2 Questions
Answer the following questions:
a) Read the synthesis report and identify how many resources in the FPGA
such as lookup tables (LUTs), input/output (IOs), etc., has been utilized.

2
Is this resource usage equal to the resource usage of the circuit you de-
signed on paper?
b) If we increase or decrease the switching rate of different seven-segment
displays, what happens? Try changing the switching rate to 200, 50, and
10 Hz.

3 Instructions
a) A written report is required for this lab. The report should include the
following:

(a) A hand-sketched design partition of the system. The design partition


should include multiplexers, demultiplexers, encoders, decoders, flip-
flops, and should avoid gates as much as possible.
(b) A hand-sketched gate-level diagram of different components used in
part (a) above.
(c) Different K-maps used to generate component circuits.
(d) The device resource utilization summary from the synthesis report.

b) You may reuse any components you made in lab 4.


c) The design should use behavioral modeling only for the components you
have studied in the class uptil the lab grading day. For all other compo-
nents, use structural modeling.
d) It is recommended that you bring your simulation in your laptop so that
you can quickly get your assignment partially graded. Otherwise, you will
have to share the computer in the lab and may have to wait. However,
you will need to transfer your code to the lab computer using USB anyway
for the synthsis and downloading the code to the FPGA.
e) The collaboration between students is encouraged, but blind code shar-
ing/copying is not allowed. If you are unable to explain anything in your
code, it will be assumed you have copied it blindly. So make sure you
know every thing you have written in your code. I am least concerned
about how you have learnt something as long as you have learnt it well.

The lab manual is for the exclusive use of the students of University of Engineering and
Technology, Lahore. c 2019 UET Lahore.

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