CD/JUL 2024/ITT270

UNIVERSITI TEKNOLOGI MARA

FINAL EXAMINATION

COURSE DIGITAL ELECTRONICS

COURSE CODE ITT270
EXAMINATION JULY 2024
TIME 3 HOURS

INSTRUCTIONS TO CANDIDATES

1. This question paper consists of three (3) parts: PART A (10 Questions)
PART B (5 Questions)
PART C (3 Questions)

2. Answer ALL questions in the Answer Booklet. Start each answer on a new page.

3. Do not bring any material into the examination room unless permission is given by the invigilator.

4. Please check to make sure that this examination pack consists of:

the Question Paper

a one - page Appendix
an Answer Booklet - provided by the Faculty

5. Answer ALL questions in English.

DO NOT TURN THIS PAGE UNTIL YOU ARE TOLD TO DO SO

This examination paper consists of 10 printed pages

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PART A (20 MARKS)

Answer ALL questions.

1. Don't care conditions can be used for simplifying Boolean expressions in

A. Registers
B. Terms
C. K-maps
D. Latches

2. Which of the following is TRUE about Signed Numbers System?

I. Signed numbers system is used to indicate whether a binary number is a negative

or a positive.
II. Signed numbers system has three parts which are sign bit, magnitude and range.
III. Signed numbers system could have -0 and +0 in its range.
IV. Sign-magnitude is commonly used in practice for representing integer numbers.

A. I, II, III
B. I, II, IV
C. I, III
D. I, II, III, IV

3. To construct a 4-bit parallel adder, which of the following circuits are needed?

A. A single full-adder and three half-adder circuits.

B. A single half-adder and three full-adder circuits.
C. A single full-adder and single half-adder circuits.
D. A single half-adder and single full-adder circuits.

Processing

Figure 1. Block Diagram of Calculator

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4. Based on the image in Figure 1, what is the function of x?

A. Display the decimal number in the screen.

B. Perform the operation of the calculator.
C. Convert the decimal number into a binary code.
D. Translate the binary code to seven-segrnent display decimal.

5. "To ensure that when 2 or more inputs are activated, the output code will correspond
to the highest numbered input". Which of the following refer to this statement?

A. Decoder
B. Priority Decoder
C. Encoder
D. Priority Encoder

6. Which of the following modes does NOT operate in S-R flip-flops?

A. Set mode
B. Reset mode
C. Toggle mode
D. Hold mode

7. Flip-flops are wired together to form a counter. What is the use of counters in digital
electronics?

A. Counters can perform arithmetic operations in the circuit.

B. Counters count the number of times events occurred in the circuit.
C. Counters contain the same information as the truth table.
D. Counters used to convert from one code to another code.

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8. Which statements are true about mod-4 counter?

I. Each flip-flop in mod-4 counter is in its toggle mode.

II. Mod-4 counter is designed to produce special-purpose count sequences of non-
consecutive numbers.
III. A clock pulse needs to be supplied to each of the flip-flops in mod-4 counter.
IV. Modulus of the mod-4 counter is 4.

A. I and II only
B. I and IV only
C. I, II and IV only
D. I, III and IV only

9. How is RAM organized?

A. As a single memory cell.

B. As an array of memory cells with an address decoder and I/O drivers.
C. As a combination of ROM and cache memory.
D. As a stack of memory blocks.

10. What happens if Read/Write = 1 in a memory cell?

A. The data from the Input will be output.

B. The data from the Input will be stored in the latch.
C. The data from the row selected will be output.
D. The data from the row selected will be stored in the latch.

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PART B (35 MARKS)

Answer ALL questions.

QUESTION 1

T a b l e ! Truth table

A B c D w
0 0 0 0 1
0 0 0 1 1
0 0 1 0 1
0 0 1 1 0
0 1 0 0 1
0 1 0 1 0
0 1 1 0 i
0 1 1 1 0
1 0 0 0 0
1 0 0 1 1
1 0 1 0 1
1 0 1 1 0
1 1 0 0 0
1 1 0 1 X
1 1 1 0 X
1 1 1 1 X

Given the truth table in Table 1, answer the following questions.

a. Determine the Boolean expression for the logic circuit using Karnaugh map.

(2 marks)

b. Draw the logic circuit.

(2 marks)

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QUESTION 2
a. Explain the difference between half-adder and full-adder circuit.

(2 marks)

b. Determine the range of integers for 10-bit two's complement number.

(2 marks)

c. Answer the following questions based on 10-bit two's complement number. Show your
steps of solution.

i) Perform-120io-119io.

(3 marks)

ii) Perform 90io - 100i0.

(3 marks)

QUESTION 3

a. Derive the truth table for 8:3 priority encoder.

(2 marks)

b. Write and simplify the expression of the output A.

(2 marks)

c. Derive the decoder and an OR gate of the following expression:

Y = (A © C) + (B + C) + ABC
(4 marks)

QUESTION 4

a. What are the primary characteristics and operational principles of an S-R latch?

(2 Marks)

b. Briefly explain using block diagram on how D flip-flop can be applied as storage register.

(4 Marks)

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QUESTION 5

Given a 64K x 8-bit memory chip:

a. Identify the number of memory cells.

(1 mark)

b. Identify the number of address lines.

(1 mark)

c. How many chips are needed to expand the capacity to 256K x 8-bit memory

(1 mark)

d. Illustrate the expanded memory diagram based on question 5(c).

(4 marks)

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PART C (45 MARKS)

Answer ALL questions.

QUESTION 1
The operation of Sg Kelantan's Flood Warning System (FWS) is depicted as a block diagram
in Figure 2. The goal of FWS is to alert residents living close to Sg Kelantan of the potential
for flooding, which could happen depending on Sg Kelantan's water level.

Water Green Yellow Red Siren

Level
9 9 <*))
7HI"
Water Level
BM- Logic Circuit
Sensor
5M-

*T-IVF

3M-

2M-

1M

Figure 2: Diagram of Flood Warning System (FWS) operation

The water level detector will function as follows:

Water Level Flood Risk Warning Alert

0-2 Normal Green light, siren off
3-4 Moderate Yellow light on, siren off
5-6 Warning Red light on, siren off
7 Danger Red light on, siren on

Assume that indicator ON is equal to 1 and OFF equal to 0.

Design the logic circuit. Your solution must include:

a. Truth table.
(4 marks)

b. Karnaugh map and its simplified expressions.

(6 marks)

c. Logic circuit.
(5 marks)

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QUESTION 2

Design a synchronous counter using JK flip-flops to produce the counting sequence as shown
in Figure 3.

Figure 3

Your solution should include the following:

a. Transition table.
(6 marks)

b. Karnaugh map for J and K.

(6 marks)

c. Counter circuit.
(3 marks)

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QUESTION 3
Determine the counting sequence for the counter circuit as shown in Figure 4.

A 3 r

10V
+v
) ^ >
s s s
Q J Q J Q
CP - CP Q o CP _
K Q K K Q
R R
TR 1—

V
CP1Q1
CP2Q2

Figure 4

Your solution should include:

a. J and K expressions.
(3 marks)

b. Transition table.
(8 marks)

c. State transition diagram.

(4 marks)

END OF QUESTION PAPER

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 APPENDIX 1 CD/JUL 2024/ITT270

BOOLEAN ALGEBRA LAWS AND THEOREMS, DE MORGAN'S THEOREMS

1. x«o = o 8. X+X=1 14. X+XY = X

2. X«1 = X 9. X+Y= Y+X 15. X + XY=X + Y

3. X«X = X 10. X«Y = Y«X 16. X + Y = X«Y

4. X»X=0 11. X+(Y+Z) = (X+Y)+Z = X+Y+Z 17. XY = X + Y

5. X+0= X 12. X(YZ) = (XY)Z = XYZ
18. X = X
6. X+1= 1 13.1 X(Y+Z) = XY + XZ

7. X+X=X 13.2 (A+B)(C+D) = AC + AD +BC+ BD

UNIVERSALITY OF NAND AND NOR GATES

NOT GATE AND GATE

t ) J
A
B
1
Y = AA = A Y = AB = AB

LJ O Y nE>
B »

A + A = A»A = A

Y = A + B = A.B = A.B

OR GATE
A —J-j
V
^y

Y = A.B = A + B = A + B Y=A+B=A+B

XOR EXPRESSION

A 0 B = A.B + A.B A © B = A.B + AB

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