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11 April 2020 1441 ‫ شعبان‬18

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Digital IC Design

Lecture 09
CMOS Dynamic (Transient) Characteristics

Dr. Hesham A. Omran

Integrated Circuits Laboratory (ICL)
Electronics and Communications Eng. Dept.
Faculty of Engineering
Ain Shams University
This lecture is mainly based on “CMOS VLSI Design”, 4th edition, by N. Weste and D. Harris and
its accompanying lecture notes
 Transient Response
❑ The two most common metrics for a good chip are speed and power
▪ First, we will talk about speed
▪ Next, we will talk about power
❑ DC analysis tells us Vout if Vin is constant
❑ Transient analysis tells us Vout(t) if Vin(t) changes
▪ Requires solving differential equations
▪ We need to develop simpler delay models
❑ Input is usually considered to be a step or ramp
▪ From 0 to VDD or vice versa

09: Dynamic (Transient) Ccs 2

 Delay Definitions
❑ Why delay may be different?
▪ Rise/fall time of input A Y
▪ Multiple inputs or paths
▪ Slow when hot and fast when cold tpd
❑ 𝑡𝑝𝑑 : Propagation delay A
▪ maximum time from the input crossing 50% to the
output crossing 50%
Y
❑ 𝑡𝑐𝑑 : Contamination delay time
▪ minimum time from the input crossing 50% to the tcd
output crossing 50%
Time
❑ When an input changes, the output will
▪ retain its old value for at least 𝑡𝑐𝑑
▪ take on its new value in at most 𝑡𝑝𝑑
09: Dynamic (Transient) Ccs [Harris and Harris, DDCA, 2012] 3
 Delay Definitions cont’d
❑ 𝑡𝑝𝑑𝑟: Rising propagation delay
❑ 𝑡𝑝𝑑𝑓: Falling propagation delay
❑ 𝑡𝑝𝑑 : Average propagation delay

𝑡𝑝𝑑𝑟 + 𝑡𝑝𝑑𝑓
𝑡𝑝𝑑 =
2

❑ 𝑡𝑐𝑑𝑟: Rising contamination delay

❑ 𝑡𝑐𝑑𝑓 : Falling contamination delay
❑ 𝑡𝑐𝑑 : Average contamination delay

𝑡𝑐𝑑𝑟 + 𝑡𝑐𝑑𝑓
𝑡𝑐𝑑 =
2

09: Dynamic (Transient) Ccs 4

 Delay Definitions cont’d
❑ 𝑡𝑟: rise time
▪ From output crossing 0.2 VDD to 0.8 VDD
❑ 𝑡𝑓: fall time
▪ From output crossing 0.8 VDD to 0.2 VDD

❑ Driver: The gate that charges or discharges a

node
❑ Load: The gates and wire being driven

09: Dynamic (Transient) Ccs 5

 Timing Analysis
❑ Arrival time: the latest time at which each node in a block of logic will switch
❑ User defines arrival time of inputs
❑ User defines required time of outputs
❑ Slack = required time of outputs – arrival time of outputs
▪ Positive slack: timing requirements met (timing closure)
▪ Negative slack: timing requirements failed

09: Dynamic (Transient) Ccs 6

 Timing Analysis cont’d
❑ WNS: Worst negative slack
❑ TNS: Total negative slack (sum of all negative slacks)
▪ If WNS = TNS, what does this mean?
❑ Exercise:
▪ If the outputs are all required at 200 ps
▪ Slack = ?
▪ Timing requirements met?

09: Dynamic (Transient) Ccs 7

 Timing Optimization
❑ Critical paths: Paths that limit the operating speed of the system
▪ i.e., paths with max delay → with smallest slack
❑ Speed can be optimized at four levels
▪ The architectural/microarchitectural level
• e.g., no. of pipeline stages, memory size, etc.
▪ The logic level
• e.g., ripple vs lookahead adder, fan-in and fan-out, etc.
▪ The circuit level
• e.g., logic style (CMOS vs pass-transistor logic), sizing, etc.
▪ The layout level
• e.g., floorplanning, parasitic capacitance, etc.

09: Dynamic (Transient) Ccs 8

 Inverter Delay
❑ 𝛥𝑄 = 𝐶 ⋅ 𝛥𝑉
❑ 𝐼 = 𝛥𝑄/𝛥𝑡 = 𝐶 ⋅ 𝛥𝑉/𝛥𝑡
❑ 𝛥𝑡 = 𝐶 ⋅ 𝛥𝑉/𝐼
❑ The higher the capacitance the slower
▪ Gate capacitance 𝐶𝑔
▪ Diffusion capacitance 𝐶𝑑𝑖𝑓𝑓
▪ Wire capacitance 𝐶𝑤𝑖𝑟𝑒
❑ The higher the current the faster
▪ Starts in saturation (large 𝑉𝐷𝑆 )
▪ Then go to linear

09: Dynamic (Transient) Ccs 9

 Inverter Step Response
❑ Ex: find step response of inverter driving load cap
Vin (t ) = u(t − t0 )VDD
Vin(t)
Vout (t  t0 ) = VDD Vout(t)
Cload
dVout (t ) I dsn (t )
=−
dt Cload Idsn(t)


 0 t  t0 Vin(t)

I dsn (t ) =  
( − ) Vout  VDD − Vt
2
2
VDD V t
 Vout(t)
   VDD − Vt − Vout (t )  V (t ) V  V − V
 out t
  2 
out DD t t0

❑ Need to solve non-linear differential equation!

09: Dynamic (Transient) Ccs 10

 Simulated Inverter Delay
❑ Should we really solve the non-linear differential
equation?! 2.0

❑ Shockley square-law model has limited value

1.5
▪ Too complicated for hand analysis
▪ Not accurate enough for modern transistors (V)
1.0
tpdf = 66ps tpdr = 83ps
❑ SPICE simulator solves the equations numerically Vin
Vout
0.5
▪ Uses more accurate (and much more complex) I-V
models! 0.0

❑ But simulations take time to write, and may hide 0.0 200p 400p 600p 800p 1n
t(s)
insight
▪ Don’t be a SPICE monkey!

09: Dynamic (Transient) Ccs 11

 Delay Estimation: RC Model
❑ We would like to be able to easily estimate delay
▪ Not as accurate as simulation
▪ But easier to ask “What if?”
❑ The step response usually looks like a 1st order RC response with a decaying exponential.
❑ Simplification: treat transistor as resistor
▪ Replace 𝐼𝑑𝑠(𝑉𝑑𝑠, 𝑉𝑔𝑠) with effective resistance 𝑅
❑ Characterize transistors by finding their effective 𝑅
▪ Depends on average current as gate switches
❑ Use RC delay models to estimate delay
▪ 𝐶 = total capacitance on output node
▪ So that 𝑡𝑝𝑑 = 𝑅𝐶

09: Dynamic (Transient) Ccs 12

 First Order RC System
❑ 𝑡𝑝𝑑 = ln 2 ⋅ 𝑅𝐶 = 0.69 ⋅ 𝑅𝐶
❑ Define 𝑅 = 0.69𝑅
❑ 𝑡𝑝𝑑 = 𝑅𝐶

09: Dynamic (Transient) Ccs 13

 Effective Resistance Through Analysis
❑ Method #1:
▪ Assume output switches from 𝑉𝐷𝐷 to zero through NMOS
▪ Assume input is abrupt (zero rise time): 𝑉𝑖𝑛 = 𝑉𝐷𝐷
▪ 𝑡𝑝𝑑 is defined as the transition from 𝑉𝐷𝐷 to 𝑉𝐷𝐷 /2
▪ Assume the NMOS is velocity saturated: 𝑉𝑑𝑠𝑎𝑡 < 𝑉𝐷𝐷 /2
▪ The current will remain constant at ≈ 𝐼𝑂𝑁
▪ Take the average resistance value

09: Dynamic (Transient) Ccs [Rabaey, 2003] 14

 Effective Resistance Through Analysis
❑ Method #1:
1 𝑉𝐷𝐷 𝑉𝐷𝐷 /2 1 3 𝑉𝐷𝐷 3𝑉𝐷𝐷
𝑅= + = ⋅ ⋅ =
2 𝐼𝑂𝑁 𝐼𝑂𝑁 2 2 𝐼𝑂𝑁 4𝐼𝑂𝑁

09: Dynamic (Transient) Ccs [Rabaey, 2003] 15

 Effective Resistance Through Analysis
❑ Method #2:
▪ Actually input is not abrupt
▪ 𝑉𝑖𝑛 ≠ 𝑉𝐷𝐷
𝑉𝐷𝐷
▪ 𝑉𝑖𝑛 = → 𝑉𝐷𝐷
2
𝐼 +𝐼
▪ 𝐼𝑒𝑓𝑓 = 𝐿 𝐻
2
▪ Δ𝑡 = C ⋅ ΔV/𝐼 = 𝑅𝐶
𝑉𝐷𝐷 /2 𝑉𝐷𝐷
▪ 𝑅 = ΔV/𝐼 = =
𝐼𝑒𝑓𝑓 𝐼𝐿 +𝐼𝐻

09: Dynamic (Transient) Ccs 16

 Effective Resistance Through Analysis
❑ Both Method #1 and #2 are not very accurate and involve a lot of assumptions
▪ We also neglected channel length modulation and DIBL
❑ But at least we learnt an important result
𝑉𝐷𝐷
▪ 𝑅∝
𝐼𝐷
❑ For hand calculations, better to get the value of ‘𝑅’ by simulation

09: Dynamic (Transient) Ccs 17

 Effective Resistance Through Simulation
❑ Unit transistors
▪ May refer to minimum contacted device (4l / 2l)
▪ Or 1 mm wide device (usually better to avoid min width effects)
▪ Doesn’t matter as long as you are consistent
❑ Calculate effective resistance of unit transistor through simulation:
▪ R  10 kW•mm in 0.6 mm process
▪ R  1.25 kW•mm in 65 nm process
▪ Improves with shorter channel lengths (why?)
❑ For any transistor with 𝑊 = 𝑘𝑊𝑢𝑛𝑖𝑡
▪ 𝑹𝒆𝒒 = 𝑹/𝒌
❑ Remember that in digital we (almost) always use 𝐿𝑚𝑖𝑛

09: Dynamic (Transient) Ccs 18

 Capacitance
❑ Capacitance
▪ C = Cg = Cs = Cd = 2 fF/mm of gate width in 0.6 mm
▪ Gradually decline to 1 fF/mm in 65 nm
❑ For any transistor with 𝑊 = 𝑘𝑊𝑢𝑛𝑖𝑡
▪ 𝑪𝒆𝒒 = 𝒌𝑪
❑ Remember that in digital we (almost) always use 𝐿𝑚𝑖𝑛

09: Dynamic (Transient) Ccs 19

 RC Delay Model
❑ Use equivalent circuits for MOS transistors
▪ Ideal switch + capacitance and ON resistance
▪ Unit NMOS has resistance R, capacitance C
▪ Unit PMOS has resistance 2R, capacitance C (assumes 𝜇𝑛 /𝜇𝑝 = 2)
❑ Capacitance proportional to width
❑ Resistance inversely proportional to width
❑ Remember that series transistors will be faster than predicted (why?)

d
s
kC
kC
R/k
d 2R/k
d
g k g kC
g k g
s kC kC
kC s
s
d
09: Dynamic (Transient) Ccs 20
 Inverter Delay Estimate
𝑳𝒐𝒂𝒅 𝒄𝒂𝒑𝒂𝒄𝒊𝒕𝒂𝒏𝒆
❑ Define: 𝒇𝒂𝒏𝒐𝒖𝒕 = 𝒉 =
𝑰𝒏𝒑𝒖𝒕 𝒄𝒂𝒑𝒂𝒄𝒊𝒕𝒂𝒏𝒄𝒆
▪ Self-loading (parasitic capacitance of driver) not included in load capacitance
❑ Estimate the delay of a fanout-of-1 inverter

09: Dynamic (Transient) Ccs 21

 Delay Model Comparison
❑ Unit inverter:
▪ NMOS: 1𝜇𝑚/50𝑛𝑚
❑ SPICE delay is longer than that estimated by
square-law
▪ Because of mobility degradation and
velocity saturation
❑ RC model provides good approximation for 𝑡𝑝𝑑
❑ The fall time is overestimated

09: Dynamic (Transient) Ccs 22

 Example: Inverter Delay
❑ Estimate 𝑡𝑝𝑑 for a unit inverter driving m identical unit inverters
❑ Answer:
▪ Each load inverter presents 3𝐶 units of gate capacitance
▪ 𝑡𝑝𝑑 = 3 + 3𝑚 𝑅𝐶= 1 + 𝑚 3𝑅𝐶

09: Dynamic (Transient) Ccs 23

 Example: Inverter Delay cont’d
❑ Repeat if the driver is 𝑤 times unit size
❑ Answer:
▪ 𝑡𝑝𝑑 = 3𝑤 + 3𝑚 𝑅/𝑤 𝐶 = 1 + 𝑚/𝑤 3𝑅𝐶
𝑳𝒐𝒂𝒅 𝒄𝒂𝒑𝒂𝒄𝒊𝒕𝒂𝒏𝒆 𝑪𝑳 𝟑𝒎 𝒎
▪ 𝒇𝒂𝒏𝒐𝒖𝒕 = 𝒉 = = = =
𝑰𝒏𝒑𝒖𝒕 𝒄𝒂𝒑𝒂𝒄𝒊𝒕𝒂𝒏𝒄𝒆 𝑪𝒊𝒏 𝟑𝒘 𝒘
▪ 𝑡𝑝𝑑 = 1 + ℎ 3𝑅𝐶

09: Dynamic (Transient) Ccs 24

 Example: FO4 Inverter
❑ Example: 65𝑛𝑚 𝑝𝑟𝑜𝑐𝑒𝑠𝑠, 𝑅 = 1𝑘Ω ⋅ 𝜇𝑚, 𝐶 = 1𝑓𝐹/𝜇𝑚, ℎ = 4
❑ Answer:
▪ 𝑡𝑝𝑑 = 1 + ℎ 3𝑅𝐶 = 1 + 4 ⋅ 3 ⋅ 1𝑝𝑠 = 15𝑝𝑠
▪ FO4 delay is a figure-of-merit for the speed of the technology

09: Dynamic (Transient) Ccs 25

 Normalized Delay
❑ For loaded inverter:
▪ 𝑡𝑝𝑑 = 1 + ℎ 3𝑅𝐶
❑ If 𝒉 = 𝟎 (unloaded inverter, i.e., parasitic delay):
▪ 𝒕𝒑𝒅 = 𝟑𝑹𝑪 regardless of sizing!
❑ Define: 𝜏 = 𝑅𝑖𝑛𝑣 𝐶𝑖𝑛𝑣 = 3𝑅𝐶𝑔 = 3𝑅𝐶
▪ The delay of an ideal FO1 inverter that has no parasitic capacitance
▪ 𝑁𝑜𝑟𝑚𝑎𝑙𝑖𝑧𝑒𝑑 𝑑𝑒𝑙𝑎𝑦: 𝑑 = 𝑡𝑝𝑑 /𝜏
❑ Delay of loaded inverter:
▪ 𝑑 = 1 + ℎ → for FO4: 𝑑 = 5
▪ Independent of the process technology → Focus on topology

09: Dynamic (Transient) Ccs 26

 Example: 3-input NAND
❑ Sketch a 3-input NAND with transistor widths chosen to achieve (worst-case) effective rise
and fall resistances equal to a unit inverter (R).

09: Dynamic (Transient) Ccs 27

 Example: 3-input NAND
❑ Sketch a 3-input NAND with transistor widths chosen to achieve (worst-case) effective rise
and fall resistances equal to a unit inverter (R).

09: Dynamic (Transient) Ccs 28

 Example: 3-input NAND cont’d
❑ Annotate the NAND gate with its gate and diffusion capacitances. Assume all diffusion
nodes are contacted (shared contact).

09: Dynamic (Transient) Ccs 29

 Example: 3-input NAND cont’d
❑ Annotate the NAND gate with its gate and diffusion capacitances. Assume all diffusion
nodes are contacted (shared contact).

09: Dynamic (Transient) Ccs 30

 Example: 3-input NAND cont’d
❑ Sketch equivalent circuits for the worst-case falling output transition and rising output
transition
▪ How to calculate the delay?

09: Dynamic (Transient) Ccs 31

 First Order RC System
❑ 𝑡𝑝𝑑 = ln 2 ⋅ 𝑅𝐶 = 0.69 ⋅ 𝑅𝐶
❑ Define 𝑅 = 0.69𝑅
❑ 𝑡𝑝𝑑 = 𝑅𝐶

09: Dynamic (Transient) Ccs 32

 Second Order RC System
❑ Too complicated

❑ Use first order approximation (Elmore

delay model)
▪ OCTC: o.c. time constant technique

❑ Not good for n1

09: Dynamic (Transient) Ccs 33

 Elmore Delay Model
❑ ON transistors look like resistors
❑ Pullup or pulldown network modeled as RC ladder (tree)
▪ The root of the tree is the voltage source and the leaves are the capacitors
❑ Elmore delay of RC ladder
t pd  
nodes i
Ri −to − sourceCi

= R1C1 + ( R1 + R2 ) C2 + ... + ( R1 + R2 + ... + RN ) C N

OR
𝑡𝑝𝑑 = 𝑅1 𝐶1 + 𝐶2 + ⋯ + 𝐶𝑁 + 𝑅2 𝐶2 + 𝐶3 + ⋯ + 𝐶𝑁 + ⋯

R1 R2 R3 RN

C1 C2 C3 CN

09: Dynamic (Transient) Ccs 34

 Example: 3-input NAND cont’d
❑ Sketch equivalent circuits for the worst-case falling output transition and rising output
transition
▪ How to calculate the delay?

09: Dynamic (Transient) Ccs 35

 Example: 3-input NAND cont’d
❑ Falling: Input is GND, output is Y
𝑅 𝑅 𝑅 𝑅 𝑅 𝑅
𝑡𝑝𝑑𝑓 = ⋅ 3𝐶 + + ⋅ 3𝐶 + + + ⋅ 9𝐶
3 3 3 3 3 3
= 12𝑅𝐶
𝑑=4
❑ Rising: Input is 𝑉𝐷𝐷 , output is Y
𝑡𝑝𝑑𝑟 = 𝑅 9 + 3 + 3 𝐶
= 15𝑅𝐶
𝑑=5

09: Dynamic (Transient) Ccs 36

 Example: 3-input NAND cont’d
❑ Calculate 𝑡𝑝𝑑 (worst case delay) if the output is loaded with h identical NAND gates

h copies

09: Dynamic (Transient) Ccs 37

 Example: 3-input NAND cont’d
❑ The output is loaded with h identical NAND gates
❑ Falling: Input is GND, output is Y
𝑅 𝑅 𝑅 𝑅 𝑅 𝑅
𝑡𝑝𝑑𝑓 = ⋅ 3𝐶 + + ⋅ 3𝐶 + + + ⋅ 9 + 5ℎ 𝐶
3 3 3 3 3 3
= 12 + 5ℎ 𝑅𝐶
5
𝑑 =4+ ℎ
3

❑ Rising: Input is 𝑉𝐷𝐷 , output is Y

𝑡𝑝𝑑𝑟 = 𝑅 9 + 5ℎ + 3 + 3 𝐶
= 15 + 5ℎ 𝑅𝐶
5
𝑑 =5+ ℎ
3
09: Dynamic (Transient) Ccs 38
 Example: 3-input NAND cont’d
❑ Calculate 𝑡𝑐𝑑 (best case delay) if the output is loaded with h identical NAND gates

h copies

09: Dynamic (Transient) Ccs 39

 Example: 3-input NAND cont’d
❑ The output is loaded with h identical NAND gates
❑ Falling: Input is GND, output is Y (n1 and n2 initially discharged)
𝑅 𝑅 𝑅
𝑡𝑐𝑑𝑓 = + + ⋅ 9 + 5ℎ 𝐶
3 3 3
= 9 + 5ℎ 𝑅𝐶
❑ Rising: Input is 𝑉𝐷𝐷 , output is Y
𝑅
𝑡𝑐𝑑𝑟 = 9 + 5ℎ 𝐶
3
5
= 3 + ℎ 𝑅𝐶
3
❑ Both significantly smaller!

09: Dynamic (Transient) Ccs 40

 Capacitance Layout Dependence
❑ We assumed contacted diffusion on every S/D.
❑ Good layout minimizes diffusion area
❑ Ex: NAND3 layout shares one diffusion contact between two PMOS
▪ Reduces output capacitance from 9C to 7C
▪ Merged uncontacted diffusion might help too

2C 2C
Shared
Contacted
Diffusion Isolated
Contacted 2 2 2
Merged Diffusion
Uncontacted 3 7C
Diffusion 3 3C

3C 3C 3C 3 3C

09: Dynamic (Transient) Ccs 41

 Capacitance Layout Dependence cont’d
❑ Which layout is better?

VDD VDD
A B A B

Y Y

GND GND

09: Dynamic (Transient) Ccs 42

 Capacitance Layout Dependence cont’d
❑ Folding wide transistors reduces diffusion capacitance (a.k.a. multifinger layout)
❑ Let min device (4𝜆/2𝜆) has cap C
❑ Unfolded inverter:
▪ NMOS: 12/2 = 3*(4/2) → 3C
▪ PMOS: 24/2 = 6*(4/2) → 6C
▪ Total cap: 9C
❑ Folded inverter:
▪ Drain area reduced to half
▪ Total cap: 4.5C
❑ Other benefits:
▪ Fits better within std cell height
▪ Reduces gate resistance
▪ Using std width reduces variability
09: Dynamic (Transient) Ccs 43
 Thank you!

09: Dynamic (Transient) Ccs 44