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DSD Lab-3

Lab #3 focuses on Behavioral Modeling of digital circuits using Verilog, where students will design an 8 to 1 MUX, a 4-bit ripple counter, and an Arithmetic Logic Unit (ALU). Each task includes creating a Verilog module, writing a stimulus module for testing, and simulating the designs in ModelSim. Students must compile their projects, verify results, and complete a lab report detailing objectives, functionality, and analysis.

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0% found this document useful (0 votes)
2 views

DSD Lab-3

Lab #3 focuses on Behavioral Modeling of digital circuits using Verilog, where students will design an 8 to 1 MUX, a 4-bit ripple counter, and an Arithmetic Logic Unit (ALU). Each task includes creating a Verilog module, writing a stimulus module for testing, and simulating the designs in ModelSim. Students must compile their projects, verify results, and complete a lab report detailing objectives, functionality, and analysis.

Uploaded by

mohammaduzair726
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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CPE3341: Digital System Design Lab

Design Lab # 3
Verilog: Behavioral Modeling
Objective: Lab #3 will familiarize students with Behavioral Modeling of digital
circuits in Verilog Programming Language. Students will also learn about writing
test-benches in Verilog behavioral modeling for digital designs.

Tasks included in this Lab are :

9. Design behavioral model of an 8 to 1 MUX in Verilog HDL

10. Write a Stimulus module to test the functionality of MUX

11. Design behavioral model of a 4-bit ripple counter in Verilog HDL

12. Write Stimulus module to test the functionality of 4-bit ripple counter

13. Write Design Module and Stimulus for an Arithmetic Logic Unit (ALU) in
Verilog

Complete your Lab Assignments in Lab and show the results to Lab Instructor.

3 Lab Assignment

3.1 Design of 8 to 1 MUX

(a). Create a new ModelSim project. Project will simulate a 8 to 1 MUX Module

(b). Add new file of type Verilog to the project. Write Verilog module for 8 to 1 MUX in Verilog
Behavioral Modeling using ‘Case Statement’.

(c). Add new file of type Verilog to the same project. Write Stimulus module for testing and
verification of 8 to 1 MUX in the file. Stimulus module should instantiate the 8 to 1 MUX
module.

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Give different input combinations of input and selection lines to the design module. Use the
$monitor to display all inputs and outputs of the 8 to 1 MUX module.

(d). Compile the project and correct any syntax errors. Next simulate the project and display
results in output window. Also verify timing waveform of output

Verify the results and show them to the lab instructor

3.2 Design of 4-bit Synchronous Counter

(a). Create a new ModelSim project. Project will simulate a 4-bit synchronous counter Module in
behavioral Modeling

(b). Add new file of type Verilog to the project. Write Verilog module for 4-bit synchronous
counter in behavioral modeling in the file.

synchronous counter will work on posedge of clock and will reset on negedge of reset signal
(active low reset).

(c). Add new file of type Verilog to the same project. Write Stimulus module for testing and
verification of 4-bit synchronous counter in the file. Stimulus module should instantiate the 4-
bit synchronous counter module.

Generate Clock signal and active low Reset signal in the stimulus module and input them to the
Counter module.

Use the $monitor to display all inputs and outputs of the 4-bit synchronous counter module.

(d). Compile the project and correct any syntax errors. Next simulate the project and display
results in output window. Also display counter module waveforms in waveform window.

Verify the results and show them to the lab instructor

Below is circuit diagram of 4-bit synchronous counter

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Figure 20. 4-bit synchronous Counter Circuit

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Design Lab # 3

Lab Assignments
Activity# 01

• Create a new project in ModelSim, add the files containing 8 to 1 MUX module and
Stimulus module to the project
• Compile and run the simulation of 8 to 1 MUX in ModelSim
• Display inputs and outputs of 8 to 1 MUX using $monitor. Also show timing waveforms
to Lab Instructor

Activity# 02

• Write Verilog code in behavioral modeling for 4-bit synchronous counter.


• Write Stimulus module to verify your counter design. Stimulus module should give
clock input and reset input to counter and display corresponding outputs using
$monitor.
• Compile and run the simulation in ModelSim and display counter output waveform

Activity# 03

• Below is Circuit diagram of an Arithmetic Logic Unit (ALU) that operates on 16-
bit input data

Figure 21. Arithmetic Logic Unit (ALU)

Department of Electrical and Computer Engineering 39


Design Lab # 3
Lab Report
Student Name:_____________________ Reg. #________________

Answer the following :-

1. Explain objective of the Lab and outline the Lab tasks

2. Explain functionality of each Task implemented in the Lab

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3. Why behavioral modeling is preferred over gate level and dataflow modeling?

4. What is RTL Level Verilog Code?

5. What is the difference between blocking and non-blocking assignments?

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Lab Exercise and Summary

Summary should cover Introduction, Procedure, Data Analysis and Evaluation.

Department of Electrical and Computer Engineering 42


Student’s Signature: ________________ Date: ________________

Department of Electrical and Computer Engineering 43


LABORATORY SKILLS ASSESSMENT (Psychomotor)
Total Marks: 100

Criteria Level 1 Level 2 Level 3 Level 4 Score


(Max Marks) 0% ≤ S < 50% 50% ≤ S< 70% 70% ≤ S< 90% 90%≤ S ≤100% (S)
Procedural Selects Selects and applies Selects and applies Selects and
Awareness inappropriate appropriate skills the appropriate applies
(20) skills and/or and/or strategies strategies and/or appropriate
strategies required by the skills specific to the strategies and/or
required by the task with some task without skills specific to
task errors significant errors the task without
any error
Practical Makes several Makes few critical Makes some non- Applies the
Implementation critical errors in errors in applying critical errors in procedural
(30) applying procedural applying procedural knowledge in
procedural knowledge knowledge perfect ways
knowledge
Safety Requires constant Requires some Follows safety Routinely follows
(10) reminders to reminders to follow procedures with safety procedures
follow safety safety procedures only minimal
procedures reminders
Use of Uses tools, Uses tools, Uses tools, Uses tools,
Tool/Equipment equipment and equipment and equipment and equipment and
(20) materials with materials with materials with materials with a
limited some competence considerable high degree of
competence competence competence
Participation Shows little Demonstrates Demonstrates Actively helps to
to Achieve commitment to commitment to commitment to identify group
Group Goals group goals and group goals, but group goals and goals and works
(10) fails to perform has difficulty carries out assigned effectively to
assigned roles performing roles effectively meet them in all
assigned roles roles assumed
Interpersonal Rarely interacts Interacts with other Interacts with all Interacts
Skills in positively within a group members if group members positively with all
Group Work group, even with prompted spontaneously group members
(10) prompting and encourages
such interaction
in others

Marks Obtained

Instructor’s Signature: ________________ Date: ________________

Department of Electrical and Computer Engineering 44


LABORATORY SKILLS ASSESSMENT (Affective)

Total Marks: 40

Criteria (Max. Level 1 Level 2 Level 3 Level 4 Score


Marks) 0% ≤ S < 50% 50% ≤ S < 70% 70% ≤ S < 90% 90% ≤ S ≤ 100% (S)
Introduction Very little Introduction is brief Introduction is nearly Introduction complete
(5) background with some minor complete, missing some and well-written;
information mistakes minor points provides all necessary
provided or background principles
information is for the experiment
incorrect
Procedure Many stages of the Many stages of the The procedure could be The procedure is well
(5) procedure are not procedure are more efficiently designed and all stages
entered on the lab entered on the lab designed but most of the procedure are
report. report. stages of the procedure entered on the lab
are entered on the lab report.
report.
Data Record Data is brief and Data provides some Data is almost complete Data is complete and
(10) missing significant significant but has some minor relevant. Tables with
pieces of information and has mistakes. units are provided.
information. few critical Graphs are labeled. All
mistakes. questions are
answered correctly.
Data Analysis Data are presented Data are presented Data are presented in Data are presented in
(10) in very unclear in ways (charts, ways (charts, tables, ways (charts, tables,
manner. Error tables, graphs) that graphs) that can be graphs) that best
analysis is not are not clear understood and facilitate
included. enough. Error interpreted. Error understanding and
analysis is included. analysis is included. interpretation. Error
analysis is included.
Report Report contains Report is somewhat Report is well organized Report is well
Quality many errors. organized with and cohesive but organized and
(10) some spelling or contains some cohesive and contains
grammatical errors. grammatical errors. no grammatical errors.
Presentation seems
polished.

Marks Obtained
LABORATORY SKILLS ASSESSMENT (Cognitive)

Total Marks: 10
( If any )
Marks Obtained

Instructor’s Signature: ________________ Date: ________________

Department of Electrical and Computer Engineering 45

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