DSD Lab-3
DSD Lab-3
Design Lab # 3
Verilog: Behavioral Modeling
Objective: Lab #3 will familiarize students with Behavioral Modeling of digital
circuits in Verilog Programming Language. Students will also learn about writing
test-benches in Verilog behavioral modeling for digital designs.
12. Write Stimulus module to test the functionality of 4-bit ripple counter
13. Write Design Module and Stimulus for an Arithmetic Logic Unit (ALU) in
Verilog
Complete your Lab Assignments in Lab and show the results to Lab Instructor.
3 Lab Assignment
(a). Create a new ModelSim project. Project will simulate a 8 to 1 MUX Module
(b). Add new file of type Verilog to the project. Write Verilog module for 8 to 1 MUX in Verilog
Behavioral Modeling using ‘Case Statement’.
(c). Add new file of type Verilog to the same project. Write Stimulus module for testing and
verification of 8 to 1 MUX in the file. Stimulus module should instantiate the 8 to 1 MUX
module.
(d). Compile the project and correct any syntax errors. Next simulate the project and display
results in output window. Also verify timing waveform of output
(a). Create a new ModelSim project. Project will simulate a 4-bit synchronous counter Module in
behavioral Modeling
(b). Add new file of type Verilog to the project. Write Verilog module for 4-bit synchronous
counter in behavioral modeling in the file.
synchronous counter will work on posedge of clock and will reset on negedge of reset signal
(active low reset).
(c). Add new file of type Verilog to the same project. Write Stimulus module for testing and
verification of 4-bit synchronous counter in the file. Stimulus module should instantiate the 4-
bit synchronous counter module.
Generate Clock signal and active low Reset signal in the stimulus module and input them to the
Counter module.
Use the $monitor to display all inputs and outputs of the 4-bit synchronous counter module.
(d). Compile the project and correct any syntax errors. Next simulate the project and display
results in output window. Also display counter module waveforms in waveform window.
Lab Assignments
Activity# 01
• Create a new project in ModelSim, add the files containing 8 to 1 MUX module and
Stimulus module to the project
• Compile and run the simulation of 8 to 1 MUX in ModelSim
• Display inputs and outputs of 8 to 1 MUX using $monitor. Also show timing waveforms
to Lab Instructor
Activity# 02
Activity# 03
• Below is Circuit diagram of an Arithmetic Logic Unit (ALU) that operates on 16-
bit input data
Marks Obtained
Total Marks: 40
Marks Obtained
LABORATORY SKILLS ASSESSMENT (Cognitive)
Total Marks: 10
( If any )
Marks Obtained