Qiskit Global Summer School 2024

Quantum Circuit
Compilation with
Qiskit
Matthew Treinish
Senior Software Engineer
IBM
Note on terminology
– In Qiskit the quantum circuit compiler is called the "transpiler"

– This is a historical name and doesn't accurately represent its capabilities or function

– Typically, when you look up the term "transpiler" it refers to a source-to-source compiler. Such
as a compiler that translates Python to Rust.

– I'll use "compile"/"compiler" and "transpile"/"transpiler" interchangeably during this

lecture; I'm referring to the same thing.

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Why do we need quantum
circuit compilation?
– Despite programming at a low level there is still abstractions in our
representation that can't be executed by hardware

– There are numerous constraints with hardware that need to be accounted for

– The compiler's job is to take the high-level abstract circuit and output an
optimized circuit that is capable of running on a given quantum computer

Bernstein Vazirani Circuit

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Why do we need quantum
circuit compilation?
Bad compilation:

Good compilation:

Better compilation:

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Why do we need quantum
circuit compilation?

Bad compilation: Good compilation: Better compilation:

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Modelling
Hardware
constraints

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Operations Operations supported on different generations
Each Quantum Computer only supports a set of operations of IBM Hardware:

Typically, hardware supports a universal gate set that can be

used to construct any unitary operation IBM Heron Systems:
CZ, Rz, sqrt(X) , X
All qubits do not necessarily need to support the same set of
operations.
IBM Eagle Systems:
the saying that many quantum computers have a global set of ECR, Rz, sqrt(X) , X
operations across all hardware is not true and that is a constraint

IBM Falcon Systems(retired):

ECR, CX, Rz, sqrt(X) , X

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Qubit connectivity IBM Yorktown 5 qubits

– Qubits may have limited connectivity

– For IBM's super conducting hardware this is limited

to qubits that have physical connectivity.

– For multi-qubit gates this means we can only run

these operations where there is connectivity
between qubits.

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Qubit connectivity IBM Rochester (retired) 53 qubits

– Qubits may have limited connectivity

– For IBM's super conducting hardware this is limited

to qubits that have physical connectivity.

– For multi-qubit gates this means we can only run

these operations where there is connectivity
between qubits.

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Qubit connectivity IBM Torino 133 qubits

– Qubits may have limited connectivity

– For IBM's super conducting hardware this is limited

to qubits that have physical connectivity.

– For multi-qubit gates this means we can only run

these operations where there is connectivity
between qubits.

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Not enough Connectivity

– Connectivity is not always sufficient to fully map the

abstract circuit

– The compiler will use SWAP gates (or other

techniques) to move state between qubits

– This is potentially expensive to do, so the compiler's

job is to minimize this as much as it can

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Not enough Connectivity

– Connectivity is not always sufficient to fully map the

abstract circuit

– The compiler will use SWAP gates (or other

techniques) to move state between qubits

– This is potentially expensive to do, so the compiler's

job is to minimize this as much as it can

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Not enough Connectivity

– Connectivity is not always sufficient to fully map the

abstract circuit

– The compiler will use SWAP gates (or other

techniques) to move state between qubits

– This is potentially expensive to do, so the compiler's

job is to minimize this as much as it can
≡

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Noise

Every operation is a potential source of noise or errors

– Gate Errors

o Single qubit Errors

individual gate error rates
o Multiqubit Errors

– Decoherence
• T1: Energy Relaxation, the time for a qubit at |1⟩
to decay to ground state |0⟩
• T2: dephasing of a qubit in superposition state
decoherence is the measure of how long a
– Readout Error quantum state can be maintained
error during measuring

transpiler's job is to minimise error rate and increase fidelity; creates a

representation of the circuit that can be executed on the hardware with
the least amount of operations
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Target print(backend.target)

Target
Number of qubits: 5

– The constraints of a given compilation target is Instructions:

cx

modeled by the `Target` class in Qiskit.

(0, 1):
Duration: 4.124444444444444e-07 sec.
Error Rate: 0.011112942844963669
With pulse schedule calibration
(1, 0):

– The target contains a list of every instruction Duration: 3.7688888888888884e-07 sec.

Error Rate: 0.011112942844963669
With pulse schedule calibration

(operation/gate on qubits), the properties (1, 2):

Duration: 2.702222222222222e-07 sec.

associated with those instructions. Typically error

Error Rate: 0.007959389035724018
With pulse schedule calibration
(2, 1):

rate, duration, and a pulse calibration. Duration: 3.0577777777777775e-07 sec.

Error Rate: 0.007959389035724018
With pulse schedule calibration
(2, 3):
Duration: 2.8444444444444443e-07 sec.
– Additional properties about qubits and other device Error Rate: 0.025418806013513956
With pulse schedule calibration

characteristics use for compilation are contained

(3, 2):
Duration: 3.2e-07 sec.
Error Rate: 0.025418806013513956

within the target. (3, 4):

With pulse schedule calibration

Duration: 4.195555555555555e-07 sec.

Error Rate: 0.018081475298807576
With pulse schedule calibration
(4, 3):
Duration: 3.84e-07 sec.
Error Rate: 0.018081475298807576
With pulse schedule calibration

https://docs.quantum.ibm.com/api/qiskit/qiskit.transp sx
(0,):
Duration: 3.5555555555555554e-08 sec.

iler.Target Error Rate: 0.00037753800551696055

With pulse schedule calibration

Target ia a collection of all constraints

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Transpiler
Internals

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DAG Representation

Inside the transpiler Qiskit represents the circuit as a

Directed Acyclic Graph (DAG). The graph tracks the flow of
data from the start of the circuit with input nodes (green in
the visualization) through operations (blue in the
visualization) to output nodes that represent the end of the
circuit (red in the visualization). The edges are used to track
bits, both quantum and classical, in addition to other
classical variables.

This representation makes it simpler to do analysis of the

circuit and see dependency between operations. It also
makes doing in place mutation and substitution of
operations simpler.

the transpiler represents its circuit using the DAG representation

- Helps to track data flow from a qubit until we reach the output node
- Pass Manager is a way of scheduling execution of passes
- Transpiler is built up of Passes that operate on these DAGs; Pass
Managers job is to schedule these passes

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Qiskit Global Summer School 2024
Pass Manager Stages Pass Manager Stages
Qiskit's compilation pipeline is broken up into discrete – Init stage: Initial passes that operate on abstract
stages. These stages execute linearly, and each perform a
logical transformation as we progressively transform the circuit. This stage is responsible for any logical
circuit towards an output that's optimized for execution on a optimizations and decomposing larger gates into
given target. By default, Qiskit uses 6 stages for its preset terms of 1 and 2 qubit gates to enable the next
pass managers but if you're constructing a pass manager stage.
manually you can create your own stages.
– Layout stage: The stage responsible for mapping
https://docs.quantum.ibm.com/transpile/transpiler-stages circuit qubits to qubits in the target.

– Routing stage: This stage makes up for a lack of

connectivity and inserts Swap gates or other
these are default stages and we can create as many stages
as we want with whatever names we want when building our
operations to move state between qubits.
circuit manually
– Translation stage: This stage is responsible for
transforming all circuit operations into ones
supported by the target.
each of these stages can use repititive pass managers to
continue performing the same operation over and over again until – Optimization stage: This stage is responsible for
the desired result is achieved
performing any optimizations, especially after
earlier stages likely inserted extra operations.

– Scheduling stage: The final optional stage is for any

Qiskit Global Summer School 2024
scheduling of the circuit to account for the timing of 19

operations in the circuit.

Pass Manager Pluggability pip install qiskit-qubit-reuse
The pass managers are pluggable and extensible so that you
can replace the implementation of just a stage on the fly.
You can build a custom PassManager object and substitute it
for a stage or modify a stage in place. This lets you reuse a
prebuilt pipeline and customize a small component

You can install/publish external Python packages that

advertise

https://docs.quantum.ibm.com/transpile/transpiler-plugins

transpile(qc, backend, init_method="qubit_reuse")

or
pm = generate_preset_pass_manager(2, backend, init_method="qubit_reuse")
pm.run(qc)

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Preset Pass
Managers

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Init stage
– Stage is broken into two phases:

o Decompose larger (>=3 qubit) gates to 1 and 2 qubit gates

o Logical optimizations

– At the end of the stage, we are able to run layout (which models the circuit as
a graph)

logical optimisations

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Init stage
– Stage is broken into two phases:

o Decompose larger (>=3 qubit) gates to 1 and 2 qubit gates

o Logical optimizations Logical optimisations are optimisations done before we have any idea about the hardware

– At the end of the stage, we are able to run layout (which models the circuit as
a graph)

pick best layouts that use best qubits and finally, have minimum usage of
SWAP gates

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Layout stage
– This stage takes the virtual qubits from abstract circuit and maps them to a
qubit as defined in the target

– Layout is of critical importance because not all qubits perform the same.

– This stage typically tries multiple techniques to find the best layout. In Qiskit
we use two passes by default: VF2Layout and Sabre

– A poor layout can induce more Swaps because of the connectivity

Layout takes circuit connections and represents as a

graph

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Layout stage

we have reordered qubits and we have assigned them each a target from
which they have been connected

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VF2Layout iterates over the circuit and builds 2 qubit interactions and builds a graph

This pass creates a graph from the 2 qubit interactions in the

circuit and tries to find an isomorphic subgraph of the
connectivity graph of the target. If a subgraph is found than Interaction Graph Connectivity Graph
that indicates a layout which does not require swaps can be
used. If a layout is found, then the pass will search for
additional layouts and pick the one with the lowest predicted
error rate.

It leverages the rustworkx's library's VF2 algorithm

implementation to efficiently search for an isomorphism.

https://docs.quantum.ibm.com/api/qiskit/qiskit.transpiler.pa
sses.VF2Layout represents 2 qubit operations

this pass tries to match the interaction graph to the connectivity graph
which is a computationally hard problem to solve. This is where rustworkx
comes in as it hs the features to implement this job

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Sabre
If VF2Layout does not find a layout then we run
SabreLayout pass. This pass is based on the SABRE
(SWAP-based BidiREctional) algorithm originally detailed in:
https://arxiv.org/pdf/1809.02573.pdf.

The SABRE algorithm works by starting with an initial

random guess, then running a routing algorithm on it to
insert swap gates and instead of inserting a swap it swaps
the qubits in the layout. It fully "routes" the circuit then
reverses the edge direction in the dag and repeats. This is
performed multiple times, doing this will minimize the
number of swaps needed.

The implementation in Qiskit has significantly changed and

improved on the algorithm from the original paper.

https://docs.quantum.ibm.com/api/qiskit/qiskit.transpiler.passes.SabreLayout

- heuristic pass that picks a layer that will have the lowest use of number of
SWAP gates
- starts with a bunch of random starting points; each starting point
produces a different mapping for each one of these; picks the one which
produces the lowest no. of SWAP gates

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Sabre
If VF2Layout does not find a layout then we run
SabreLayout pass. This pass is based on the SABRE
(SWAP-based BidiREctional) algorithm originally detailed in:
https://arxiv.org/pdf/1809.02573.pdf.

The SABRE algorithm works by starting with an initial

random guess, then running a routing algorithm on it to
insert swap gates and instead of inserting a swap it swaps
the qubits in the layout. It fully "routes" the circuit then
reverses the edge direction in the dag and repeats. This is
performed multiple times, doing this will minimize the
number of swaps needed.

The implementation in Qiskit has significantly changed and

improved on the algorithm from the original paper.

https://docs.quantum.ibm.com/api/qiskit/qiskit.transpiler.passes.SabreLayout

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Routing stage
– This stage takes the circuit with a layout set and inserts Swap gates where
necessary. This is used to insert SWAP gates to build
connectivity for the qubits that are not
– The default pass for this is SabreSwap. connected

– If running with defaults however this pass is skipped for efficiency, and it's
run as part of SabreLayout in the Layout stage.

– We re-run layout with VF2PostLayout after swap insertion to search for a

better layout

In case we perform custoom operations like

changing the layout in this stage, SabreSwap
executes at the end to ensure that the circuit is
ready to execute

this pass stage is made up of if-els statements

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VF2PostLayout

Just as with VF2Layout this pass creates a graph from the 2

qubit interactions in the circuit and tries to find an
isomorphic subgraph of the connectivity graph of the target. Interaction Graph Connectivity Graph
The difference is by running after routing we know that there
is at least one isomorphic subgraph. This pass then searches
for other layouts and picks the one found with the lowest
predicted error rate.

https://journals.aps.org/prxquantum/abstract/10.1103/PRXQuantum.4.010327

https://docs.quantum.ibm.com/api/qiskit/qiskit.transpiler.passes.VF2PostLayout

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VF2PostLayout

Just as with VF2Layout this pass creates a graph from the 2

qubit interactions in the circuit and tries to find an
isomorphic subgraph of the connectivity graph of the target.
The difference is by running after routing we know that there
is at least one isomorphic subgraph. This pass then searches
for other layouts and picks the one found with the lowest
predicted error rate.

https://journals.aps.org/prxquantum/abstract/10.1103/PRXQuantum.4.010327

https://docs.quantum.ibm.com/api/qiskit/qiskit.transpiler.passes.VF2PostLayout

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Translation stage
• This stage takes the routed circuit which meets the connectivity constraints
of the target and is responsible for making sure that all the operations are
supported on the target

• This stage runs the same passes we used in the first phase of the init stage
but for all operations instead of just those with >= 3 qubits

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Basis Translator Does bulk of the translation

– The basis translator uses an equivalence library that builds a

graph of equivalent circuits to a gate

– Dijkstra's algorithm is used to find a path from a given gate to

gates in the target

– The gates in the circuits are recursively substituted along the

path to build an equivalent circuit that conforms to the target

– Each gate is then replaced in the DAG by that equivalent circuit

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Basis Translator
– The basis translator uses an equivalence library that builds a
graph of equivalent circuits to a gate

– Dijkstra's algorithm is used to find a path from a given gate to

gates in the target

– The gates in the circuits are recursively substituted along the

path to build an equivalent circuit that conforms to the target

– Each gate is then replaced in the DAG by that equivalent circuit

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Basis Translator

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Optimization stage
– This stage takes the mapped circuit and optimizes it to reduce unnecessary
operations

– This stage runs in a loop to repeatedly run the optimization passes until a
minimum point in depth and size is found

up until Translation
stage, we have circuit
that could be executed
on hardware; all the
constraints have been
made up for; but this
will not give a good
result; thus we have
this stage to optimise
the circuit by reducing
the no. of operations

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1 Qubit Unitary Peephole Optimization
– This pass looks for sequences of single qubit gates

- produces same end state with fewer gates

- single qubit simulation to build the unitary matrix representation of operation at the endo of the sequence and then synthesising to the
target basis state and we do it using fewer operations

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1 Qubit Unitary Peephole Optimization

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2 Qubit Unitary Peephole Optimization
- DAG representation is very powerful

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Commutative Cancellation
2 gates that commute; if we reorder the gate then they will perform the same operations
without depending upon the order of their representation

Examples of commuting gates:

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Scheduling stage
• This stage takes the mapped and optimized circuit and analyzes the runtime
of the operations in the circuit and identify idle periods on each qubit

• It will then insert explicit operations to account for all the time in the circuit

- Delay Gates
- Dynamic Decoupling: where we insert gates to supress them and reduce errors

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Scheduling stage
• This stage takes the mapped and optimized circuit and analyzes the runtime
of the operations in the circuit and identify idle periods on each qubit

• It will then insert explicit operations to account for all the time in the circuit

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