MICROCONTROLLERS:

3.1 Features
• Compatible with MCS®-51Products
• 2K Bytes of Reprogrammable Flash Memory – Endurance: 10,000 Write/Erase Cycles
• 2.7V to 6V Operating Range
• Fully Static Operation: 0 Hz to 24 MHz
• Two-level Program Memory Lock
• 128 x 8-bit Internal RAM
• 15 Programmable I/O Lines
• Two 16-bit Timer/Counters
• Six Interrupt Sources
• Programmable Serial UART Channel
• Direct LED Drive Outputs
• On-chip Analog Comparator
• Low-power Idle and Power-down Modes
• Green (Pb/Halide-free) Packaging Option

3.1.2 Description

The AT89C2051 is a low-voltage, high-performance CMOS 8-bit microcomputer with

2K bytes of Flash programmable and erasable read-only memory (PEROM). The device
is manufactured using Atmel’s high-density nonvolatile memory technology and is
compatible with the industry-standard MCS-51 instruction set. By combining a versatile
8-bit CPU with Flash on a monolithic chip, the Atmel AT89C2051 is a powerful
microcomputer which provides a highly-flexible and cost-effective solution to many
embedded control applications.

The AT89C2051 provides the following standard features: 2K bytes of Flash, 128 bytes
of RAM, 15 I/O lines, two 16-bit timer/counters, a five vector two-level interrupt
architecture, a full duplex serial port, a precision analog comparator, on-chip oscillator
and clock circuitry. In addition, the AT89C2051 is designed with static logic for
operation down to zero frequency and supports two software selectable power saving
modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial
port and interrupt system to continue functioning. The power-down mode saves the RAM
contents but freezes the oscillator disabling all other chip functions until the next
hardware reset.

Fig 3.2: Pin diagram

Fig 3.3: Block diagram
3.1.3 Pin Description

1. VCC
Supply voltage.

2. GND
Ground.

3. Port 1
The Port 1 is an 8-bit bi-directional I/O port. Port pins P1.2 to P1.7 provide internal pull
ups. P1.0 and P1.1 require external pull-ups. P1.0 and P1.1 also serve as the positive
input (AIN0) and the negative input (AIN1), respectively, of the on-chip precision analog
comparator. The Port 1 out-put buffers can sink 20 mA and can drive LED displays
directly. When 1s are written to Port 1 pins, they can be used as inputs. When pins P1.2
to P1.7 are used as inputs and are externally pulled low, they will source current (IIL)
because of the internal pull-ups. Port 1 also receives code data during Flash programming
and verification.

4. Port 3
Port 3 pins P3.0 to P3.5, P3.7 are seven bi-directional I/O pins with internal pull-ups.
P3.6 is hard-wired as an input to the output of the on-chip comparator and is not
accessible as a general purpose I/O pin. The Port 3 output buffers can sink 20 mA. When
1s are written to Port 3 pins they are pulled high by the internal pull-ups and can be used
as inputs. As inputs, Port 3 pins that are externally being pulled low will source current
(IIL) because of the pull-ups. Port 3 also serves the functions of various special features
of the AT89C2051.
 Fig 3.4: Figure showing the alternate functions of Port P3

Port 3 also receives some control signals for Flash programming and verification.

5. RST Reset input All I/O pins are reset to 1s as soon as RST goes high. Holding the
RST pin high for two machine cycles while the oscillator is running resets the device.
Each machine cycle takes 12 oscillator or clock cycles.

6. XTAL1 Input to the inverting oscillator amplifier and input to the internal clock
operating circuit.

7. XTAL2 Output from the inverting oscillator amplifier.

Oscillator Characteristics
The XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier
which can be configured for use as an on-chip oscillator, as shown in Fig 5.1. Either a
quartz crystal or ceramic resonator may be used. To drive the device from an external
clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Fig
5.2. There are no requirements on the duty cycle of the external clock signal, since the
input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum
and maximum voltage high and low time specifications must be observed.
Fig 5.1. Oscillator Connections
Note: C1, C2 = 30 pF ± 10 pF for Crystals
= 40 pF ± 10 pF for Ceramic Resonators

Fig 5.2. External Clock Drive Configuration

Special Function Registers

A map of the on-chip memory area called the Special Function Register (SFR) space is
shown in the table below. Note that not all of the addresses are occupied, and unoccupied
addresses may not be implemented on the chip. Read accesses to these addresses will in
general return random data, and write accesses will have an indeterminate effect. User
software should not write 1s to these unlisted locations, since they may be used in future
products to invoke new features. In that case, the reset or inactive values of the new bits
will always be 0.
 Table 3.1. AT89C2051 SFR Map and Reset Values

Restrictions on Certain Instructions

The AT89C2051 and is an economical and cost-effective member of Atmel’s growing
family of microcontrollers. It contains 2K bytes of Flash program memory. It is fully
compatible with the MCS-51 architecture, and can be programmed using the MCS-51
instruction set. However, there are a few considerations one must keep in mind when
utilizing certain instructions to pro-gram this device. All the instructions related to
jumping or branching should be restricted such that the destination address falls within
the physical program memory space of the device, which is 2K for the AT89C2051. This
should be the responsibility of the software programmer. For example, LJMP 7E0H
would be a valid instruction for the AT89C2051 (with 2K of memory), whereas LJMP
900H would not.

Branching Instructions
LCALL, LJMP, ACALL, AJMP, SJMP, JMP @A+DPTR – These unconditional
branching instructions will execute correctly as long as the programmer keeps in mind
that the destination branching address must fall within the physical boundaries of the
program memory size (locations 00H to 7FFH for the 89C2051). Violating the physical
space limits may cause unknown program behavior.

CJNE [...], DJNZ [...], JB, JNB, JC, JNC, JBC, JZ, JNZ – With these conditional
branching instructions the same rule above applies. Again, violating the memory
boundaries may cause erratic execution. For applications involving interrupts the normal
interrupt service routine address locations of the 80C51 family architecture have been
preserved.

MOVX-related Instructions, Data Memory

The AT89C2051 contains 128 bytes of internal data memory. Thus, in the AT89C2051
the stack depth is limited to 128 bytes, the amount of available RAM. External DATA
memory access is not supported in this device, nor is external PROGRAM memory
execution. Therefore, no MOVX [...] instructions should be included in the program. A
typical 80C51 assembler will still assemble instructions, even if they are written in
violation of the restrictions mentioned above. It is the responsibility of the controller user
to know the physical features and limitations of the device being used and adjust the
instructions used correspondingly.

Program Memory Lock Bits

On the chip are two lock bits which can be left unprogrammed (U) or can be programmed
(P) to obtain the additional features listed in the Table 3.2
 Table 3.2: Lock Bit Protection Modes

Idle Mode
In idle mode, the CPU puts itself to sleep while all the on-chip peripherals remain active.
The mode is invoked by software. The content of the on-chip RAM and all the special
functions registers remain unchanged during this mode. The idle mode can be terminated
by any enabled interrupt or by a hardware reset. The P1.0 and P1.1 should be set to “0” if
no external pull-ups are used, or set to “1” if external pull-ups are used. It should be
noted that when idle is terminated by a hardware reset, the device normally resumes
program execution, from where it left off, up to two machine cycles before the internal
reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this
event, but access to the port pins is not inhibited. To eliminate the possibility of an
unexpected write to a port pin when Idle is terminated by reset, the instruction following
the one that invokes Idle should not be one that writes to a port pin or to external
memory.

Power-down Mode
In the power-down mode the oscillator is stopped, and the instruction that invokes power
down is the last instruction executed. The on-chip RAM and Special Function Registers
retain their values until the power-down mode is terminated. The only exit from power-
down is a hardware reset. Reset redefines the SFRs but does not change the on-chip
RAM. The reset should not be activated before VCC is restored to its normal operating
level and must be held active long enough to allow the oscillator to restart and stabilize.
The P1.0 and P1.1 should be set to “0” if no external pull ups are used, or set to “1” if
external pull-ups are used.
Programming the Flash
The AT89C2051 is shipped with the 2K bytes of on-chip PEROM code memory array in
the erased state (i.e., contents = FFH) and ready to be programmed. The code memory
array is programmed one byte at a time. Once the array is programmed, to re-program
any non-blank byte, the entire memory array needs to be erased electrically.

Internal Address Counter: The AT89C2051 contains an internal PEROM address

counter which is always reset to 000H on the rising edge of RST and is advanced by
applying a positive going pulse to pin XTAL1.

Programming Algorithm:

To program the AT89C2051, the following sequence is recommended.

1. Power-up sequence: Apply power between VCC and GND pins Set RST and XTAL1
to GND
2. Set pin RST to “H” Set pin P3.2 to “H”
3. Apply the appropriate combination of “H” or “L” logic levels to pins P3.3, P3.4,
P3.5and P3.7 to select one of the programming operations shown in the PEROM
Programming Modes table.

To Program and Verify the Array:

4. Apply data for Code byte at location 000H to P1.0 to P1.7.

5. Raise RST to 12V to enable programming.
6. Pulse P3.2 once to program a byte in the PEROM array or the lock bits. The byte-write
cycle is self-timed and typically takes 1.2 ms.
7. To verify the programmed data, lower RST from 12V to logic “H” level and set pins
P3.3 to P3.7 to the appropriate levels. Output data can be read at the port P1 pins.
8. To program a byte at the next address location, pulse XTAL1 pin once to advance the
internal address counter. Apply new data to the port P1 pins.
9. Repeat steps 6 through 8, changing data and advancing the address counter for the
entire 2K bytes array or until the end of the object file is reached. 10. Power-off
sequence: set XTAL1 to “L” set RST to “L” Turn VCC power off

Data Polling:
The AT89C2051 features Data Polling to indicate the end of a write cycle. During a write
cycle, an attempted read of the last byte written will result in the complement of the
written data on P1.7. Once the write cycle has been completed, true data is valid on all
outputs and the next cycle may begin. Data Polling may begin any time after a write
cycle has been initiated. Ready/Busy: The Progress of byte programming can also be
monitored by the RDY/BSY output signal. Pin P3.1 is pulled low after P3.2 goes high
during programming to indicate BUSY. P3.1 is pulled high again when programming is
done to indicate READY.

Program Verify:
If lock bits LB1 and LB2 have not been programmed, code data can be read back via the
data lines for verification:

1. Reset the internal address counter to 000H by bringing RST from “L” to “H”.
2. Apply the appropriate control signals for Read Code data and read the output data at
the port P1 pins.
3. Pulse pin XTAL1 once to advance the internal address counter.
4. Read the next code data byte at the port P1 pins.
5. Repeat steps 3 and 4 until the entire array is read. The lock bits cannot be verified
directly. Verification of the lock bits is achieved by observing that their features are
enabled.
Chip Erase:
The entire PEROM array (2K bytes) and the two Lock Bits are erased electrically by
using the proper combination of control signals and by holding P3.2 low for 10 ms. The
code array is written with all “1”s in the Chip Erase operation and must be executed
before any non-blank memory byte can be re-programmed. Reading the Signature Bytes:
The signature bytes are read by the same procedure as a nor-mal verification of locations
000H, 001H, and 002H, except that P3.5 and P3.7 must be pulled to a logic low. The
values returned are as follows. (000H) = 1EH indicates manufactured by Atmel (001H) =
21H indicates 89C2051.

Programming Interface
Every code byte in the Flash array can be written and the entire array can be erased by
using the appropriate combination of control signals. The write operation cycle is self-
timed and once initiated, will automatically time itself to completion. Most major
worldwide programming vendors offer support for the Atmel AT89 microcontroller
series.

Flash Programming modes

Programming the Flash memory

Verifying the flash memory