CMPE361

Computer Organization
Computer Engineering Department
TED University

Digital Building Blocks

 Chapter 5 :: Topics
• Introduction
• Arithmetic Circuits
• Sequential Building Blocks
• Memory Arrays

Chapter 5 <2>
 Introduction
• Digital building blocks:
– Gates, multiplexers, decoders, registers, arithmetic
circuits, counters, memory arrays, logic arrays
– The building blocks are hierarchically assembled
from simpler components such as logic gates,
multiplexers, and decoders.
• Building blocks demonstrate hierarchy,
modularity, and regularity:
– Hierarchy of simpler components
– Well-defined interfaces and functions
– Regular structure easily extends to different sizes
• These building blocks are used to build a
microprocessor
Chapter 5 <3>
 Arithmetic Circuits
• Digital logic perform many arithmetic functions
such as:-
– Addition
– subtraction
– comparison
– Shifts
– Multiplication
– division
• Few of these will be introduced here

Chapter 5 <4>
1-Bit Adders
Half Full
Adder Adder
A B A B

Cout Cout Cin

+ +
S S

A B Cout S Cin A B Cout S

0 0 0 0 0
0 1 0 0 1
1 0 0 1 0
1 1 0 1 1
1 0 0
S = 1 0 1
Cout = 1 1 0
1 1 1

S =
Cout =

Chapter 5 <5>
1-Bit Adders
Half Full
Adder Adder
A B A B

Cout Cout Cin

+ +
S S

A B Cout S Cin A B Cout S

0 0 0 0 0 0 0 0 0
0 1 0 1 0 0 1 0 1
1 0 0 1 0 1 0 0 1
1 1 1 0 0 1 1 1 0
1 0 0 0 1
S = 1 0 1 1 0
Cout = 1 1 0 1 0
1 1 1 1 1

S =
Cout =

Chapter 5 <6>
1-Bit Adders
Half Full
Adder Adder
A B A B

Cout Cout Cin

+ +
S S

A B Cout S Cin A B Cout S

0 0 0 0 0 0 0 0 0
0 1 0 1 0 0 1 0 1
1 0 0 1 0 1 0 0 1
1 1 1 0 0 1 1 1 0
1 0 0 0 1
S =AB 1 0 1 1 0
Cout = AB 1 1 0 1 0
1 1 1 1 1

S = A  B  Cin
Cout = AB + ACin + BCin

Chapter 5 <7>
 Ripple-Carry Adder
• Chain 1-bit adders together
• Carry ripples through entire chain
• Disadvantage: slow

A31 B31 A30 B30 A1 B1 A0 B0

Cout Cin
+ C30 + C29 C1 + C0 +
S31 S30 S1 S0

Chapter 5 <8>
 Multibit Adders (CPAs)
• Types of carry propagate adders (CPAs):
– Ripple-carry (slow) SERIAL
– Carry-lookahead (fast) PARALLEL
– Prefix (faster)
• Carry-lookahead and prefix adders faster for large
adders but require more hardware
Symbol
A B
N N

Cout Cin
+
N
S
Chapter 5 <9>
How come Carry Look-Ahead is Faster?

– Ripple-carry SERIAL
– Carry-lookahead PARALLEL

– How can you make this parallel, C2

needs C1 and vice, versa !!!
Why is This Faster?
•In a Ripple Carry Adder, each full adder must wait for the
previous carry, leading to a worst-case delay of O(n)

•In a Carry Look-Ahead Adder, all carries are computed in parallel

using precomputed expressions, reducing the delay to O(log n).

Chapter 5 <10>
You can compute Carry Bits in Parallel: No need to wait
for previous stage

Chapter 5 <11>
What is the catch? More complex- Need more gates

Gate Count (Hardware Complexity)

The number of logic gates used affects power consumption and area.
Explanation:
•RCA only requires one full adder per bit, making it simple but slow.
•CLA requires additional gates for generate (G), propagate (P),
•and carry computation, leading to more hardware overhead.

Adder Type Number of Gates

Ripple Carry Adder (RCA) O(n) (Simple)
Carry Look-Ahead Adder (CLA) O(n log n) (More Complex)

Chapter 5 <12>
Subtracter

Symbol adders can add positive

and negative numbers
using two’s
A B
N N complement number
representation.
-
N
Y

Chapter 5 <13>
Subtracter

Symbol Implementation
A B
A B flip the N
N N sign of B,
then add N N
-
N +
Y N
Y
Flip: 2’s complement of B (1’s complement + 1)

Chapter 5 <14>
Comparator: Equality

Symbol A comparator
determines
whether two
A B binary numbers are
4 4
equal or if one is
=
greater or less than
Equal the other.

Chapter 5 <15>
Comparator: Equality implementation

Symbol Implementation
A3
B3

A B A2
4 4 B2
Equal
= A1
B1
Equal
A0
B0

Chapter 5 <16>
 Comparator: Less Than
A B compute A − B and
N N look at the sign (most
significant bit) of the
- result.
N If the result is
[N-1]
negative (i.e., the sign
A<B bit is 1), then A is less
than B. Otherwise A
is greater than or
equal to B.
5-<17>
Copyright © 2007 Elsevier
Chapter 5 <17>
ALU-Arithmetic & Logic Unit
• An Arithmetic/Logical Unit (ALU) combines a
variety of mathematical and logical operations
into a single unit.
• For example, a typical ALU might perform
addition, subtraction, magnitude comparison,
AND, and OR operations.
• The ALU forms the heart of most computer
systems.
• In the following table f is the control signal
defining the operation.

Chapter 5 <18>
 Arithmetic Logic Unit (ALU)

F2:0 Function
A B 000 A&B
N N 001 A|B
010 A+B
ALU 3F 011 not used
N 100 A & ~B
Y 101 A | ~B
110 A-B
111 SLT

5-<19>
Copyright © 2007 Elsevier
Chapter 5 <19>
 An ALU Implementation
A B
N N F2:0 Function
000 A&B
N
001 A|B
1

0 F2
N 010 A+B
011 not used
Cout + 100 A & ~B
[N-1] S
101 A | ~B
Extend
Zero

110 A-B
N N N N
1

111 SLT
3

2 F1:0
N
Y
5-<20>
Copyright © 2007 Elsevier
Chapter 5 <20>
 I will demonstrate &, do the rest at home
A
N
B
N For A & B F= 0 0 0
F2 F1 F0
N
1

0 F2 =0 The mux selects input 0, which is B

N

We have A & B here

Cout +
[N-1] S
Extend
Zero

N N N N
1

0
3

2 F1:0= 0 0, mux selects 0, which is the

N output of AND gate. Thus Y=A&B
Y
Chapter 5 <21>
 Set Less Than (SLT) Example
A B
N N
• Configure 32-bit ALU for
SLT operation: A = 25
N
1
and B = 32
0
F2
N • When A<B, Y=1.
Otherwise, Y=0
Cout +
[N-1] S
Extend
Zero

N N N N
1

0
3

2 F1:0
N
Y

5-<22>
Copyright © 2007 Elsevier
Chapter 5 <22>
 Set Less Than (SLT) Example
A B
N N
• Configure 32-bit ALU for SLT
operation: A = 25 and B = 32
N
1 – A < B, so Y should be 32-bit
0
F2 representation of 1
N
(0x00000001)
– F2:0 = 111
Cout + – F2 = 1 (adder acts as
[N-1] S
subtracter), so 25 - 32 = -7
Extend

– -7 has 1 in the most

Zero

N N N N significant bit (S31 = 1)

1

0
3

2 F1:0 – F1:0 = 11 multiplexer selects Y

N = S31 (zero extended) =
Y
0x00000001.
5-<23>
Copyright © 2007 Elsevier
Chapter 5 <23>
 Shifters
• Shifters and rotators move bits and multiply or divide by powers of 2.
• Logical shifter: shifts value to left or right and fills empty spaces
with 0’s
– Ex: 11001 >> 2 =
– Ex: 11001 << 2 =
• Arithmetic shifter: same as logical shifter, but on right shift, fills
empty spaces with the old most significant bit (msb).
– Ex: 11001 >>> 2 =
– Ex: 11001 <<< 2 =
• Rotator: rotates bits in a circle, such that bits shifted off one end
are shifted into the other end
– Ex: 11001 ROR 2 =
– Ex: 11001 ROL 2 =

5-<24>
Copyright © 2007 Elsevier
Chapter 5 <24>
 Shifters
• Logical shifter:
– Ex: 11001 >> 2 = 00110
– Ex: 11001 << 2 = 00100
• Arithmetic shifter:
– Ex: 11001 >>> 2 = 11110
– Ex: 11001 <<< 2 = 00100
• Rotator:
– Ex: 11001 ROR 2 = 01110
– Ex: 11001 ROL 2 = 00111

Chapter 5 <25>
Shifter Design
A 3 A 2 A1 A0 shamt1:0
2
00 S1:0
01

10
Y3

shamt1:0 11

2 00
S1:0
01
Y2
A3:0 4 >> 4 Y3:0
10

11

00
S1:0
01

10
Y1
11

00
S1:0
01

10
Y0
11

Chapter 5 <26>
 Shifters as Multipliers, Dividers

• A << N = A × 2N
– Example: 00001 << 2 = 00100 (1 × 22 = 4)
– Example: 11101 << 2 = 10100 (-3 × 22 = -12)
• A >>> N = A ÷ 2N
– Example: 01000 >>> 2 = 00010 (8 ÷ 22 = 2)
– Example: 10000 >>> 2 = 11100 (-16 ÷ 22 = -4)

Chapter 5 <27>
 Counters
• Increments on each clock edge
• Used to cycle through numbers. For example,
– 000, 001, 010, 011, 100, 101, 110, 111, 000, 001…
• Example uses:
– Digital clock displays
– Program counter: keeps track of current instruction executing

Symbol Implementation
On each cycle, the
counter adds 1 to the CLK
value stored in the N CLK
register. N N
Q

+
Q N N r
1
Reset
Reset

Chapter 5 <28>
 Counters in SystemVerilog
module counter #(parameter N = 8) (input logic clk,
input logic reset, output logic [N–1:0] q);
always_ff @(posedge clk, posedge reset)
if (reset) q <= 0;
else q <= q + 1;
endmodule
always_ff @(posedge clk) begin
a <= b; // Scheduled for update
c <= a; // Uses old 'a' value
End

Difference between = (assignment, immediate - blocking) and

<= gets ( old value – nonblocking)

Chapter 5 <29>
 Shift Registers
• Shift a new bit in on each clock edge
• Shift a bit out on each clock edge
• Serial-to-parallel converter: converts serial input (Sin) to
parallel output (Q0:N-1)

Symbol: Implementation:
CLK
N
Q Sin Sout

Sin Sout
Q0 Q1 Q2 QN-1

Chapter 5 <30>
 Shift Register with Parallel Load
• When Load = 1, acts as a normal N-bit register
• When Load = 0, acts as a shift register
• Now can act as a serial-to-parallel converter (Sin to Q0:N-1) or
a parallel-to-serial converter (D0:N-1 to Sout)

When Load = 1, D1, D2, … Dn-1 is LOADED to registers

D0 D1 D2 DN-1
Load
Clk
Sin 0 0 0 0 Sout
1 1 1 1

Q0 Q1 Q2 QN-1

Chapter 5 <31>
HDL Example: Shift Register with Parallel Load

module shiftreg #(parameter N = 8)

input logic clk,
input logic reset, load,
input logic sin, (serial in)
input logic [N–1:0] d,
output logic [N–1:0] q,
output logic sout);
always_ff @(posedge clk, posedge reset)
if (reset) q <= 0;
else if (load) q <= d;
else q <= {q[N–2:0], sin};
assign sout = q[N–1];
endmodule

Chapter 5 <32>
Memory Arrays: Overview

N
Address Array

Data
Chapter 5 <33>
 Memory Arrays
• Efficiently store large amounts of data
• 3 common types:
– Dynamic random access memory (DRAM), tequires refreshment
– Static random access memory (SRAM), cross-coupled inverters
restore the bit…
– Read only memory (ROM)
• M-bit data value read/ written at each unique N-bit address

N
Address Array

Data
Chapter 5 <34>
 Memory Arrays
• 2-dimensional array of bit cells
• Each bit cell stores one bit
• N address bits and M data bits: Address
N
Array
– 2N rows and M columns
– Depth: number of rows (number of words) M

– Width: number of columns (size of word) Data

– Array size: depth × width = 2N × M

Address Data
11 0 1 0
2
Address Array 10 1 0 0
depth
01 1 1 0
3 00 0 1 1
Data width

Chapter 5 <35>
 Memory Array Example
• 22 × 3-bit array
• Number of words: 4
• Word size: 3-bits
• For example, the 3-bit word stored at address 10 is 100

Address Data
11 0 1 0
2
Address Array 10 1 0 0
depth
01 1 1 0
3 00 0 1 1
Data width

Chapter 5 <36>
Memory Arrays

1024-word x
10
Address 32-bit
Array

32

Data

What is one word ? Word size: 32-bits

Chapter 5 <37>
 Memory Array
Horizontal (connects memory cells in a row)
• Wordline: ROW decoder to select which row of the
– like an enable memory is accessed!
– single row in memory array read/written
– corresponds to unique address
– only one wordline HIGH at once
2:4
Decoder bitline2 bitline1 bitline0
wordline3
11
2 stored stored stored
Address bit = 0 bit = 1 bit = 0
wordline2
10
stored stored stored
wordline1 bit = 1 bit = 0 bit = 0
01
stored stored stored
bit = 1 bit = 1 bit = 0
wordline0
00
stored stored stored
bit = 0 bit = 1 bit = 1

Data2 Data1 Data0

Chapter 5 <38>
 Types of Memory
• Random access memory (RAM): volatile:
DRAM, SRAM
• Read only memory (ROM): nonvolatile

Chapter 5 <39>
SRAM / DRAM

Chapter 5 <40>
 RAM: Random Access Memory
• Volatile: loses its data when power off
• Read and written quickly
• Main memory in computers is mostly RAM
(DRAM)

Historically called random access memory because any data

word accessed as easily as any other (in contrast to
sequential access memories such as a tape recorder)

Chapter 5 <41>
 ROM: Read Only Memory
• Nonvolatile: retains data when power off
• Read quickly, but writing is slow
• Flash memory in cameras, thumb drives, and
digital cameras are all ROMs

Historically called read only memory because ROMs were

written at manufacturing time or by burning fuses. Once
ROM was configured, it could not be written again. This is
no longer the case for Flash memory and other types of
ROMs.

Chapter 5 <42>
 Multi-ported Memories
• Port: address/data pair
• 3-ported memory
– 2 read ports (A1/RD1, A2/RD2)
– 1 write port (A3/WD3, WE3 enables writing)
• Register file: small multi-ported memory
CLK

WE3
A1 RD1
N M
A2 RD2
N M

A3 Array
N
WD3
M

Chapter 5 <43>
 SystemVerilog Memory Arrays
// 256 x 3 memory module with one read/write port
module dmem( input logic clk, we,
input logic [7:0] a,
input logic [2:0] wd,
output logic [2:0] rd);

logic [2:0] RAM[255:0];

assign rd = RAM[a];

always @(posedge clk)

if (we)
RAM[a] <= wd;
endmodule

Chapter 5 <44>