American International University- Bangladesh

Faculty of Science and Technology (FST)

Electronic Devices

Fall 2024-2025

Section: Z, Group: 02

LAB REPORT - 09

Study of JFET and MOSFET Characterization

Supervised By
SADIA YASMIN

Submitted by

Name ID Contribution
1.M.Sakib Sadman Arian 23-54986-3 Abstract, Procedure,
Experimental Data
2. Jarin Tasnim 23-54985-3 Analysis, Simulation
3. Md Tahsin Ur Rahman 23-54884-3 Simulation, Discussion
4. Asmaul Husna 23-54988-3 Theory, Data Table
5. Salman Arefin 22-47262-1 Data Table

Date of Submission : 07 January 2024

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Abstract:
This experiment helps to study the basic principles and characteristics of JFETs (Junction Field Effect
Transistors) and MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). The goal is to
understand their structure, operation, voltage control. By plotting the transfer characteristics of a p-
channel JFET and analyzing the I-V characteristics of MOSFETs helps to understand their behavior in
different operating regions.
The experiment measures the threshold voltage and pinch-off voltage, which are important for
understanding how these transistors work. It also records the gate-to-source voltage and drain current to
show the relationship between input and output. The experiment indicates the differences between JFETs
and MOSFETs. The I-V curves of JFETs and MOSFETs are different because JFETs already have a
channel, and the gate voltage changes its size to control current. In MOSFETs, the channel forms only
when the gate voltage is high enough, called the threshold voltage. This difference in how the channels
work leads to different ways they control current. By studying , the experiment helps understand how
these transistors are used in electronic devices like amplifiers, switches, and circuits.

Theory:
The most common transistor types are the Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) and
the Bipolar Junction Transistors (BJT). BJT-based circuits dominated the electronics market in the 1960s and
1970s. Nowadays, most electronic circuits, particularly integrated circuits (ICs), are made of MOSFETs. The
BJT-based circuits are mainly used for specific applications like analog circuits (e.g., amplifiers), high-speed
circuits, or power electronics.
There are two main differences between BJTs and FETs. The first is that FETs are voltage-controlled devices
while BJTs are current-controlled devices. The second difference is that the input impedance of the FETs is very
high while that of BJT is relatively low. As for the FET transistors, there are two main types: the Junction Field
Effect Transistor (JFET) and the Metal Oxide Semiconductor Field Effect Transistor (MOSFET). The power
dissipation of a JFET is high in comparison to MOSFETs. Therefore, JFETs are less important if it comes to the
realization of ICs, where transistors are densely packed. The power dissipation of a JFET-based circuit would be
very high. The MOSFET became the most popular field effect device in the 1980s.
The combination of n-type and p-type MOSFETs allows for the realization of the Complementary Metal Oxide
Semiconductor (CMOS) devices. CMOS-based technology is the most important technology in the electronics
industry nowadays. All microprocessors and memory products are based on CMOS technology. The very low
power dissipation of CMOS circuits allows for the integration of millions of transistors in a single chip.

JFET Structure and Operation

A transistor is a kind of current-controlled device, and its generating current includes electron flow and hole flow.
The transistor is therefore referred to as a bipolar junction transistor.
FET is a unipolar device, in which the current of n-channel FET is formed by electron flow and the current of p-
channel is formed by hole flow. FET is a kind of voltage-controlled device. FET can also perform the functions
that general transistors (BJT) do, with the only exception that the bias conditions and characteristics are different.
Their applications shall thus be chosen in accordance with related advantages and drawbacks.
The characteristics of FET are listed as follows:
1. FET has a very high input impedance, typically around 100 MΩ.
2. When FET is used as a switch, there is no offset voltage.
3. FET is relatively independent of radiation, whereas BJT is very sensitive to radiation (β varies).
4. The intrinsic noise of FET is lower than that of BJT, which makes FET suitable for the input stage of
low-level amplifiers.
5. During operation the thermal stability of FET is higher than that of BJT.
However, FET also has some drawbacks when compared with BJT, its gain and bandwidth product is smaller,
and it is easier to be damaged by static electricity.
The internal structure of a JFET is shown in Fig. 1. The n-channel JFET is formed by diffusing one pair of p-
type regions into a slab of n-type material as shown in Fig. 1 (a). On the contrary, the p-channel JFET is formed
by diffusing one pair of n-type regions into a slab of p-type material as shown in Fig. 1 (b). The p-channel JFET
is constructed in the same manner as the n-channel device of but with a reversal of the p- and n-type materials.
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 Figure 1: Internal structure of n-channel and p-channel JFETs.

Since the p-channel and n-channel JFETs are constructed by reversing the p- and n-type materials their current
directions are also reversed due to reversal of the actual polarities for the voltages VGS and VDS. For the p-channel
device, the channel will be constricted by increasing positive voltages from gate to source, and the drain-to-source
voltage VDS will result in a negative on the characteristics curve shown in Fig. 3. The curve shows a drain
saturation current (IDSS) of 6 mA and a pinch-off voltage (VP) of +6 V.

Figure 2: JFET symbols: (a) n-channel (b) p-channel

Figure 3: p-channel JFET drain-source characteristics with IDSS = 6 mA and VP = +6 V.

Figure 4 shows the transfer characteristics of a JFET. The curve shows a drain saturation current (IDSS) of 4 mA
and a pinch-off voltage (VP) of +3 V.
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 Figure 4: Transfer characteristics of p-channel JFET with IDSS = 4 mA and VP = +3 V.

MOSFET Structure and Operation

The MOSFETs are the most widely used FETs. Strictly speaking, MOSFET devices belong to the group of
Insulated Gate Field Effect Transistors (IGFETs). As the name implies, the gate is insulated from the channel by
an insulator. In most cases, the insulator is formed by a silicon dioxide (SiO 2) layer, which leads to the term
MOSFET. MOSET, like all other IGFETs, has three terminals, which are called Gate (G), Source (S), and Drain
(D). In certain cases, the transistors have a fourth terminal, which is called the bulk or body terminal (B). In
PMOS, the body terminal is held at the most positive voltage terminal in the circuit, and in NMOS, it is held at
the most negative voltage terminal in the circuit.
There are four types of MOSFETs, such as enhancement mode n-type MOSFET, enhancement mode p-type
MOSFET, depletion mode n-type MOSFET, and depletion mode p-type MOSFET. The type depends on whether
the channel between the drain and source is an induced channel or is a physically implanted one and whether the
current flowing in the channel is an electron current or a hole current. If the channel between the drain and the
source is an induced channel, the transistor is called an enhancement-type transistor. If the channel between the
drain and source is physically implanted, then the transistor is called a depletion-type transistor. If the current
flowing in the channel is an electron current, the transistor is called an n-type MOSFET or NMOS transistor. If
the current flow is a hole current, then the transistor is called a p-type MOSFET or PMOS transistor. Throughout
this laboratory manual, we will concentrate on analyzing the enhancement-type MOSFET. The cross-section of
an enhancement NMOS transistor is shown in Fig. 5.

Figure 5: Schematic cross-section of an enhancement-type NMOS transistor.

If we put the drain and source on ground potential and apply a positive voltage to the gate, the free holes (positive
charges) are repelled from the region of the substrate under the gate (channel region) due to the positive voltage
applied to the gate. The holes are pushed away downwards into the substrate leaving behind a depletion region.

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At the same time, the positive gate voltage attracts electrons into the channel region. When the concentration of
electrons near the surface of the substrate under the gate is equal to or greater than the concentration of holes, an
n-channel is created, connecting the source and the drain regions. This is called enhancement and inversion mode
as it enhances the channel by inverting its type at the surface of the device. The induced n-region thus forms the
channel for current flow from drain to source. The channel is only a few nanometers wide. Nevertheless, the entire
current transport occurs in this thin channel between the drain and the source. Now, if a voltage is applied between
the drain and source electrodes, an electron current can flow through the induced channel. Increasing the voltage
applied to the gate above a certain threshold voltage enhances the channel.
In the case of an enhancement-type NMOS transistor, the threshold voltage is positive, whereas an enhancement-
type PMOS transistor has a negative threshold voltage. So, for the current to flow from drain to source, the
condition that should be satisfied is VGS > Vth, where VGS is the gate-to-source voltage and Vth is the threshold
voltage defined as the minimum voltage required to form a channel between the drain and source regions at the
surface of the device so that carriers can flow through the channel. By changing the applied gate-to-source voltage,
we can modulate the conductance of the channel.
Depletion-type MOSFETs use a different approach. The channel is already conductive for a gate-to-source
voltage of 0 V. Such kind of MOS transistors are realized by the physical implantation of an n-type region between
the drain and the source.

Figure 6: Symbols for enhancement-type NMOS and PMOS transistors.

Figure 7: Drain current, ID vs. gate-to-source voltage, VGS graph of an enhancement type NMOS transistor for a
drain-to-source voltage above the gate overdrive voltage (VGS – Vth) showing threshold voltage Vtn.

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Figure 8: (a) an n-channel enhancement type MOSFET with VGS and VDS applied (b) the IDS – VDS characteristics curve of a
device with 𝑘𝑛′ (𝑊/𝐿) = 1 mA/V2 showing the three operating regions.

Apparatus:
SL# Apparatus Quantity
J176 (p-channel JFET); 2N7000/IRF540N (n-channel enhancement
1 1 each
type MOSFET); 9540 (p-channel enhancement type MOSFET).
2 Resistance (R = 1 k) 1
3 Project Board 1
4 DC Power Supply 1
5 DC milliammeter (0-50 mA) 1
6 DC microammeter (0-500 A) 1
7 Multimeter 1
8 Connecting Leads 10

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Precaution:
1. Transistors should never be removed or inserted into a circuit with voltage applied.
2. Ensure that replacement transistors are oriented in the correct direction within the circuit.
3. Transistors are sensitive to damage caused by electrical overloads, heat, humidity, and radiation. Such
damage often results from incorrect polarity voltage applied to the collector circuit or excessive voltage to the
input circuit.
4. One common cause of transistor damage is electrostatic discharge from human contact during handling.
5. The applied voltage and current must not exceed the transistor's maximum rated specifications.
6. Components or their properties should only be changed after turning off the power or stopping the simulation.
7. Circuit connections should be checked by an instructor after setup, and only sufficient voltage (within VDD)
should be applied to turn on the transistors or chip, preventing potential damage.
8. MOSFET transistors are particularly susceptible to breakdown from electrostatic discharge. It is
recommended to ground yourself before handling a MOSFET chip and to avoid touching its pins.

Experimental Procedures:
A. Transfer Characteristics of p-channel JFET (J176)
1. The actual value of the drain resistor (as the load of Fig. 9) should be measured.
2. The terminals of the transistor should be identified.
3. The circuit should be connected, and the milliammeter should be connected as shown in Fig. 9.
4. A multimeter (in voltmeter mode) should be connected to measure the drain current (IDS) and gate voltage
(VGS).
5. The DC power supply should be turned on with the voltage control knob set to 0 V, and the gate supply voltage
(VGS) should be set to 0 V.
6. The gate-to-source voltage (VGS) and drain-to-source current (IDS) should be measured for a fixed drain-to-
source voltage (VDS = 1 V) by varying the gate-to-source voltage (VG) from 0 V to 12 V in steps of 1 V.
7. The IDS vs. VGS curve should be plotted using the data from Table 1, and the pinch-off voltage (VP) should be
measured.
8. The measured values should be recorded in Table 1.
9. Images of the hardware, simulation circuit diagrams, and various waveforms should be recorded.
10. The DC power supply should be turned off.

Figure 9: Circuit for plotting the IDS vs VGS that is, transfer characteristics of p-channel JFET (J176)

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 Table 1 Measured data of the voltage and current for the transfer characteristic curve of a JFET. Dain- to-
Source voltage, VDS = 1 V.
Gate Voltage, Drain Current, IDS
VG VGS(V) (mA) VR=IDS
0 0.111 0.844 0.844
1 0.681 0.7 0.7
2 1.177 0.191 0.191
3 2.046 0.0003 0.0003
4 2.99 0 0
5 4.02 0 0
6 5 0 0
7 6.02 0 0
8 7 0 0
9 8.04 0 0
10 8.97 0 0
11 9.95 0 0
12 11.02 0 0

B.Output Characteristics of p-channel JFET (J176)

1. The actual value of the drain resistor (as the load of Fig. 9) should be measured.
2. The terminals of the transistor should be identified.
3. The circuit should be connected, and the milliammeter should be connected as shown in Fig. 9.
4. A multimeter (in voltmeter mode) should be connected to measure the drain current (IDS) and drain
voltage (VGS).
5. The DC power supply should be turned on with the voltage control knob set to 0 V, and the gate supply
voltage (VGS) should be set to 2 V.
6. The drain-to-source voltage (VDS) and drain-to-source current (IDS) should be measured for a fixed gate-
to-source voltage (VG = 2 V) by varying the drain-to-source voltage (VDS) from 0 V to 15 V in steps of 1
V.
7. The IDS vs. VDS curve should be plotted using the data from Table 2, and different operating regions
should be indicated.
8. The measured values should be recorded in Table 2.
9. Images of the hardware, simulation circuit diagrams, and various waveforms should be recorded.
10. The DC power supply should be turned off.

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 Table 2 Measured data of the voltage and current for the transfer characteristic curve of a JFET. Gate-
to-Source voltage, VG = 2 V.
Drain Voltage, Drain Current, IDS
Vs VDS(V) (mA) VR=IDS
0 0.0018 0.0024 0.0024
1 0.785 0.806 0.806
2 1.096 0.86 0.86
3 1.298 0.87 0.87
4 1.45 0.874 0.874
5 1.57 0.877 0.877
6 1.59 0.879 0.879
7 1.72 0.882 0.882
8 1.87 0.884 0.884
9 2.046 0.887 0.887
10 2.164 0.89 0.89
11 2.258 0.893 0.893
12 2.338 0.895 0.895
13 2.433 0.898 0.898
14 2.512 0.9 0.9
15 2.576 0.903 0.903

IDS vs. VDS

1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0 0.5 1 1.5 2 2.5 3

C.Transfer Characteristics of n-channel MOSFET (IRF540)

1. The actual value of the drain resistor (as the load of Fig. 10) should be measured.
2. The terminals of the MOS transistor should be identified.
3. The circuit should be connected, and the milliammeter should be connected as shown in Fig. 10.
4. A multimeter (voltmeter mode) should be connected to measure the drain current (IDS) and gate voltage
(VGS).
5. The DC power supply should be turned on with the voltage control knob set to 0 V, and the gate supply
voltage (VGS) should be set to 0 V.
6. The gate-to-source voltage (VGS) and drain-to-source current (IDS) should be measured for a fixed drain-to-
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 source voltage (VDS = 1 V) by varying the gate-to-source voltage (VG) from 0 V to 10 V in steps of 1 V.
7. The IDS vs. VGS curve should be plotted using the data from Table 3, and the pinch-off voltage (VP) should
be measured.
8. The measured values should be recorded in Table 3.
9. Images of the hardware, simulation circuit diagrams, and various waveforms should be recorded.
10. The DC power supply should be turned off.

Figure 10: Circuit for plotting the IDS vs VGS that is, transfer characteristics of n-channel MOSFET (IRF540)

Table 3 Measured data of the voltage and current for the transfer characteristic curve of a MOSFET.
Dain-to-Source voltage, VDS = 1 V.
Gate Voltage, Drain Current, IDS
VG VGS(V) (mA) VR=IDS
0 0.0054 0 0
1 0.941 0 0
2 1.947 0.0003 0.0003
3 2.978 0.665 0.665
4 3.96 1.007 1.007
5 4.95 1.007 1.007
6 5.92 1.007 1.007
7 6.98 1.007 1.007
8 7.97 1.007 1.007
9 8.92 1.007 1.007
10 9.97 1.007 1.007

IDS vs VGS
1.2

0.8

0.6

0.4

0.2

0
0 2 4 6 8 10 12 14

D.Output Characteristics of n-channel MOSFET (IRF540)

1. The actual value of the drain resistor (as the load of Fig. 10) should be measured.
2. The terminals of the MOS transistor should be identified.
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3. The circuit should be connected, and the milliammeter should be connected as shown in Fig. 10.
4. A multimeter (voltmeter mode) should be connected to measure the drain current (IDS) and drain voltage
(VGS).
5. The DC power supply should be turned on with the voltage control knob set to 0 V, and the gate supply
voltage (VGS) should be set to 5 V.
6. The drain-to-source voltage (VDS) and drain-to-source current (IDS) should be measured for a fixed gate-
to-source voltage (VG= 3 V) , varying the drain-to-source voltage (VDS) from 0 V to 15 V in steps of 1 V.
7. The IDS vs. VDS curve should be plotted using the data from Table 4, and different operating regions
should be indicated.
8. The measured values should be recorded in Table 4.
9. Images of the hardware, simulation circuit diagrams, and various waveforms should be recorded.
10. The DC power supply should be turned off.

Table 4 Measured data of the voltage and current for the transfer characteristic curve of a MOSFET.
Gate- to-Source voltage, VG = 3 V.
Drain Voltage, Drain Current, IDS
Vs VDS(V) (mA) VR=IDS
0 0.0011 0.0024 0.0024
1 0.0227 0.806 0.806
2 1.19 0.86 0.86
3 2.141 0.87 0.87
4 3.155 0.874 0.874
5 4.24 0.877 0.877
6 5.23 0.879 0.879
7 6.32 0.882 0.882
8 7.28 0.884 0.884
9 8.17 0.887 0.887
10 9.14 0.89 0.89
11 10.34 0.893 0.893
12 11.28 0.895 0.895
13 12.22 0.898 0.898
14 13.32 0.9 0.9
15 14.24 0.903 0.903

IDS vs. VDS

1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0 2 4 6 8 10 12 14 16

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Simulation & Measurement:

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Page 13 of 14
Discussion & Conclusion:

This experiment explore to study the characteristics of JFETs (Junction Field Effect Transistors) and MOSFETs
(Metal Oxide Semiconductor Field Effect Transistors). By analyzing the transfer characteristics and I-V curves of
both devices, we understand how their gate voltage controls the current flow. The data from the tables shows how the
drain current (IDS) changes with gate voltage (VG) for JFETs and MOSFETs at different drain voltages (VDS).For
the JFET with a VDS of 1V the gate voltage increases, the drain current decreases. At gate voltages (VG > 3V), the
drain current becomes zero, indicating that the JFET is "off." This shows that the JFET's current decreases as the gate
voltage increases. For the MOSFET with a VDS of 1V , the drain current starts at zero and increases as the gate
voltage increases. Once the gate voltage reaches about 3V, the current stabilizes at value, showing the MOSFET is
"on" after this threshold. In conclusion, the JFET shows a decrease in current as the gate voltage increases, while the
MOSFET shows an increase after reaching a threshold.

References:
[1] Robert L. Boylestad, Louis Nashelsky, Electronic Devices and Circuit Theory, 9th Edition, 2007-2008
[2] Adel S. Sedra, Kenneth C. Smith, Microelectronic Circuits, Saunders College Publishing, 3rd ed., ISBN: 0-03-
051648-X, 1991.
[3] American International University–Bangladesh (AIUB) Electronic Devices Lab Manual.
[4] David J. Comer, Donald T. Comer, Fundamentals of Electronic Circuit Design, John Wiley & Sons Canada, Ltd.,
ISBN: 0471410160, 2002.
[5] J. Keown, ORCAD PSpice and Circuit Analysis, Prentice Hall Press (2001)
[6] Resistor values: https://www.eleccircuit.com/how-to-basic-use-resistor/, accessed on 20 September 2023.

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