Marco: Configurable Graph-Based Task Solving and Multi-AI Agents Framework For Hardware Design
Marco: Configurable Graph-Based Task Solving and Multi-AI Agents Framework For Hardware Design
Fig. 1: Graph-Based Task Solving illustration in Marco: Fig. 2: (a) Single-AI/Multi-AI Configurations of Sub-Task
Configurable Graph-Based Task Solving and Multi-AI Agents Node. (b) Agent memory, knowledge database, and tool
Framework. configurations.
Table I: Task graph, agent configuration, customized tool of Marco Framework for various agent implementations for hardware
design tasks. In the last column, X (Supported)=The agent can be configured and implemented using Marco Framework.
V=The agent is implemented on Marco Framework.
Agent Works Task Category Configuration of Marco Framework Original Agent Work
Task Graph Sub-Task Agent Customized Tools Implementation using
Config. Marco Framework
RTLFixer [7] Code Syntax Fixing N/A Single-AI RTL Syntax Error RAG Database (Supported)
Standard Cell Layout Optimization N/A Single-AI Cluster Evaluator, Netlist Traverse Tool (Supported)
Opt. [8]
MCMM Timing Summary & Anomaly Dynamic Multi-AI Timing Distribution Calculator, Timing Metric ✓
Analysis Identification Comparator
(Partition/Block-Level)
DRC Coder [9] Code Generation N/A Multi-Modality Foundry Rule Analysis, Layout DRV Analysis, DRC ✓
& Multi-AI Code Evaluation
Timing Path Debug Summary & Anomaly Static Hierarchical Agentic Timing Report Retrieval ✓
(Path-Level) Identification (Fig. 1 (a) Right) Multi-AI
VerilogCoder [6] Code Generation Dynamic Multi-AI TCRG Retrieval Tool, AST-Based Waveform Tracing ✓
Tool
32% 33.9%
Fig. 3. Verilog syntax fixing and generation performance. Fig. 4. DRC Coder [9]: Performance evaluation of DRC
(a) Syntax pass-rate on VerilogEval-syntax [12] dataset. The code generation using standard prompting and DRC-Coder
LLM used in RTLFixer [7] agent is GPT-3.5. (b) Functional with GPT-4o across seven design rules. We use F1 Score to
pass-rates of recent LLMs and the proposed VerilogCoder [6] evaluate the generated DRC code on DRV detection in an
on VerilogEval-Human v2 [11] dataset. The LLM used in industrial advanced technology node.
VerilogCoder agent is GPT-4 Turbo.
Table II: Pass-rate (%) of Timing Path Debug Agent with static
task graph solving, and a naïve standard task solving without task
graph information. X=failed to solve the task. V=solve the task.
Required Standard Timing
Task ID Multi Report Task Description Analyzed Task Path Debug
Sub-Tasks Solving Agent
Find missing clk signals that have no max, clk
M1 rise/fall information X V
Identify pairs of nets with high RC max, wire
≈ 60× Speedups M2 mismatch X V
Detect unusual constraints between max, xtalk, LC
M3 victim and its aggressors X V
Identify unusual RC values between max, wire,
M4 victim and its aggressors xtalk, LC X V
Find the constraints of slowest max, wire,
Fig. 5. MCMM Timing Analysis Agent: (Top) Task M5 stages with highest RC values xtalk, LC X V
correctness evaluation of 10-point Likert Scale from human Compare each timing table for max
evaluation on 6 timing histogram cases. Here, we omit the number of stages, point values and
M6 timing mismatch X X
details of the 6 tasks due to the tasks are industrial design.
Task M2 and Task M3 for specific max, wire,
(Bottom) MCMM Timing Analysis Agent achieves 60× M7 stages in list of paths xtalk, LC X V
speedups than experienced human engineer. Avg Pass-rate 0% 86%
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