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Marco: Configurable Graph-Based Task Solving and Multi-AI Agents Framework For Hardware Design

The document presents Marco, a unified framework for hardware design that integrates configurable graph-based task solving with multi-AI agents, aimed at addressing the complexities of hardware design and reducing turn-around-time (TAT). It highlights the framework's application in various tasks such as layout optimization, code generation, and timing analysis, showcasing significant performance improvements and efficiency gains. Experimental results demonstrate the effectiveness of LLM-powered agents in achieving high pass rates and speedups in hardware design tasks.

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0% found this document useful (0 votes)
9 views3 pages

Marco: Configurable Graph-Based Task Solving and Multi-AI Agents Framework For Hardware Design

The document presents Marco, a unified framework for hardware design that integrates configurable graph-based task solving with multi-AI agents, aimed at addressing the complexities of hardware design and reducing turn-around-time (TAT). It highlights the framework's application in various tasks such as layout optimization, code generation, and timing analysis, showcasing significant performance improvements and efficiency gains. Experimental results demonstrate the effectiveness of LLM-powered agents in achieving high pass rates and speedups in hardware design tasks.

Uploaded by

khanakmittal92
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We take content rights seriously. If you suspect this is your content, claim it here.
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Marco: Configurable Graph-Based Task Solving and

Multi-AI Agents Framework for Hardware Design


Chia-Tung Ho, Jing Gong, Yunsheng Bai, Chenhui Deng, Haoxing Ren, Brucek Khailany
NVIDIA, Santa Clara, CA
Abstract as shown in Fig. 2(a), and Fig. 2(b). Table 1 summarizes the
Hardware design presents numerous challenges stemming task graph, agent, and LLM configurations of Marco
from its complexity and advancing technologies. These framework for various agents. For specification-to-RTL task,
challenges result in longer turn-around-time (TAT) for VerilogCoder [6] leverages a dynamic task graph for the
optimizing performance, power, area, and cost (PPAC) during proposed novel Task and Circuit Relation Graph-based task
synthesis, verification, physical design, and reliability loops. planner to create a high-quality plan with step-by-step sub-
Large Language Models (LLMs) have shown remarkable tasks and related circuit information (i.e., signal, signal
capacity to comprehend and generate natural language at a transition, and single examples). The novel Abstract Syntax
massive scale, leading to many potential applications and Tree-based waveform tracing tool is developed to assist the
benefits across various domains. Successful LLM-based LLM agent in fixing functional correctness autonomously
agents for hardware design can drastically reduce TAT, with the configuration in Fig. 2(b). MCMM timing analysis
leading to faster product cycles, lower costs, improved design agent utilizes dynamic task graph to create a task flow that
reliability and reduced risk of costly errors. In this work, we analyzing the timing report for each corner and modes, and
propose a unified framework, Marco, that integrates then extract key takeaways across MCMM timing reports. The
configurable graph-based task solving with multi-modality timing path debug agent finds the problematic net, wire, and
and multi-AI agents for chip design by leveraging the natural constraints through static timing debugging task graph as
language and reasoning abilities with collaborative toolkits. shown in Fig. 1. For RTLFixer [7], cell layout optimizer [8],
Lastly, we demonstrate promising performance, productivity, and DRC Coder [9], we employ single-AI or multi-AI agent
and efficiency of LLM agents by leveraging the Marco configurations in Fig. 2(a) with customized tools, memory,
framework on layout optimization, Verilog/design rule and domain knowledge (Fig. 2(b)).
checker (DRC) coding, and timing analysis tasks. Experimental Results
Introduction We demonstrate the performance of agents that are
The exponential growth in the number of transistors within supported or enabled by Marco framework on optimization,
System-on-Chip (SoC) designs has significantly increased the code syntax fixing and generation, and summary and anomaly
complexity of meeting Power, Performance, and Area (PPA) identification task categories in Table 1.
requirements in Very-Large-Scale Integration (VLSI). The Optimization: The cell layout optimizer [8] generates high-
rising complexity and associated costs underline the necessity quality cluster constraints to optimize the cell layout PPA and
to rethink and innovate the EDA processes to accommodate routability with the guidance of designers’ expertise and
the demands of modern chip architectures. Autonomous customized tools. The agent not only achieves up to 19.4%
agents have long been a research focus in academic and smaller cell area, but also generates 23.5% more LVS/DRC
industrial communities across various fields. Recently, AI clean cell layouts than previous work [10] on a set of
agents empowered by LLMs [1]-[3] have shown impressive sequential cells in industrial 2nm technology node.
performance in software engineering for solving real world Code syntax fixing and generation: The RTLFixer [7], and
challenging benchmarks (i.e., SWE-Bench, HumanEval) VerilogCoder [6] achieve 99% syntax pass-rate, and 94.2%
through planning, memory management, actions involving Functional pass-rate on VerilogEval dataset [11] as shown in
external environment tools. In addition to single-AI agents, Fig. 3(a), and Fig. 3(b), respectively. Moreover, Fig. 4 shows
many researchers are starting to explore the capabilities of that DRC Coder [9] achieves perfect F1 score for a set of
multi-AI agents to optimize and verify complex tasks through industrial DRC rules for standard cell layouts in the advanced
collaborative discussions [4], [5]. However, these agent technology node. The generated DRC code is evaluated on
frameworks cannot be directly used for designing hardware hundreds of layouts with various types of DRC violations.
because solving hardware tasks requires integrated domain Summary and Anomaly Identification: The MCMM timing
knowledge and specialized hardware design tools to analyze analysis agent achieves an average score of 8.33 out of 10,
signals, trace signal transitions, and decompose tasks into based on evaluations by experienced engineers on a set of
manageable sub-tasks from circuit architecture and signal industrial cases, and delivers approximately 60X speedups
transaction perspectives. compared to human engineers as shown in Fig. 5. In Table II,
The remaining sections are organized as follows. Firstly, the timing path debug agent resolves 86% of path-level
we introduce the proposed configurable graph-based task debugging tasks, whereas standard task solving approach fails
solving and multi-AI agent framework, where agent works on to resolve any of the tasks.
various types of hardware design tasks. Lastly, we present the Conclusion
performances of the developed agents that are supported or The proposed Marco framework enables more flexible and
enabled by the proposed Macro framework in experimental domain-specialized methods for hardware design tasks. By
results and conclude our work. leveraging task graph and flexible single-AI/multi-AI agent
Marco: Configurable Graph-Based Task Solving and configurations with domain-specific tools and knowledge, we
Multi-AI Agents Framework developed various agents for tasks such as cell layout
The proposed Marco framework, which encompasses optimization, Verilog syntax error fixing, Verilog and DRC
graph-based task solving, agent configurations for sub-tasks, code generation, and timing debugging on problematic blocks,
and skill/tool configurations for each agent. Fig. 1 illustrates nets, and wires. The experimental results show impressive
the dynamic and static configurable graph-based task solving, performance and efficiency benefits on utilizing collaborative
which is flexibly integrated with hardware design knowledge LLM-based agents for hardware design.
(e.g., circuits, timing, etc.). In the task graph, each node Future research directions include: (1) training LLMs with
represents a sub-task, and each edge represents the execution high-quality hardware design data, (2) integrating PPA
or knowledge relationship between nodes. For solving each optimization loops with agentic methodologies, and (3)
sub-task, we leverage Autogen [4] to configure single-AI or developing efficient self-learning techniques and memory
multi-AI agent with knowledge database, tools, and memory systems for complex real-world hardware tasks.
User Query Task Timing Debug Task (b) Sub-Task Node: Agent Config (c) Agent Skill/Capability Config
Wire
Sub-Task 1: Plan LC Sub-Task Sub-Task Memory
Thought: Need Pair of Knowledge DB (Recall)
Thought: Verify plan Logic RC
more knowledge Nets (Retrieve)
Constraints mismatch Agent Agent1
Sub-Task 2: Plan Sub-Task 3: Retrieve Problematic Chat
Verification Related Knowledge Max/Min Agent3 History
Nets
Missing Sub-Task Agent2
Thought: Simulate⋮ the circuit now Aggressors Clocks Answer
Long term
Xtalk Clock Info Multi-AI Agent
Nets memory
Sub-Task N: Simulation Max/Min Clk Single-AI Agent (Discuss, Debate, etc)

Sub-Task Tools, Skills


(ReACT)
Sub-Task k
Group Manager Agent1
SubTask: Dynamically Dynamic execution SubTask: Query Static Relations between
created subtask based order between potential problematic timing reports for issue
subtasks nets, paths, constraints, Agent1 ⋯ Group Manager
on thought or user input. debugging.
from timing reports. Agent2
Multi-AI Agent
(Left: Dynamic task graph, Right: Static task graph) (Hierarchical Collaboration)

Fig. 1: Graph-Based Task Solving illustration in Marco: Fig. 2: (a) Single-AI/Multi-AI Configurations of Sub-Task
Configurable Graph-Based Task Solving and Multi-AI Agents Node. (b) Agent memory, knowledge database, and tool
Framework. configurations.

Table I: Task graph, agent configuration, customized tool of Marco Framework for various agent implementations for hardware
design tasks. In the last column, X (Supported)=The agent can be configured and implemented using Marco Framework.
V=The agent is implemented on Marco Framework.
Agent Works Task Category Configuration of Marco Framework Original Agent Work
Task Graph Sub-Task Agent Customized Tools Implementation using
Config. Marco Framework

RTLFixer [7] Code Syntax Fixing N/A Single-AI RTL Syntax Error RAG Database  (Supported)
Standard Cell Layout Optimization N/A Single-AI Cluster Evaluator, Netlist Traverse Tool  (Supported)
Opt. [8]
MCMM Timing Summary & Anomaly Dynamic Multi-AI Timing Distribution Calculator, Timing Metric ✓
Analysis Identification Comparator
(Partition/Block-Level)
DRC Coder [9] Code Generation N/A Multi-Modality Foundry Rule Analysis, Layout DRV Analysis, DRC ✓
& Multi-AI Code Evaluation
Timing Path Debug Summary & Anomaly Static Hierarchical Agentic Timing Report Retrieval ✓
(Path-Level) Identification (Fig. 1 (a) Right) Multi-AI
VerilogCoder [6] Code Generation Dynamic Multi-AI TCRG Retrieval Tool, AST-Based Waveform Tracing ✓
Tool

(a) RTLFixer [7] (b) VerilogCoder [6]

32% 33.9%

Fig. 3. Verilog syntax fixing and generation performance. Fig. 4. DRC Coder [9]: Performance evaluation of DRC
(a) Syntax pass-rate on VerilogEval-syntax [12] dataset. The code generation using standard prompting and DRC-Coder
LLM used in RTLFixer [7] agent is GPT-3.5. (b) Functional with GPT-4o across seven design rules. We use F1 Score to
pass-rates of recent LLMs and the proposed VerilogCoder [6] evaluate the generated DRC code on DRV detection in an
on VerilogEval-Human v2 [11] dataset. The LLM used in industrial advanced technology node.
VerilogCoder agent is GPT-4 Turbo.
Table II: Pass-rate (%) of Timing Path Debug Agent with static
task graph solving, and a naïve standard task solving without task
graph information. X=failed to solve the task. V=solve the task.
Required Standard Timing
Task ID Multi Report Task Description Analyzed Task Path Debug
Sub-Tasks Solving Agent
Find missing clk signals that have no max, clk
M1 rise/fall information X V
Identify pairs of nets with high RC max, wire
≈ 60× Speedups M2 mismatch X V
Detect unusual constraints between max, xtalk, LC
M3 victim and its aggressors X V
Identify unusual RC values between max, wire,
M4 victim and its aggressors xtalk, LC X V
Find the constraints of slowest max, wire,
Fig. 5. MCMM Timing Analysis Agent: (Top) Task M5 stages with highest RC values xtalk, LC X V
correctness evaluation of 10-point Likert Scale from human Compare each timing table for max
evaluation on 6 timing histogram cases. Here, we omit the number of stages, point values and
M6 timing mismatch X X
details of the 6 tasks due to the tasks are industrial design.
Task M2 and Task M3 for specific max, wire,
(Bottom) MCMM Timing Analysis Agent achieves 60× M7 stages in list of paths xtalk, LC X V
speedups than experienced human engineer. Avg Pass-rate 0% 86%

References
[1] X. Wang, et al. 2024, arXiv preprint arXiv:2407.16741.
[2] J. Yang, et al. 2024, arXiv preprint arXiv:2405.15793.
[3] Dong Huang, et al. 2023, arXiv preprint arXiv:2312.13010.
[4] Qingyun Wu, et al. 2023, arXiv preprint arXiv:2308.08155.
[5] crewAI Inc. 2024, https://github.com/crewAIInc/crewAI.
[6] C.T. Ho, et al. 2024, arXiv preprint arXiv:2408.08927.
[7] Y.D. Tsai, et al. DAC, 2024, pp. 1-6.
[8] C.T. Ho, et al. 2024, arXiv preprint arXiv:2406.06549.
[9] C.C. Chang, et al. 2024, arXiv preprint arXiv:2412.05311.
[10] C.T. Ho, et al. ISPD, 2024, pp. 195–203.
[11] N. Pinckney, et al. 2024, arXiv preprint arXiv:2408.11053.
[12] M.J. Liu, et al. ICCAD, 2023, pp. 1–8.
[13] S. Liu, et al. LAD, 2024, pp. 1-5.
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