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The document discusses various aspects of computer architecture related to RAM and DRAM, including calculations for decoding addresses, determining address pin requirements, and constructing block diagrams. It poses specific problems regarding RAM chip configurations, address calculations, and refresh intervals. The document serves as a guide for understanding memory architecture and design considerations.

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JIMMY y
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81 views1 page

sheet 1

The document discusses various aspects of computer architecture related to RAM and DRAM, including calculations for decoding addresses, determining address pin requirements, and constructing block diagrams. It poses specific problems regarding RAM chip configurations, address calculations, and refresh intervals. The document serves as a guide for understanding memory architecture and design considerations.

Uploaded by

JIMMY y
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Computer Architecture

Sheet # 1
1- A 64K × 16 RAM chip uses coincident decoding by splitting the internal
decoder into row select and column select. (a) Assuming that the RAM cell
array is square, what is the size of each decoder, and how many AND gates
are required for decoding an address? (b) Determine the row and column
selection lines that are enabled when the input address is the binary equivalent
of (32000)10.
2- A DRAM has 15 address pins and its row address is 1 bit longer than its
column address. How many addresses, total, does the DRAM have?
3- A 1 Gb DRAM uses 4-bit data and has equal-length row and column
addresses. How many address pins does the DRAM have?
4- A DRAM has a refresh interval of 128 ms and has 4096 rows. What is the
interval between refreshes for distributed refresh? What is the total time
required out of the 128 ms for a refresh of the entire DRAM? What is the
minimum number of address pins on the DRAM?
5- Using the 64K × 8 RAM chip plus a decoder, construct the block diagram for
a 512K × 16 RAM.

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