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EXPERIMENT NO6 pdf

The document outlines a VHDL program for a 4-bit ripple carry adder, which utilizes four full adders to compute the sum of two 4-bit binary numbers. It includes the structural VHDL code for the adder and a testbench to validate its functionality. Additionally, the document provides the code for the full adder component used in the design.

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4 views

EXPERIMENT NO6 pdf

The document outlines a VHDL program for a 4-bit ripple carry adder, which utilizes four full adders to compute the sum of two 4-bit binary numbers. It includes the structural VHDL code for the adder and a testbench to validate its functionality. Additionally, the document provides the code for the full adder component used in the design.

Uploaded by

Yash
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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EXPERIMENT NO.

: DATE :

4 BIT RIPPLE CARRY ADDER

AIM : VHDL program for 4 bit ripple carry adder

SOFTWARE REQUIRED: ModelSim

THEORY: 4 bit ripple carry adder: A 4-bit ripple carry adder adds two 4-bit binary numbers using four full
adders, where the carry output of each adder feeds into the carry input of the next, starting with a carry-
in of 0.

VHDL CODE WITH TESTBENCH:

Strutural-------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity rcadder is
Port ( A : in STD_LOGIC_VECTOR(3 downto 0);
B : in STD_LOGIC_VECTOR(3 downto 0);
Cin : in STD_LOGIC;
Sum : out STD_LOGIC_VECTOR(3 downto 0);
Cout : out STD_LOGIC);
end rcadder;
architecture Structural of rcadder is
component fulladder_forrc
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
sum : out STD_LOGIC;
carry : out STD_LOGIC);
end component;
signal C : STD_LOGIC_VECTOR(3 downto 0);
begin
RC0: fulladder_forrc port map ( a=>A(0), b=>B(0),c => Cin, sum =>sum(0),carry => C(0));
RC1: fulladder_forrc port map ( a=>A(1), b=>B(1),c=> C(0), sum=> sum(1) , carry=>C(1));
RC2: fulladder_forrc port map ( a=>A(2), b=>B(2),c => C(1), sum=> sum(2) , carry=>C(2));
RC3: fulladder_forrc port map ( a=>A(3), b=>B(3),c => C(2), sum=> sum(3) , carry=>Cout);
end Structural;

testbench------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity tbrcadder1 is
end tbrcadder1 ;
architecture abd of tbrcadder1 is
signal A : STD_LOGIC_VECTOR(3 downto 0);
signal B : STD_LOGIC_VECTOR(3 downto 0);
signal Cin : STD_LOGIC;
signal Sum : STD_LOGIC_VECTOR(3 downto 0);
signal Cout : STD_LOGIC;
component rcadder
Port ( A : in STD_LOGIC_VECTOR(3 downto 0);
B : in STD_LOGIC_VECTOR(3 downto 0);
Cin : in STD_LOGIC;
Sum : out STD_LOGIC_VECTOR(3 downto 0);
Cout : out STD_LOGIC);
end component;
begin
IT: rcadder
Port map ( A => A, B => B, Cin => Cin,
Sum => Sum, Cout => Cout);
process
begin
A <= "0001"; B <= "0011"; Cin <= '0';
wait for 10 ns;
A <= "1010"; B <= "0101"; Cin <= '0';
wait for 10 ns;
end process;
end abd;
code for fulladder_forrc--------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity fulladder_forrc is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
sum : out STD_LOGIC;
carry : out STD_LOGIC);
end fulladder_forrc;
architecture dataflow of fulladder_forrc is
begin
sum<= a xor b xor c;
carry<= ((a xor b) and c) or (a and b);
end dataflow;

OUTPUT:

CONCLUSION:

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