EXPERIMENT NO.

: DATE :

ADDERS AND SUBTRACTORS

AIM : VHDL programs for half adder, full adder , half subtractor , full subtractor

SOFTWARE REQUIRED: ModelSim

THEORY:

Half adder : A half-adder is a combinational logic circuit that adds two single-bit binary numbers (A
and B), producing a sum (S) and a carry-out (C) bit. It's built using an XOR gate for the sum and an
AND gate for the carry.

Full adder: Full Adder is the adder that adds three inputs and produces two outputs. The first two
inputs are A and B and the third input is an input carry as C-IN. The output carry is designated as C-
OUT and the normal output is designated as S which is SUM.

Half subtractor: A half subtractor is a digital circuit that performs binary subtraction of two single-bit
numbers, producing a difference (D) and a borrow (B) output.
Full subtractor: A full subtractor is a digital circuit that performs subtraction of three binary
digits. It's a combinational circuit, which means its outputs depend only on its current inputs.

VHDL CODE WITH TESTBENCH:

Half adder

Dataflow-----

entity halfadder is
port(a,b:in bit;
sum,carry:out bit);
end halfadder;
architecture dataflow of halfadder is
begin
sum<= a xor b;
carry<= a and b;
end dataflow;

structural-----

entity halfadder is
Port ( a : in bit;
b : in bit;
sum : out bit;
carry : out bit);
end halfadder;
architecture Structural of halfadder is
component xorgate is
Port ( a, b : in bit;
y : out bit);
end component;
component andgate is
Port ( a, b : in bit;
y : out bit);
end component;
 begin
X2: xorgate port map ( a => a, b => b, y => sum );
A2: andgate port map ( a=> a, b => b, y => carry );
end Structural;

Testbench-----

entity testhalfadder is
end testhalfadder;
architecture abc of testhalfadder is
component halfadder
port(a,b:in bit;sum,carry:out bit);
end component;
signal a,b,sum,carry:bit;
begin
i1: halfadder port map(a,b,sum,carry);
process
begin
a<='0'; b<='0'; wait for 2 ns;
a<='0'; b<='1'; wait for 2 ns;
a<='1'; b<='0'; wait for 2 ns;
a<='1'; b<='1'; wait for 2 ns;
end process;
end abc;

2. Full adder
Dataflow---
entity fulladder is
port(a,b,c:in bit;sum,carry:out bit);
end fulladder;
architecture dataflow of fulladder is
begin
sum<= a xor b xor c;
carry<= ((a xor b) and c) or (a and b);
end dataflow;

structural----

entity fulladder is
Port ( a : in bit;
b : in bit;
c : in bit;
sum : out bit;
carry : out bit);
end fulladder;
architecture Structural of fulladder is
component xorgate is
Port ( a, b : in bit;
y : out bit);
end component;
component andgate is
Port ( a, b : in bit;
y : out bit);
end component;
component orgate is
Port ( a, b : in bit;
y : out bit);
end component;
signal out1,out2,out3:bit;
begin
X1: xorgate port map ( a => a, b => b, y => out1 );
X2: xorgate port map ( a=> out1, b=> c, y => sum );
A1: andgate port map (a=> a, b => b, y => out2 );
A2: andgate port map ( a=> out1, b => c, y=> out3 );
O1: orgate port map ( a => out2, b=> out3, y => carry );
end Structural;

testbench-----

entity testfulladder is
end testfulladder;
architecture abc of testfulladder is
component fulladder
port(a,b,c:in bit;sum,carry:out bit);
end component;
signal a,b,c,sum,carry:bit;
begin
i1: fulladder port map(a,b,c,sum,carry);
process
begin
a<='0'; b<='0';c<='0';wait for 2 ns;
a<='0'; b<='0';c<='1'; wait for 2 ns;
a<='0'; b<='1';c<='0'; wait for 2 ns;
a<='0'; b<='1';c<='1'; wait for 2 ns;
a<='1'; b<='0';c<='0'; wait for 2 ns;
a<='1'; b<='0';c<='1'; wait for 2 ns;
a<='1'; b<='1';c<='0'; wait for 2 ns;
a<='1'; b<='1';c<='1'; wait for 2 ns;
end process;
end abc;
3. Half subtractor
Dataflow----
entity halfsubtractor is
port(a,b:in bit;diff,borrow:out bit);
end halfsubtractor;
architecture dataflow of halfsubtractor is
begin
diff<= a xor b;
borrow<= (not a) and b;
end dataflow;

structural-----

entity halfsubtractor is
Port ( a : in bit;
b : in bit;
diff : out bit;
borrow : out bit);
end halfsubtractor;
architecture Structural of halfsubtractor is
component xorgate is
Port ( a,b : in bit;
y : out bit);
end component;
component andgate is
Port ( a, b : in bit;
y: out bit);
end component;
component notgate is
Port ( a : in bit;
y: out bit);
end component;
signal out1: bit;
begin
X1: xorgate port map ( a => a, b=> b, y => diff );
N1: notgate port map (a=> a, y=> out1 );
A1: andgate port map ( a => out1, b => b, Y => borrow );
end Structural;

testbench--------

entity testhalfsubtractor is
end testhalfsubtractor;
architecture abc of testhalfsubtractor is
component halfsubtractor
port(a,b:in bit;diff,borrow:out bit);
end component;
signal a,b,diff,borrow:bit;
begin
i1: halfsubtractor port map(a,b,diff,borrow);
process
begin
a<='0'; b<='0'; wait for 2 ns;
a<='0'; b<='1'; wait for 2 ns;
a<='1'; b<='0'; wait for 2 ns;
a<='1'; b<='1'; wait for 2 ns;
end process;
end abc;

4. Full subtractor
Dataflow -------
entity fullsubtractor is
port(a,b,bin:in bit;diff,borrow:out bit);
end fullsubtractor;
architecture dataflow of fullsubtractor is
begin
diff<= a xor b xor bin;
borrow<= ((a xor b) and bin) or ((not a) and b);
end dataflow;

structural-----

entity fullsubtractor is
Port ( a : in bit;
b : in bit;
bin : in bit;
diff : out bit;
borrow : out bit);
end fullsubtractor;
architecture Structural of fullsubtractor is
component xorgate is
Port ( a,b : in bit;
y : out bit);
end component;
component andgate is
Port ( a,b : in bit;
y : out bit);
end component;
component orgate is
Port ( a,b : in bit;
y : out bit);
end component;
component notgate is
Port ( a: in bit;
y : out bit);
end component;
signal out1, out2, out3, out4: bit;
begin
X1: xorgate port map ( a => a, b => b, y=> out1 );
X2: xorgate port map ( a => out1, b => bin, y => diff);
N1: notgate port map ( a=> a, y=> out2 );
A1: andgate port map ( a => out2, b=> out3, y => out4 );
O1: orgate port map ( a=> b, b => bin, y => out3 );
A2: andgate port map ( a => b, b=> bin, y=> out5 );
O2: orgate port map ( a => out4, B => out5, Y => borrow);
end Structural;

testbench-----

entity testfullsubtractor is
end testfullsubtractor;
architecture abc of testfullsubtractor is
component fullsubtractor
port(a,b,bin:in bit;diff,borrow:out bit);
end component;
signal a,b,bin,diff,borrow:bit;
begin
i1: fullsubtractor port map(a,b,bin,diff,borrow);
process
begin
a<='0'; b<='0';bin<='0';wait for 2 ns;
a<='0'; b<='0';bin<='1';wait for 2 ns;
a<='0'; b<='1';bin<='0';wait for 2 ns;
a<='0'; b<='1';bin<='1';wait for 2 ns;
a<='1'; b<='0';bin<='0';wait for 2 ns;
a<='1'; b<='0';bin<='1';wait for 2 ns;
a<='1'; b<='1';bin<='0';wait for 2 ns;
a<='1'; b<='1';bin<='1';wait for 2 ns;
end process;
end abc;
OUTPUT:
1. Half adder

2. Full adder

3. Half subtractor
 4. Full subtractor

CONCLUSION: