VII Latin American Symposium on Circuits and Systems (LASCAS) 2016

A 32-bit RISC-V AXI4-lite bus-based

Microcontroller with 10-bit SAR ADC
Ckristian Duran, Luis Rueda D., Giovanny Castillo, Anderson Agudelo, Camilo Rojas,
Luis Chaparro, Harry Hurtado, Juan Romero, Wilmer Ramirez,
Hector Gomez, Javier Ardila, Luis Rueda, Hugo Hernandez, Jose Amaya and Elkim Roa
Design Group of Integrated Systems CIDIC, Universidad Industrial de Santander, Bucaramanga, Colombia
[email protected], [email protected]

Abstract—In this paper a complete implementation and design order to explore all the status of the peripherals while the
of a fully-synthesized 32-bit microcontroller in a 130nm CMOS microprocessor is still executing its program.
technology is presented. This is the first microcontroller featuring
the open source RISC-V instruction set all mounted through II. RISC-V
AXI4-Lite and APB buses for communication process. The
microcontroller contains a 10-bit SAR ADC, a 12-bit DAC, an RISC-V is a new open instruction set architecture (ISA)
8-bit GPIO module, a 4kB-RAM, an SPI AXI slave interface for designed by the Berkeley Architecture Group with the aim
output verification, and an SPI APB slave interface for checking to support architecture research and education [1]. RISC-V
the correct behavioral of the APB bridge. All peripherals are is fully available to public and has advantages such as a
controlled by a RISC-V and an SPI AXI master interface that is smaller footprint size, support for highly-parallel multi-core
used for programming the device and checking the data flowing
through all the slaves. A total power density is reported as or many-core implementations [2], variable-length instructions
167µW/MHz and the area for this RISC-V microcontroller has to support an optional dense instruction, and energy efficient.
a reduced footprint of 798µm×484µm. Moreover, RISC-V presents improvements in different charac-
teristics over another open ISAs as shown the comparison in
I. INTRODUCTION the Table I.

Many commercial microcontrollers have been built to suit TABLE I

different requirements featuring many private-and-licensed in- C OMPARISON OF THE O PEN ISA
struction sets. Licensed instruction sets and microprocessor PARAMETER/ISA SPARCV8 OpenRISC RISC-V
cores restrict the process of modifying the core for different BASE+EXT NO NO YES
purposes such as improving performance and adapting it to Compact Code NO NO YES
Quad FP NO NO YES
specific applications. 32-bit YES YES YES
RISC-V is a new open ISA aimed to support architecture 64-bit NO YES YES
research and education [1]. It is fully available to the public 128-bit NO NO YES
and can replace ARM microprocessors because is comparable GCC YES YES YES
LLVM YES YES YES
fast and has a small footprint size. RISC-V features an instruc- 32-bit YES YES YES
tion set easy to migrate empowering a developer community
to work on this new architecture. Recently, in [2] and [3]
processors are reported capable of running linux using a RISC- 31 76
0 bit
25 24 20 19 15 14 12 11

V instruction set. However, up to date there has not been any funct7 rs2 rs1 funct3 rd OPCODE R-type
reported work with of a small footprint RISC-V core for low- imm[11:0] rs1 funct3 rd OPCODE I-type
power microcontroller applications.
We are presenting the implementation of the first reported imm[11:5] rs2 rs1 funct3 imm[4:0] OPCODE S-type
32-bit RISC-V based microcontroller (mRISC-V). Our imple-
mentation and design is equivalent to commercial microcon- imm[31:12] rd OPCODE U-type
trollers implemented with an ARM-M0 core. Features of this Fig. 1. RISC-V base instruction formats
microcontroller are: AXI4-Lite and APB buses for interfac-
ing communication between the core and all the peripherals The base ISA is clean and suitable for direct hardware
attached to it, a 4kB-RAM, Serial Peripheral Interface (SPI) implementation, the instructions of RISC-V are similar to
slaves for output, a GPIO module, a SAR Analog-to-Digital other RISC instructions set such as OpenRISC. The Fig.
converter and a Digital-to-Analog converter. The circuit was 1 shows the four core instruction formats (R,I,S,U). R-type
designed using 130nm CMOS technology and tested using format is used for several arithmetic instructions with one or
an efficient test algorithm in bus and using RISC-V tool- two source operands and for the atomic memory operation
chain. In addition, a master SPI has been implemented in (AMO) instructions that perform read-modify-write operations
for multiprocessor synchronization. In addition, R-type is used

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 VII Latin American Symposium on Circuits and Systems (LASCAS) 2016

RISC-V
INSTRUCTIONS ALU Registers
Instructin
Decoder

SPI
Multiplier PCPI RISC-V Master

Controller
Memory
R-type S-type I-type U-type

* Aritmetic *System IRQ Admin

instructions * Store instructions * JAL
*AMO instructions Instructions *Load instructions Instructions
*Computational *Computational * Immediate
Instructions Instructions Instructions
REG-REG REG-immediate AXI4-Lite

Fig. 2. RISC-V Instructions

APB Bridge

for computational instruction register-register. I-type format is ADC DAC GPIO RAM
SPI SPI
used for system instructions to access system functionality that 10-bit 12-bit 8 pins 4 KB
Slave 10 MHz
Slave
might require privileged access and computational instructions
register-immediate. Load and store instructions transfer a value
between the registers and memory. Loads are encoded in the Fig. 3. mRISC-V block diagram.
I-type format and stores are S-type. U-type format is used for
JAL instructions or immediate instructions as LUI (load upper
data channels of 32-bit and other necessary control signals for
immediate) and AUIPC (add upper immediate to pc), see Fig.
communication between Masters (SPI M, RISC-V) and slaves
2. All formats are fixed 32-bit in length, and keeps the source
(RAM, SPI S, APB) [5].
(rs1 and rs2) and destination (rd) registers at the same position
According to the AXI4 specification, communication be-
to simply decoding, for all formats the bit 31 is the sign bit.
tween the masters and the slaves must be done through
RISC-V architecture contains an Arithmetic Logic Unit
an Interconnect module. For this application the AXI4-Lite
(ALU), registers, past memory and future memory, an inter-
interconnect has been implemented following specification.
rupt system, an instruction decoder and a Pico co-processor
interface (PCPI) which is connected to a co-processor to do B. SPI Master
multiplications. We have implemented a reduced instruction SPI is used as a master AXI4-Lite interface for controlling
set microcontroller mRISC-V, described in verilog, using a all slaves attached to the core. This interface has a 66-bit
smaller core to promote research and development of the data instruction: 32-bit for data, 32-bit for address and 2-
internet of things. According to [1], the implemented sub-set bit to define an action like write, read; to put the core reset;
of instructions are RV32I Base Integer Instruction Set (all) and check the last request. This is a fully custom design for
and ”M” Standard Extension for Integer Multiplication and debugging and programming purposes.
Division (only MUL[H[SU—U]]).
C. APB
III. M RISC-V ARCHITECTURE
Several types of protocols are available in SoC, which
Implementation of an efficient microcontroller requires a
require a bridge to safely pass the information from one
reliable and fast communication between masters and slaves
type of protocol to another without data loss. The Advance
blocks in the microcontroller. Nowadays, many bus-based
Peripheral Bus (APB) is part of the Advaced Microcontroller
communication architecture standards are found. In this work
Bus Architecture (AMBA) protocol family. This protocol
we are using the AMBA and APB protocols such that we can
determines a low-cost interface that is optimized for minimal
compare with microcontrollers based on ARM-M0 cores. The
power expending and decreased interface complexity used to
architecture of the mRISC-V is shown in Fig. 3.
connect to low-bandwidth peripherals that do not demand the
Slave interfaces are interconnected to the AXI4-Lite or to
high performance of the AXI protocol.
the APB Bridge. Each interface is different but with several
The signal transaction between AXI master and APB slave
similarities for each protocol. Buses are composed of state
are described by:
machines, registers, multiplexers and Hi-Z buffers. Moreover,
• AMBA AXI-Lite signals as described in the AMBA AXI-
the master interface is implemented with a Serial Peripheral In-
terface (SPI). Following sections describe all these interfaces. Lite 4.0 protocol specification. [5]
• AMBA APB signals as described in the AMBA APB 4.0
A. AXI4-Lite protocol specification. [6]
The AMBA AXI4 is an ultra-high performance protocol The APB bridge provides an interface between the high-
bus standard [4] developed by ARM for easy application in speed AXI domain and the low-power APB domain. It’s
small scale SoCs. AXI4 has different forms to be implemented seen as slave on AXI but as a master on APB. To run
and this work uses the AXI4-Lite protocol, which has two a process of writing or reading transfers on the AXI bus

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 VII Latin American Symposium on Circuits and Systems (LASCAS) 2016

are converted into corresponding transfers on the APB. This BOOSTTRAPED

conversion is described in verilog applying the respective
protocol specifications. Since its execution is not pipelined,
wait states and response signals of protocol are added during
transfers to and from the APB when the AXI must wait for CAPACITIVE VIN_N_ANALOG
the APB protocol. DAC_1
The APB bridge is responsible for converting the APB
signals corresponding AXI signals. The APB bridge acts
as master in APB module and all transactions initiated by CAPACITIVE
the AXI masters. Whenever AXI master tries to access a DAC_2 VIN_P_ANALOG
slave, it requires completing the handshaking process with the
corresponding slave. When the AXI master wants to start a
process of writing and reading simultaneously in any of the
peripherals, reading takes priority and the writing process can BOOSTTRAPED
take place after completion of the read transaction.
SAR REGISTER DIGITAL DATA OUT
IV. PERIPHERALS
A. GPIO
Fig. 5. SAR ADC block diagram.
General-purpose input/output (GPIO) are crucial for a vari-
ety of microcontroller applications and these pins are used as
digital inputs or outputs. Figure 4 shows the block diagram On the other hand, the DAC implemented is based in a R2R
of communication between the core and the pad, which structure with 12-bit resolution, rail to rail output voltage and
perform the connection of the GPIO with the APB bridge a typical settling time of 100ns.
protocol. This block is controlled by a digital control system V. RESULTS
designed for speed and low power consumption according to
Verification of peripherals has been performed from the
the APB Bridge protocol. The implemented GPIO have slew-
perspective of the RISC-V core and the SPI master. The
rate control capability for output and Schmit-Trigger windows
SPI master is used to program the memory and also can
for input. The 8-port GPIO is able to drive up to 25mA per
read or write on any peripheral attached to the AXI-4 bus
output pin.
and the APB bridge. Fig. 6 shows the used initialization and
verification tasks where signal generation and communications
2.5V
transactions are shown in Fig. 7.
1.2V A methodology is described in verilog which perfom an
automatic verification of random handshake generation in the
AXI master 1 and AXI master 2. As the first step, the AXI
APB master choose a slave, then the transaction type is selected
Bridge (read or write) depending of type transaction that can support
the slave. The data is sent to the bus and the AXI scoreboard
registers of the data flow between the master and the slave.
The data is kept and compared to verify that the transaction is
correct. In case of a violation in the protocol, the verification
process is paused and the error is reported to the prompt.
Fig. 4. GPIO block diagram.

Programming mRISC-V through SPI

B. ANALOG AND DIGITAL CONVERTERS
Execute mRISC-V and wait "OK"
In order to perform analog and digital conversions,
mRISC-V incorporates an analog-to-digital converter (ADC) Test DAC from SPI mRISC-V
and a digital-to-analog converter (DAC) which communicate
Test ADC from SPI async
with APB Bridge through the interface shown in Fig. 3. The execution
ADC type that is implemented is a successive approximation Test GPIO from SPI
register (SAR) and its structure is shown in Fig. 5. The
SAR ADC implemented operates at a maximum sampling Fig. 6. Initialization and testing setup for mRISC-V.
frequency of 10MHz and a resolution of 10-bit for a
differential input. Microcontroller is fully synthesized in 130nm CMOS tech-
nology. Synthesis results are shown in the Table II for each

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 VII Latin American Symposium on Circuits and Systems (LASCAS) 2016

AXI
scoreboard

AXI master
trasaction
RAM
Write read/

AXI4-LITE
get data SPI slave
AXI master 1
DAC
Write read/
get data
ADC

APB
AXI master
trasaction GPIO

AXI master 2
SPI slave
Fig. 8. Final layout for AXI-APB implementation. Area:798µm×484µm

Fig. 7. Testbench architecture.

The proposed mRISC-V is the first designed RISC-V
TABLE II microcontroller with enough peripheral to perform common
P OWER , TIMING AND AREA BREAKOUT OF THE M RISC-V.
microcontroller tasks. Power and area results show that a
Core Power Time Slack Area reduced RISC-V architecture can be used to replace ARM-MO
[nW/MHz] [ps @ 100MHz] [µm2 ] based microcontrollers with similar peformance. Considering
AXI-4 interconnect 5284.66 6093 11830 the advantage of the growing RISC-V community and the
mRISC-V 96952.67 2143 120776
SPI AXI master 13532.69 3998 19627 existing tool-chain and software around this new instruction
AXI-RAM 2617.00 3602 2580 set, the mRISC-V paves the way of future implementations
RAM 18997.73 N/A 168708 for specific and general applications in the world of IoT with
APB TOP 11703.14 3664 23794
SPI AXI slave 2176.93 8085 1899
open source devices.
All 166841.47 1185 349233
R EFERENCES
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peripherals and for whole system with the AXI-APB imple- instruction set manual, volume I: User-level ISA, version 2.0,”
EECS Department, University of California, Berkeley, Tech. Rep. UCB/
mentation. The 4kB RAM module occupies almost the same EECS- 2014-54, May 2014.
area of the sum of the core and peripherals. The highest [2] Y. Lee, A. Waterman, R. Avizienis, H. Cook, C. Sun, V. Stojanovic, and
power consumption density comes from the RISV-V processor. K. Asanovic, “A 45nm 1.3GHz 16.7 double-precision GFLOPS/W RISC-
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B. Nikolic, “A RISC-V vector processor with tightly-integrated switched-
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[6] C. Ma, Z. Liu, and X. Ma, “Design and implementation of apb bridge
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VI. SUMMARY
A fully-synthesized microncontroller based on RISC-V ar-
chitecture on 130nm CMOS technology has been presented.
Many peripherals are included using a proposed methodology
to verify the correct operation. The proposed architecture
shows the interconnection between the RISC-V, the SPI AXI
master, and all the peripherals attached to the AXI4-Lite and
APB buses, explaining details of the implementation.

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